VGA module

`timescale 1ns / 1ps

module vga2(
    input clk,
    input rst_n,
    output hsyncOut,
    output vsyncOut,
    output [2:0] Red,
    output [2:0] Green,
    output [1:0] Blue,
    output [9:0] hCountOut,
    output [9:0] vCountOut,
    input [2:0] RedIn,
    input [2:0] GreenIn,
    input [1:0] BlueIn
    );

    reg divide_by_2;
    reg clock2;
    reg [9:0] hCount;
    reg [9:0] vCount;
    reg [9:0] nextHCount;
    reg [9:0] nextVCount;
    reg hsync;
    reg vsync;
    assign hsyncOut = hsync;
    assign vsyncOut = vsync;
    assign hCountOut = hCount;
    assign vCountOut = vCount;
    wire inRange = hCount < 639 && vCount < 479;

    reg [2:0] RedOut;
    reg [2:0] GreenOut;
    reg [1:0] BlueOut;
    assign Red = RedOut;
    assign Green = GreenOut;
    assign Blue = BlueOut;

    // 100% --> 50%
    always @(posedge clk or negedge rst_n) begin
        if (rst_n == 0) begin
            clock2 <= 0;
        end else begin
            clock2 <= !clock2;
        end
    end

    // 50% --> 25%
    always @(posedge clock2 or negedge rst_n) begin
        if (rst_n == 0) begin
            divide_by_2 = 0;
        end else begin
            divide_by_2 = !divide_by_2;
        end
    end

    always @(posedge divide_by_2 or negedge rst_n) begin
        if (rst_n == 0) begin
            hCount <= 640;
            vCount <= 480;
            nextHCount <= 641;
            nextVCount <= 481;
        end else begin
            hCount <= (hCount >= 799) ? 0 : hCount + 1;
            vCount <= (hCount >= 799) ? ((vCount >= 524) ? 0 : vCount + 1) : vCount;

            nextHCount <= (nextHCount >= 799) ? 0 : hCount + 1;
            nextVCount <= (nextHCount >= 799) ? ((nextVCount >= 524) ? 0 : vCount + 1) : nextVCount;

            vsync <= (vCount >= 490 && vCount < 492);
            hsync <= (hCount >= 656 && hCount < 752);

            RedOut <= inRange ? RedIn : 0;
            GreenOut <= inRange ? GreenIn : 0;
            BlueOut <= inRange ? BlueIn : 0;
        end
    end

endmodule