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- `timescale 1ns/10ps
- typedef enum bit[3:0] {ADD, SUB, MUL, DIV, MOD, POW,
- AND, OR, XOR,
- CONC,
- LLS, LRS,
- ALS, ARS,
- GTQ, EQU} opcode_enum;
- class alu_inputs;
- rand bit [3:0] a_rand, b_rand;
- rand opcode_enum opcode_rand;
- constraint opcode_range
- {
- (opcode_rand == POW) -> b_rand inside {[0:2]};
- }
- endclass
- module alu_tb();
- reg [3:0] a_tb, b_tb;
- reg rst_tb, clk_tb;
- reg [3:0] opcode_tb;
- wire [7:0] _output_tb;
- always
- begin
- clk_tb = 1'b1; #(10);
- clk_tb = 1'b0; #(10);
- end
- alu uut(.a(a_tb), .b(b_tb), .clk(clk_tb), .rst(rst_tb), .opcode(opcode_tb), ._output(_output_tb));
- alu_inputs alu_rand;
- integer i;
- initial
- begin
- alu_rand = new();
- rst_tb = 1;
- @(negedge clk_tb);
- rst_tb = 0;
- @(negedge clk_tb);
- for (i = 0; i < 50; i = i + 1)
- begin
- alu_rand.randomize();
- opcode_tb = alu_rand.opcode_rand;
- a_tb = alu_rand.a_rand;
- b_tb = alu_rand.b_rand;
- @(negedge clk_tb);
- end
- $stop;
- end
- /*task check_result(input [7:0] exp_rslt);
- if(exp_rslt !== _output_tb)
- $display("Incorrect");
- else
- $display("Correct");
- endtask*/
- endmodule
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