HaS5HeM

ALU TB

Jul 1st, 2023
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SystemVerilog 1.24 KB | Source Code | 0 0
  1. `timescale 1ns/10ps
  2.  
  3. typedef enum bit[3:0] {ADD, SUB, MUL, DIV, MOD, POW,
  4.                        AND,  OR, XOR,
  5.                        CONC,
  6.                        LLS, LRS,
  7.                        ALS, ARS,
  8.                        GTQ, EQU} opcode_enum;
  9.  
  10. class alu_inputs;
  11.   rand bit [3:0] a_rand, b_rand;
  12.   rand opcode_enum opcode_rand;
  13.   constraint opcode_range
  14.   {
  15.     (opcode_rand == POW) -> b_rand inside {[0:2]};
  16.   }
  17. endclass
  18.  
  19. module alu_tb();
  20.  
  21.  
  22.  
  23. reg  [3:0] a_tb, b_tb;
  24. reg        rst_tb, clk_tb;
  25. reg  [3:0] opcode_tb;
  26. wire [7:0] _output_tb;
  27.  
  28. always
  29. begin
  30.   clk_tb = 1'b1; #(10);
  31.   clk_tb = 1'b0; #(10);
  32. end
  33.  
  34. alu uut(.a(a_tb), .b(b_tb), .clk(clk_tb), .rst(rst_tb), .opcode(opcode_tb), ._output(_output_tb));
  35.  
  36. alu_inputs alu_rand;
  37.  
  38. integer i;
  39.  
  40. initial
  41. begin
  42.   alu_rand = new();
  43.   rst_tb = 1;
  44.   @(negedge clk_tb);
  45.   rst_tb = 0;
  46.   @(negedge clk_tb);
  47.   for (i = 0; i < 50; i = i + 1)
  48.   begin
  49.     alu_rand.randomize();
  50.     opcode_tb = alu_rand.opcode_rand;
  51.     a_tb = alu_rand.a_rand;
  52.     b_tb = alu_rand.b_rand;
  53.     @(negedge clk_tb);
  54.   end
  55.   $stop;
  56. end
  57.  
  58. /*task check_result(input [7:0] exp_rslt);
  59.   if(exp_rslt !== _output_tb)
  60.     $display("Incorrect");
  61.   else
  62.     $display("Correct");
  63. endtask*/
  64.  
  65. endmodule
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