--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date        : Mon May  2 13:04:37 2016
--Host        : Samsung running 64-bit Ubuntu 15.10
--Command     : generate_target sine_generator_fh.bd
--Design      : sine_generator_fh
--Purpose     : IP block netlist
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sine_generator_fh is
  port (
    clk : in STD_LOGIC;
    data_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    data_request : in STD_LOGIC;
    reset_n : in STD_LOGIC
  );
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of sine_generator_fh : entity is "sine_generator_fh,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=sine_generator_fh,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=2,numReposBlks=2,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,synth_mode=Global}";
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of sine_generator_fh : entity is "sine_generator_fh.hwdef";
end sine_generator_fh;

architecture STRUCTURE of sine_generator_fh is
  component sine_generator_fh_sine_table_0_0 is
  port (
    clk : in STD_LOGIC;
    reset_n : in STD_LOGIC;
    data_request : in STD_LOGIC;
    amplitude : in STD_LOGIC_VECTOR ( 2 downto 0 );
    addr : in STD_LOGIC_VECTOR ( 12 downto 0 );
    data_out : out STD_LOGIC_VECTOR ( 11 downto 0 )
  );
  end component sine_generator_fh_sine_table_0_0;
  component sine_generator_fh_sine_table_controller_0_0 is
  port (
    clk : in STD_LOGIC;
    generate_enable : in STD_LOGIC;
    addr : out STD_LOGIC_VECTOR ( 12 downto 0 );
    amplitude : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  end component sine_generator_fh_sine_table_controller_0_0;
  signal clk_1 : STD_LOGIC;
  signal data_request_1 : STD_LOGIC;
  signal reset_n_1 : STD_LOGIC;
  signal sine_table_0_data_out : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal sine_table_controller_0_addr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal sine_table_controller_0_amplitude : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
  clk_1 <= clk;
  data_out(11 downto 0) <= sine_table_0_data_out(11 downto 0);
  data_request_1 <= data_request;
  reset_n_1 <= reset_n;
sine_table_0: component sine_generator_fh_sine_table_0_0
     port map (
      addr(12 downto 0) => sine_table_controller_0_addr(12 downto 0),
      amplitude(2 downto 0) => sine_table_controller_0_amplitude(2 downto 0),
      clk => clk_1,
      data_out(11 downto 0) => sine_table_0_data_out(11 downto 0),
      data_request => data_request_1,
      reset_n => reset_n_1
    );
sine_table_controller_0: component sine_generator_fh_sine_table_controller_0_0
     port map (
      addr(12 downto 0) => sine_table_controller_0_addr(12 downto 0),
      amplitude(2 downto 0) => sine_table_controller_0_amplitude(2 downto 0),
      clk => clk_1,
      generate_enable => data_request_1
    );
end STRUCTURE;