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- opt 6809
- opt cd
- include const.asm
- cHState equ (R01_HSyncFlag|R01_MuxSelLSB|R01_HSyncIrq) ;R01_HDirection|
- cVState equ (R03_VsyncFlag|R03_MuxSelMSB|R03_VsyncIrq) ;R03_VDirection|
- cScrStart equ 1024
- cScrEnd equ 1536
- org 32000
- lda #$FF
- tfr A,DP ; DP = 0xFF??
- SETDP $FF
- orcc #(cFirqMask|cIrqMask) ; Disable Interrupts ; Disable IRQs
- lda <$01 ;
- ldb <$03 ;
- anda #(^cHState) ; Disable Hsync Interrupt / Clear Flag
- ora #(R01_MuxSelLSB) ; (Sound Source Cassette)
- sta <$01 ; (Sound Source cassette)
- andb #(^cVState) ; Disable Vsync Interrupt / Clear Flag
- stb <$03 ;
- lda <$21
- ldb <$23
- ora #R21_DPolarity ; Output Direction
- sta <$21
- orb #R23_SoundOn ; and Enable Sound
- stb <$23 ;
- ; **************************************************
- ; ************** Setup Initial State ***************
- ; **************************************************
- ; **************************************************
- ; **************** Initial Sync UP *****************
- ; **************************************************
- ;bne SYNCUP ;~03|26 no? then just continue
- SYNCUP: ldx #cScrStart+64 ;~03 start of screen
- ldu #cScrStart ;~03
- clr ,U ;~06
- bra SYNCBYTE ;~03
- @SYNC9BIT: tstb ;~02|17
- bpl @IS1 ;~03|20
- @IS0: lsr <$20 ;~06|06 read 1st sample
- bcc @IS0 ;~03|09
- lsr <$20 ;~06|15
- bcc @IS0 ;~03|18
- lsr <$20 ;~06|24
- bcc @IS0 ;~03|27
- bra @SYNCCHK ;~03|30
- ;;
- @IS1: lsr <$20 ;~06|06 read 1st sample
- bcs @IS1 ;~03|09
- lsr <$20 ;~06|15
- bcs @IS1 ;~03|18
- lsr <$20 ;~06|24
- bcs @IS1 ;~03|27
- bra @SYNCCHK ;~03|30
- ;;
- @SYNCCHK: sta ,X+ ;~06|36 store byte on screen
- cmpx #cScrEnd ;~04|40 reached end of string?
- beq @DOWRAP ;~03|43 yes then go put back on start
- bra @NOWRAP ;~03|46|no? then skip putting back
- @DOWRAP: ldx #cScrStart+64 ;~03|46|yes? then reload to start pos
- @NOWRAP: cmpa #$4B ;~02|48 $4B
- beq @STAGE1 ;~03|51 if char is 4B Assert Stage 1
- tsta ;~02|53 $00
- beq @STAGE2 ;~03|56 if char is 00 Check/Try Stage 2
- inca ;~02|58 $FF
- beq @STAGE3 ;~03|61 if char is FF Check/Try Stage 3
- clr ,U ;~06|67
- bra @SYNCW70 ;~03|70
- ;;
- @STAGE1: tst ,U ;~06|57 check state
- bne @SYNCW60 ;~03|60 non zero than already Stage 1
- inc ,U ;~06|66 Set state to Stage1 (01)
- jmp @SYNCW70,PCR ;~04|70 and go read next byte
- ;;
- @STAGE2: tst ,U ;~06|62 check state
- beq @SYNCW65 ;~03|65 zero? than can't proceed
- tst ,U ;~06|71
- bmi @SYNCW74 ;~03|74
- neg 0,U ;~07|81
- tfr D,D ;~06|87 Set state to Stage2 (FF)
- bra SYNCBYTE ;~03|90 and go read next byte
- ;;
- @STAGE3: tst ,U ;~06|67 check state
- bpl @SYNCW70 ;~03|70 positive? then can't proceed
- jmp START,PCR ;~04|74 Sync finished go read bits :)
- ;;
- @SYNCW60: stx <$FE ;~05|65 +
- @SYNCW65: bra @SYNCW68 ;~03|68 +
- @SYNCW68: nop ;~02|70 +
- @SYNCW70: bita <$FE ;~04|74 +
- @SYNCW74: pshs X,DP ;~08|82 +
- puls X,DP ;~08|90 > wait til 90 cycles
- ;;
- SYNCBYTE: lda #128 ;~02|02 holds byte and rotate signal
- @SYNCBIT: ldb <$20 ;~04|06 read 1st sample
- andb #1 ;~02|08 add carry to sum
- pshs X,Y,D,DP ;~12|20
- puls X,Y,D,DP ;~12|32
- ;;
- lsr <$20 ;~06|08 read 2nd sample
- adcb #0 ;~02|10 add carry to sum
- pshs X,Y,D ;~11|20 +
- puls X,Y,D ;~11|32 > wait till 30+2 cycles
- ;;
- lsr <$20 ;~06|08 read 3rd sample
- adcb #254 ;~02|10 add carry to sum
- rora ;~02|12 rotate into byte buffer
- bcs @SYNC9BIT ;~03|15 rotated 8 bits? then go sync
- pshs X ;~07|22
- puls X ;~07|29
- bra @SYNCBIT ;~03|32 go read next bit
- ; **************************************************
- ; ******** in Sync can start reading bytes *********
- ; **************************************************
- ; |74 <- jump from there
- START: ldx #cScrStart ;~03|77 start screen position
- ldd #$3071 ;~03|80 chars for 0,1
- pshs D ;~07|87 store chars
- bra NEXTBYTE ;~03|90 align to 90 cycles
- ;;
- NEXTBYTE: lda #128 ;~02|02 holds byte and rotate signal
- @NEXTBIT: ldb <$20 ;~04|06 read 1st sample
- andb #1 ;~02|08 add carry to sum
- pshs X,Y,D,DP ;~12|20
- puls X,Y,D,DP ;~12|32
- ;;
- lsr <$20 ;~06|08 read 2nd sample
- adcb #0 ;~02|10 add carry to sum
- pshs X,Y,D ;~11|20 +
- puls X,Y,D ;~11|32 > wait till 30+2 cycles
- ;;
- lsr <$20 ;~06|08 read 3rd sample
- adcb #254 ;~02|10 add carry to sum
- rora ;~02|12 rotate into byte buffer
- bcs LASTBIT ;~03|15 rotated 8 bits? then go sync
- pshs X ;~07|22
- puls X ;~07|29
- bra @NEXTBIT ;~03|32 go read next bit
- ; ==== AND SO START READING NORMAL BITS ====
- LASTBIT: tstb ;~02|17
- bpl @IS1 ;~03|20
- @IS0: lsr <$20 ;~06|06 read 1st sample
- bcc @IS0 ;~03|09
- lsr <$20 ;~06|15
- bcc @IS0 ;~03|18
- lsr <$20 ;~06|24
- bcc @IS0 ;~03|27
- bra @GOTBYTE ;~03|30
- ;;
- @IS1: lsr <$20 ;~06|06 read 1st sample
- bcs @IS1 ;~03|09
- lsr <$20 ;~06|15
- bcs @IS1 ;~03|18
- lsr <$20 ;~06|24
- bcs @IS1 ;~03|27
- bra @GOTBYTE ;~03|30
- ;;
- @GOTBYTE: tsta ;~02|32 char is null?
- bne @DOWRITE ;~03|35 yes? then skip it
- lda #8 ;~02|37 waits 9*5 cycles later
- clr 0,X ;~07|44
- @REUSE1: bra @NOWRAP ;~03|47 go wait for next byte
- ;;
- @DOWRITE: sta ,X+ ;~06|41 store byte on screen
- lda #6 ;~02|43 waits 6*5 cycles later
- bita <$FF ;~04|47 plus 4 cycles waiting to align
- cmpx #cScrEnd ;~04|51 reached end of string?
- bne @REUSE1 ;~03|54 yes then go put back on start
- ldx #cScrStart ;~03|57 yes? then reload to start pos
- ;;
- @NOWRAP: deca ;~02|?? +
- bne @NOWRAP ;~03|87 > sync to 85
- bra NEXTBYTE ;~03|90 go read another byte
- end 32000
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