module seconds_counter(
	input clk,
	output secsBus,
	input rst
);
	reg [15:0] cycleCnt = 0;
	reg [9:0] timeCnt = 0;
	reg secsPassed = 0;

	parameter CYCLES_PER_10ms = 50_000/2;
	parameter TICKS_PER_SEC = 1000;

	always @(posedge clk) begin
		if (cycleCnt == CYCLES_PER_10ms - 1) begin
			cycleCnt <= 0;
			timeCnt <= timeCnt + 1;
			if (timeCnt == TICKS_PER_SEC - 1) begin
				timeCnt <= 0;
				secsPassed <= ~secsPassed;
			end
		end else begin
			cycleCnt <= cycleCnt + 1;
		end
	end
	assign secsBus = secsPassed;
endmodule

module minutes_counter(
    input clk,
    output [5:0] minsBus,
    input rst
);
    wire secsBus;
    reg [5:0] minsPassed = 0;

    parameter SECS_IN_MIN = 5;

    reg secsRst;


    seconds_counter sec_counter (
        .clk(clk),
        .secsBus(secsBus),
        .rst(rst)
    );

    reg [5:0] secsCnt = 0;
    always @(posedge secsBus) begin

    	if (secsCnt == SECS_IN_MIN) begin
    		minsPassed = minsPassed + 1;
    		secsCnt = 0;
    	end else begin
    		secsCnt = secsCnt + 1;
    	end
    end

    assign minsBus = minsPassed;
endmodule

module hex(

);

endmodule