module matrix_multiplier_8x8 (
  input wire clk,
  input wire rst,
  input wire [63:0] matrix_A,
  input wire [63:0] matrix_B,
  output wire [63:0] matrix_C
);

reg [31:0] temp_result [0:7][0:7];
reg [31:0] matrix_C_ [0:7][0:7];

reg [2:0] i, j, k;
reg multiply_done;

always @(posedge clk) begin
  if (rst) begin
    i <= 0;
    j <= 0;
    k <= 0;
    multiply_done <= 0;
  end
  else begin
    if (!multiply_done) begin
      if (k < 8) begin
        temp_result[i][j] <= temp_result[i][j] + matrix_A[i * 8 + k] * matrix_B[k * 8 + j];
        k <= k + 1;
      end
      else if (j < 7) begin
        k <= 0;
        j <= j + 1;
      end
      else if (i < 7) begin
        k <= 0;
        j <= 0;
        i <= i + 1;
      end
      else begin
        multiply_done <= 1;
      end
    end
    else begin
      if (i < 7) begin
        j <= 0;
        i <= i + 1;
      end
      else begin
        i <= 0;
        multiply_done <= 0;
      end
    end
  end
end

always @(posedge clk or posedge rst) begin
  if (rst) begin
    i = 0;
    j = 0;
    begin: reset_loop
      if (i < 8) begin
        if (j < 8) begin
          temp_result[i][j] <= 32'h0;
          matrix_C_[i][j] <= 32'h0;
          j = j + 1;
        end
        else begin
          j = 0;
          i = i + 1;
        end
      end
      else begin
        i = 0;
      end
    end
  end
  else if (multiply_done) begin
    i = 0;
    j = 0;
    begin: transfer_output_loop
      if (i < 8) begin
        if (j < 8) begin
          matrix_C_[i][j] <= temp_result[i][j];
          j = j + 1;
        end
        else begin
          j = 0;
          i = i + 1;
        end
      end
      else begin
        i = 0;
      end
    end
  end
end


endmodule