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- library ieee;
- use ieee.std_logic_1164.all;
- use IEEE.NUMERIC_STD.ALL;
- entity sign_extender is
- port (
- instruction_input : in std_logic_vector(31 downto 0);
- extended_output : out std_logic_vector(63 downto 0)
- -- debug_output_64 : out std_logic_vector(63 downto 0);
- -- debug_output_11 : out std_logic_vector(10 downto 0);
- -- debug_output_bool : out boolean
- );
- end entity sign_extender;
- architecture Dataflow of sign_extender is
- -- Handy Constants
- constant ADD_R : std_logic_vector(10 downto 0) := "10001011000"; -- 11 bits
- constant SUB_R : std_logic_vector(10 downto 0) := "11001011000"; -- 11 bits
- constant LSL_R : std_logic_vector(10 downto 0) := "11010011011"; -- 11 bits
- constant LSR_R : std_logic_vector(10 downto 0) := "11010011010"; -- 11 bits
- constant AND_R : std_logic_vector(10 downto 0) := "10001010000"; -- 11 bits
- constant OR_R : std_logic_vector(10 downto 0) := "10101010000"; -- 11 bits
- constant LDUR_D : std_logic_vector(10 downto 0) := "11111000010"; -- 11 bits
- constant STUR_D : std_logic_vector(10 downto 0) := "11111000000"; -- 11 bits
- constant BR_R : std_logic_vector(10 downto 0) := "11010110000"; -- 11 bits
- constant ADDI_I : std_logic_vector(9 downto 0) := "1001000100"; -- (10 downto 1) bits
- constant SUBI_I : std_logic_vector(9 downto 0) := "1101000100"; -- (10 downto 1) bits
- constant MOVZ_IM : std_logic_vector(8 downto 0) := "110100101"; -- (10 downto 2) bits
- constant CBNZ_CB : std_logic_vector(7 downto 0) := "10110101"; -- (10 downto 3) bits
- constant CBZ_CB : std_logic_vector(7 downto 0) := "10110100"; -- (10 downto 3) bits
- constant B_B : std_logic_vector(5 downto 0) := "000101"; -- (10 downto 5) bits
- -- Handy signal
- signal Opcode : std_logic_vector(10 downto 0);
- begin
- Opcode <= instruction_input(31 downto 21);
- -- debug_output_11 <= Opcode ;
- -- debug_output_64 <= std_logic_vector(resize(signed(instruction_input(23 downto 5)),extended_output'length));
- -- debug_output_bool <= Opcode(10 downto 3) = CBZ_CB;
- -- R Format
- extended_output <= std_logic_vector(resize(signed(instruction_input(15 downto 10)),extended_output'length)) when Opcode = ADD_R or
- Opcode = SUB_R or
- Opcode = LSL_R or
- Opcode = LSR_R or
- Opcode = AND_R or
- Opcode = OR_R or
- Opcode = BR_R else
- -- I Format
- std_logic_vector(resize(signed(instruction_input(21 downto 10)),extended_output'length)) when Opcode(10 downto 1) = ADDI_I or
- Opcode(10 downto 1) = SUBI_I else
- -- D Format pos
- std_logic_vector(resize(signed(instruction_input(20 downto 12)),extended_output'length)) when (Opcode = LDUR_D or Opcode = STUR_D) and
- (instruction_input(11 downto 10) = "01") else
- -- D Format neg
- std_logic_vector( not (resize( signed(instruction_input(20 downto 12)),extended_output'length)) + to_signed(1, extended_output'length)) when (Opcode = LDUR_D or Opcode = STUR_D) and
- (instruction_input(11 downto 10) = "10") else
- -- B Format
- std_logic_vector(resize(signed(instruction_input(25 downto 0)),extended_output'length)) when Opcode(10 downto 5) = B_B else
- -- CB Format
- std_logic_vector(resize(signed(instruction_input(23 downto 5)),extended_output'length)) when Opcode(10 downto 3) = CBNZ_CB or
- Opcode(10 downto 3) = CBZ_CB else
- -- IM Format
- std_logic_vector(resize(signed(instruction_input(20 downto 5)),extended_output'length)) when Opcode(10 downto 2) = MOVZ_IM
- -- Unknown
- else (others => 'X');
- end Dataflow;
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