sadd

module sadd(
    input clk, rst,
    input x, y,
    output reg z
);
    localparam S0 = 0, S1 = 1;
    reg st, st_nxt;
    always @(*)
        case (st)
        S0:
            if (x & y) st_nxt = S1;
            else st_nxt = S0;
        S1:
            if ((~x) & (~y)) st_nxt = S0;
            else st_nxt = S1;
        endcase

    always @(*) begin
        z = 0;
        case (st)
        S0:
            if (x ^ y) z = 1;
        S1:
            if (x ~^ y) z = 1;
        endcase
    end

    always @(posedge clk, negedge rst)
        if (!rst) st <= S0;
        else st <= st_nxt;
endmodule


module sadd_tb;
    reg clk, rst, x, y;
    wire z;
    sadd inst(.clk(clk), .rst(rst), .x(x), .y(y));
    localparam CLK_PERIOD = 100, RST_PULSE = 10, CLK_CYCLES = 5;
    initial begin
        clk = 0;
        repeat (2*CLK_CYCLES)
            #(CLK_PERIOD/2) clk=~clk;
    end
    initial begin
        rst = 0;
        #(RST_PULSE) rst = 1;
    end
    initial begin
        {x,y}='b01;
        #(1*CLK_PERIOD) {x,y}='b10;
        #(1*CLK_PERIOD) {x,y}='b11;
        #(1*CLK_PERIOD) {x,y}='b00;
    end

endmodule