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aidanozo

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Nov 5th, 2024
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  1. module moore_fsm(
  2.     output reg parity,
  3.     input clk,
  4.     input reset,
  5.     input x);
  6.    
  7.     reg state, next_state;
  8.     parameter S0=0;
  9.     parameter S1=1;
  10.  
  11.      // Partea secvențială
  12.     always @(posedge clk or negedge reset)
  13.         if (!reset)
  14.             state <= S0;
  15.         else
  16.             state <= next_state;
  17.  
  18.     always @(*) begin
  19.         case(state)
  20.             S0: begin
  21.                 parity = 0;
  22.                 if (x)
  23.                     next_state = S1;
  24.                 else
  25.                     next_state = S0;
  26.             end
  27.             S1: begin
  28.                 parity = 1;
  29.                 if(!x)
  30.                     next_state = S1;
  31.                 else
  32.                     next_state = S0;
  33.             end
  34.         endcase
  35.     end
  36. endmodule
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