library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY funkcija IS port(
    input : in std_logic_vector (0 to 2);
    output : out std_logic_vector (5 downto 0));
END funkcija;

ARCHITECTURE arch OF funkcija IS
    signal a,b,c: std_logic;
BEGIN
    a <= input(0);
    b <= input(1);
    c <= input(2);

    output(0) <= (not a and not c) or (not c and not b) or (not a and not b);
    output(1) <= (a and c) or (a and not b) or (not b and c);
    output(2) <= (a and not b) or (a and not c) or (not c and not b);
    output(3) <= c or a or not b;
    output(4) <= c or (not a and b);
    output(5) <= (a and not c) or (b and c);

END arch;