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TehnoZet2

ListingAX6000

TehnoZet2
Nov 3rd, 2024
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  1. ▒
  2. F0: 102B 0000
  3. FA: 1040 0000
  4. FA: 1040 0000 [0200]
  5. F9: 0000 0000
  6. V0: 0000 0000 [0001]
  7. 00: 0000 0000
  8. BP: 2400 0041 [0000]
  9. G0: 1190 0000
  10. EC: 0000 0000 [1000]
  11. T0: 0000 0228 [010F]
  12. Jump to BL
  13.  
  14. NOTICE: BL2: v2.6(release):8b2bdeec64-dirty
  15. NOTICE: BL2: Built : 09:23:25, Jan 30 2023
  16. INFO: BL2: Doing platform setup
  17. NOTICE: WDT: disabled
  18. NOTICE: CPU: MT7986 (2000MHz)
  19. NOTICE: EMI: Using DDR4 settings
  20.  
  21. before ctrl3 = 0x0
  22. clear request & ack
  23. after ctrl3 = 0x0
  24.  
  25. DVFSRC_SUCCESS 0
  26.  
  27. dump toprgu registers data:
  28. 1001c000 | 00000000 0000ffe0 00000000 00000000
  29. 1001c010 | 00000fff 00000000 00800000 00000000
  30. 1001c020 | 00000000 00000000 00000000 00000000
  31. 1001c030 | 003c0003 003c0003 00000000 00000000
  32. 1001c040 | 00000000 00000000 00000000 00000000
  33. 1001c050 | 00000000 00000000 00000000 00000000
  34. 1001c060 | 00000000 00000000 00000000 00000000
  35. 1001c070 | 00000000 00000000 00000000 00000000
  36. 1001c080 | 00000000 00000000 00000000 00000000
  37.  
  38. dump drm registers data:
  39. 1001d000 | 00000000 00000000 00000000 00000000
  40. 1001d010 | 00000000 00000000 00000000 00000000
  41. 1001d020 | 00000000 00000000 00000000 00000000
  42. 1001d030 | 00a083f1 000003ff 00100000 00000000
  43. 1001d040 | 00000000 00000000 00020303 000000ff
  44. 1001d050 | 00000000 00000000 00000000 00000000
  45. 1001d060 | 00000002 00000000 00000000 00000000
  46. drm: 500 = 0x8
  47. [DDR Reserve] ddr reserve mode not be enabled yet
  48. Save DRM_DEBUG_CTL(0xa083f1)
  49. DRM_LATCH_CTL : 0x27e71
  50. DRM_LATCH_CTL2: 0x200a0
  51. drm_update_reg: 0, bits: 0x8000, addr: 0x1001d030, val: 0xa003f1
  52. drm_update_reg: 0, bits: 0x80000, addr: 0x1001d030, val: 0xa003f1
  53. drm_update_reg: 0, bits: 0x200, addr: 0x1001d034, val: 0x1ff
  54. drm_update_reg: 0, bits: 0x200000, addr: 0x1001d034, val: 0x1ff
  55. drm_update_reg: 0, bits: 0x100, addr: 0x1001d034, val: 0xff
  56. MTK_DRM_DEBUG_CTL : 0xa003f1
  57. MTK_DRM_DEBUG_CTL2: 0xff
  58. drm_update_reg: 0, bits: 0x4000, addr: 0x1001d030, val: 0xa003f1
  59. DRM DDR reserve mode FAIL! a083f1
  60. DDR RESERVE Success 0
  61. drm_update_reg: 0, bits: 0x2000, addr: 0x1001d030, val: 0xa003f1
  62. drm_update_reg: 0, bits: 0x1000, addr: 0x1001d030, val: 0xa003f1
  63. [DRAM] into mt_set_emi
  64. [EMI] ComboMCP not ready, using default setting
  65.  
  66. Init_DRAM:2169: init PCDDR4 dram Start
  67. [MD32_INIT] in c code >>>>>>
  68. [MD32_INIT] 3
  69. [MD32_INIT] 4
  70. [MD32_INIT] 5
  71. [MD32_INIT] 6
  72. [MD32_INIT] V22 add 1
  73. [MD32_INIT] V22 add 1 end
  74. [MD32_INIT] 7
  75. [MD32_INIT] 8
  76. [MD32_INIT] 9
  77. [MD32_INIT] 10
  78. [MD32_INIT] 11
  79. [MD32_INIT] 12
  80. [MD32_INIT] 13
  81. [MD32_INIT] 14
  82. [MD32_INIT] 15
  83. [MD32_INIT] 16
  84. [MD32_INIT] 17
  85. [MD32_INIT] 18
  86. [MD32_INIT] 19
  87. [MD32_INIT] 20
  88. [MD32_INIT] 21
  89. [MD32_INIT] 22
  90. [MD32_INIT] 23
  91. [MD32_INIT] 28
  92. [MD32_INIT] 29
  93. [MD32_INIT] 30 for RTMRW, if have
  94. [MD32_INIT] in c code <<<<<<
  95. [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
  96.  
  97.  
  98. [Bian_co] ETT version 0.0.0.1
  99. dram_type 4, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=136
  100.  
  101. Read voltage for 1600, 0
  102. Vio18 = 0
  103. Vcore = 0
  104. Vdram = 0
  105. Vddq = 0
  106. Vmddr = 0
  107. == DRAMC_CTX_T ==
  108. support_channel_num: 1
  109. channel: 0
  110. support_rank_num: 1
  111. rank: 0
  112. freq_sel: 22
  113. shu_type: 0
  114. dram_type: 4
  115. dram_fsp: 0
  116. odt_onoff: 1
  117. DBI_R_onoff: 0, 0
  118. DBI_W_onoff: 0, 0
  119. data_width: 16
  120. test2_1: 0x55000000
  121. test2_2: 0xaa000100
  122. frequency: 1600
  123. freqGroup: 1600
  124. u1PLLMode: 0
  125. dram type 6
  126. ===============================================================================
  127. Dram Type= 4, Freq= 1600, CH_0, rank 0
  128. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  129. ===============================================================================
  130. OCD DRVP=0 ,CALOUT=0
  131. OCD DRVP=1 ,CALOUT=0
  132. OCD DRVP=2 ,CALOUT=0
  133. OCD DRVP=3 ,CALOUT=0
  134. OCD DRVP=4 ,CALOUT=0
  135. OCD DRVP=5 ,CALOUT=0
  136. OCD DRVP=6 ,CALOUT=0
  137. OCD DRVP=7 ,CALOUT=0
  138. OCD DRVP=8 ,CALOUT=0
  139. OCD DRVP=9 ,CALOUT=1
  140.  
  141. OCD DRVP calibration OK! DRVP=9
  142.  
  143. OCD DRVN=0 ,CALOUT=1
  144. OCD DRVN=1 ,CALOUT=1
  145. OCD DRVN=2 ,CALOUT=1
  146. OCD DRVN=3 ,CALOUT=1
  147. OCD DRVN=4 ,CALOUT=1
  148. OCD DRVN=5 ,CALOUT=1
  149. OCD DRVN=6 ,CALOUT=0
  150.  
  151. OCD DRVN calibration OK! DRVN=6
  152.  
  153. [SwImpedanceCal] DRVP=9, DRVN=6
  154. freq_region=0, Reg: DRVP=9, DRVN=6, ODTP=6
  155. MEM_TYPE=6, freq_sel=22
  156. [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  157. PCDDR4 DRAM CONFIGURATION
  158. ===================================
  159. CWL = 0x7
  160. RTT_NORM = 0x6
  161. CL = 0xb
  162. AL = 0x0
  163. BL = 0x0
  164. RBT = 0x0
  165. WR = 0x8
  166. ===================================
  167. ===================================
  168. ANA top config
  169. ===================================
  170. ASYNC_MODE = 3
  171. DLL_ASYNC_EN = 1
  172. ALL_SLAVE_EN = 0
  173. NEW_RANK_MODE = 0
  174. DLL_IDLE_MODE = 1
  175. LP45_APHY_COMB_EN = 1
  176. TX_ODT_DIS = 0
  177. NEW_8X_MODE = 0
  178. ===================================
  179. ===================================
  180. data_rate = 3200
  181. CKR = 1
  182. DQ_P2S_RATIO = 8
  183. ===================================
  184. CA_P2S_RATIO = 8
  185. DQ_CA_OPEN = 0
  186. DQ_SEMI_OPEN = 0
  187. CA_SEMI_OPEN = 0
  188. CA_FULL_RATE = 0
  189. DQ_CKDIV4_EN = 0
  190. CA_CKDIV4_EN = 0
  191. CA_PREDIV_EN = 0
  192. PH8_DLY = 31
  193. SEMI_OPEN_CA_PICK_MCK_RATIO= 0
  194. DQ_AAMCK_DIV = 4
  195. CA_AAMCK_DIV = 4
  196. CA_ADMCK_DIV = 4
  197. DQ_TRACK_CA_EN = 0
  198. CA_PICK = 1600
  199. CA_MCKIO = 1600
  200. MCKIO_SEMI = 0
  201. PLL_FREQ = 3200
  202. DQ_UI_PI_RATIO = 32
  203. CA_UI_PI_RATIO = 0
  204. ===================================
  205. ===================================
  206. memory_type:PCDDR4
  207. GP_NUM : 1
  208. SRAM_EN : 1
  209. MD32_EN : 0
  210. ===================================
  211. ===========================================
  212. HW_ZQCAL_config
  213. ===========================================
  214. ZQCALL is 0
  215. TZQLAT is 27
  216. ZQCSDUAL is 0
  217. ZQCSCNT is 511
  218. ===========================================
  219. [ANA_INIT] >>>>>>>>>>>>>>
  220. [ANA_ClockOff_Sequence] flow start
  221. WLY_DEBUG::ANA_ClockOff_Sequence delay 100ns start
  222. WLY_DEBUG::ANA_ClockOff_Sequence delay 100ns end
  223. [ANA_ClockOff_Sequence] flow end
  224. ============ PULL DRAM RESETB DOWN ============
  225. ========== PULL DRAM RESETB DOWN end =========
  226. ============ SUSPEND_ON ============
  227. ============ SUSPEND_ON end ============
  228. ============ SPM_control ============
  229. ============ SPM_control end ============
  230. <<<<<< [CONFIGURE PHASE]: ANA_TX
  231. >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
  232. ===================================
  233. data_rate = 3200,PCW = 0X7800
  234. ===================================
  235. <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
  236. INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  237. INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  238. INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  239. INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  240. INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0
  241. INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  242. INFO: RG_ARCMD_REV_TEMP_VALUE= 0x0
  243. INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  244. >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
  245. INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0
  246. INFO: RG_ARDQ_REV_B0_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  247. INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0
  248. INFO: RG_ARDQ_REV_B1_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  249. INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0
  250. INFO: RG_ARDQ_REV_B2_TEMP_VALUE= 0x0 PH8_DLY= 0x1f
  251. INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  252. INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60 PH8_DLY= 0x1f
  253. <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
  254. >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
  255. INFO: RG_ARCMD_REV_TEMP_VALUE= 0x60
  256. INFO: RG_ARCMD_REV_TEMP_VALUE= 0x61
  257. <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
  258. [ANA_INIT] flow start
  259. [ANA_INIT] PLL >>>>>>>>
  260. [ANA_INIT] PLL <<<<<<<<
  261. [ANA_INIT] MIDPI >>>>>>>>
  262. [ANA_INIT] MIDPI <<<<<<<<
  263. [ANA_INIT] DLL >>>>>>>>
  264. [ANA_INIT] DLL <<<<<<<<
  265. [ANA_INIT] flow end
  266. [ANA_INIT] <<<<<<<<<<<<<
  267. [Flow] [DDRPHY] DIG_CONFIG_NONSHUF_DCM <<<<<
  268. [Flow] [DDRPHY] DIG_CONFIG_NONSHUF_DCM <<<<<
  269. [Flow] Enable top DCM control >>>>>
  270. [Flow] Enable top DCM control <<<<<
  271. Enable DLL master slave shuffle
  272. ==============================================================
  273. Gating Mode config
  274. ==============================================================
  275. Config description:
  276. RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
  277. RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (Jade-like) 2: FIFO mode
  278. SELPH_MODE 0: By rank 1: By Phase
  279. ==============================================================
  280. GAT_TRACK_EN = 1
  281. RX_GATING_MODE = 2
  282. RX_GATING_TRACK_MODE = 2
  283. SELPH_MODE = 1
  284. PICG_EARLY_EN = 1
  285. VALID_LAT_VALUE = 0
  286. ==============================================================
  287. Enter into Gating configuration >>>>
  288. Exit from Gating configuration <<<<
  289. [DIG_HW_NONSHUF_ZQCAL_CFG],Configuration Enter
  290. [DIG_HW_NONSHUF_ZQCAL_CFG_FOR_PCDDR],Configuration Enter
  291. [DIG_HW_NONSHUF_ZQCAL_CFG],Configuration Enter
  292. [DIG_HW_NONSHUF_ZQCAL_CFG_FOR_PCDDR],Configuration Enter
  293. Enter into PICG configuration >>>>
  294. Exit from PICG configuration <<<<
  295. [DIG_SHUF_CONFIG] DCM_FUNCTION >>>>>>, group_id=0
  296. [DIG_SHUF_CONFIG] DCM_FUNCTION <<<<<<, group_id=0
  297. [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:0, group_id:0 >>>>>
  298. [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id:0, group_id:0 <<<<<
  299. [DIG_HW_SHUF_ZQCAL_CFG] Group:0, Configuration Enter
  300. [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  301. PCDDR4 DRAM CONFIGURATION
  302. ===================================
  303. CWL = 0x7
  304. RTT_NORM = 0x6
  305. CL = 0xb
  306. AL = 0x0
  307. BL = 0x0
  308. RBT = 0x0
  309. WR = 0x8
  310. ===================================
  311. [ReadLatency GET] MR_CL:[ReadLatency GET] MR_CL:UI_MCK_least is 1
  312. RX_GW_selph_by_ps[0] is 12464
  313. RX_GW_selph_by_ps[1] is 12464
  314. RX_GW_selph_by_ps[2] is 12464
  315. RX_GW_selph_by_ps[3] is 12464
  316. ===================================
  317. RX_path CONFIGURATION
  318. ===================================
  319. data_rate is 3200
  320. dq_p2s_ratio is 8
  321. ca_default_delay is 1
  322. ca_ser_latency is 7
  323. cs2RL_start is 1
  324. byte_num is 2
  325. rank_num is 2
  326. RL[0] is 24
  327. RL[1] is 24
  328. RL_min is 24
  329. RL_max is 24
  330. TDQSCK[0] is 0
  331. TDQSCK[1] is 0
  332. TDQSCK[2] is 0
  333. TDQSCK[3] is 0
  334. dqsien_default_delay is 0
  335. dqsien_ser_latency is 7
  336. oe_ser_latency is 4
  337. gating_window_ahead_dqs is 2
  338. aphy_slice_delay is 11
  339. aphy_dtc_delay is 100
  340. aphy_lead_lag_margin is 16
  341. dram_ui_ratio is 2
  342. dq_ui_unit is 312
  343. ca_ui_unit is 312
  344. MCK_unit is 2496
  345. dramc_dram_ratio is 4
  346. CKR is 1
  347. tRPRE_toggle is 0
  348. tRPRE_static is 2
  349. tRPST is 0
  350. DQSIENMODE is 1
  351. BL is 16
  352. FAKE_1TO16_MODE is 0
  353. SVA_1_10_t2_SPEC is 11
  354. read_cmd_out is 1
  355. ca_MCKIO_ui_unit is 312
  356. ca_p2s_ratio is 8
  357. TDQSCK_min_SPEC is 0
  358. TDQSCK_max_SPEC is 360
  359. TX_pipeline is 1
  360. RX_pipeline is 1
  361. NEW_RANK_MODE is 0
  362. close_loop_mode is 1
  363. ===================================
  364. ===================================
  365. RX_path RG value
  366. ===================================
  367. RX_UI_P0[0] is 15
  368. RX_UI_P0[1] is 15
  369. RX_UI_P0[2] is 15
  370. RX_UI_P0[3] is 15
  371. RX_UI_P1[0] is 19
  372. RX_UI_P1[1] is 19
  373. RX_UI_P1[2] is 19
  374. RX_UI_P1[3] is 19
  375. RX_PI[0] is 31
  376. RX_PI[1] is 31
  377. RX_PI[2] is 31
  378. RX_PI[3] is 31
  379. DQSINCTL is 3
  380. DATLAT_DSEL is 11
  381. DATLAT is 12
  382. DATLAT_DSEL_PHY is 12
  383. DLE_EXTEND is 1
  384. RX_IN_GATE_EN_HEAD is 0
  385. RX_IN_GATE_EN_TAIL is 0
  386. RX_IN_BUFF_EN_HEAD is 2
  387. RX_IN_BUFF_EN_TAIL is 0
  388. RX_IN_GATE_EN_PRE_OFFSET is 2
  389. RANKINCTL_ROOT1 is 1
  390. RANKINCTL is 1
  391. RANKINCTL_STB is 2
  392. RANKINCTL_RXDLY is 0
  393. SHU_GW_THRD_POS is 42
  394. SHU_GW_THRD_NEG is 0
  395. RDSEL_TRACK_EN is 0
  396. RDSEL_HWSAVE_MSK is 1
  397. DMDATLAT_i is 12
  398. RODTEN is 0
  399. RODT is -27331254
  400. RODTE is 1
  401. RODTE2 is 1
  402. ODTEN_MCK_P0[4] is 0
  403. ODTEN_MCK_P1[4] is 0
  404. ODTEN_UI_P0[4] is 0
  405. ODTEN_UI_P1[4] is 0
  406. RX_RANK_DQS_LAT is 0
  407. RX_RANK_DQ_LAT is 1
  408. RANKINCTL_PHY is 5
  409. RANK_SEL_LAT_CA is 0
  410. RANK_SEL_LAT_B0 is 0
  411. RANK_SEL_LAT_B1 is 0
  412. RANK_SEL_STB_EN is 0
  413. RANK_SEL_RXDLY_TRACK is 0
  414. RANK_SEL_STB_TRACK is 1
  415. RANK_SEL_STB_PHASE_EN is 1
  416. RANK_SEL_PHSINCTL is 2
  417. RANK_SEL_STB_UI_MINUS is 2
  418. RANK_SEL_STB_UI_PLUS is 0
  419. RANK_SEL_MCK_P0 is 0
  420. RANK_SEL_UI_P0 is 0
  421. RANK_SEL_MCK_P1 is 1
  422. RANK_SEL_UI_P1 is 0
  423. R0DQSIENLLMTEN is 1
  424. R0DQSIENLLMT is 96
  425. R0DQSIENHLMTEN is 1
  426. R0DQSIENHLMT is 63
  427. R1DQSIENLLMTEN is 1
  428. R1DQSIENLLMT is 96
  429. R1DQSIENHLMTEN is 1
  430. R1DQSIENHLMT is 63
  431. DQSIEN_FIFO_DEPTH_HALF is 1
  432. ===================================
  433. [ModeRegister CWL Config] data_rate:3200-MR_CWL:[ModeRegister CL Config] data_rate:3200-MR_CL:[ModeRegister WR Config] data_rate:3200-MR_WR:===================================
  434. PCDDR4 DRAM CONFIGURATION
  435. ===================================
  436. CWL = 0x7
  437. RTT_NORM = 0x6
  438. CL = 0xb
  439. AL = 0x0
  440. BL = 0x0
  441. RBT = 0x0
  442. WR = 0x8
  443. ===================================
  444. [WriteLatency GET] MR_CWL:[WriteLatency GET] MR_CWL:=====================================
  445. print TX_path_config
  446. =====================================
  447. data_ratio is 3200
  448. dq_p2s_ratio is 8
  449. cs2WL_start is 1
  450. byte_num is 2
  451. rank_num is 2
  452. CKR is 1
  453. DBI_WR is 0
  454. dly_1T_by_FDIV2 is 0
  455. WL[0] is 20
  456. WL[1] is 20
  457. TDQSS[0][0] is 156
  458. TDQSS[0][1] is 156
  459. TDQSS[1][0] is 156
  460. TDQSS[1][1] is 156
  461. TDQS2DQ[0][0] is 0
  462. TDQS2DQ[0][1] is 0
  463. TDQS2DQ[1][0] is 0
  464. TDQS2DQ[1][1] is 0
  465. ca_p2s_ratio is 8
  466. ca_default_dly is 1
  467. ca_default_pi is 0
  468. ca_ser_latency is 7
  469. dqs_ser_laterncy is 7
  470. dqs_default_dly is 5
  471. dqs_oe_default_dly is 2
  472. dq_ser_laterncy is 7
  473. MCK_unit is 2496
  474. dq_ui_unit is 312
  475. ca_unit is 312
  476. ca_MCKIO_unit is 312
  477. ca_frate is 0
  478. TX_ECC is 0
  479. TWPRE is 4
  480. OE_pre_margin is 400
  481. OE_pst_margin is 500
  482. OE_downgrade is 1
  483. aphy_slice_dly is 11
  484. aphy_dtc_dly is 100
  485. aphy_tx_dly is 16
  486. DDRPHY_CLK_EN_COMB_TX_OPT is 1
  487. NEW_RANK_MODE is 0
  488. close_loop_mode is 1
  489. TXP_WORKAROUND_OPT is 0
  490. ui2pi_ratio is 32
  491. XRTW2W_PI_mute_time is 7
  492. fake_mode is 0
  493. ===========================================
  494. TX_DQ_UI_OE_pre is 2
  495. TX_DQS_UI_OE_pre is 1
  496. data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  497. data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  498. data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  499. data_ratio 3200, TX_dq_latency_ps is 8112, TX_dq_latency_MCK is 3
  500. ===========================================
  501. print TX_path_attribution
  502. ===========================================
  503. TX_DQ_MCK_OE[0][0] is 2
  504. TX_DQ_MCK_OE[0][1] is 2
  505. TX_DQ_MCK_OE[1][0] is 2
  506. TX_DQ_MCK_OE[1][1] is 2
  507. TX_DQ_UI_OE[0][0] is 6
  508. TX_DQ_UI_OE[0][1] is 6
  509. TX_DQ_UI_OE[1][0] is 6
  510. TX_DQ_UI_OE[1][1] is 6
  511. TX_DQ_MCK[0][0] is 3
  512. TX_DQ_MCK[0][1] is 3
  513. TX_DQ_MCK[1][0] is 3
  514. TX_DQ_MCK[1][1] is 3
  515. TX_DQ_UI[0][0] is 2
  516. TX_DQ_UI[0][1] is 2
  517. TX_DQ_UI[1][0] is 2
  518. TX_DQ_UI[1][1] is 2
  519. TX_DQ_PI[0][0] is 0
  520. TX_DQ_PI[0][1] is 0
  521. TX_DQ_PI[1][0] is 0
  522. TX_DQ_PI[1][1] is 0
  523. TX_DQ_UIPI_all[0][0] is 0
  524. TX_DQ_UIPI_all[0][1] is 0
  525. TX_DQ_UIPI_all[1][0] is 0
  526. TX_DQ_UIPI_all[1][1] is 0
  527. TX_DQ_dlyline[0][0] is 0
  528. TX_DQ_dlyline[0][1] is 0
  529. TX_DQ_dlyline[1][0] is 0
  530. TX_DQ_dlyline[1][1] is 0
  531. TX_DQS_MCK_OE[0][0] is 2
  532. TX_DQS_MCK_OE[0][1] is 2
  533. TX_DQS_MCK_OE[1][0] is 2
  534. TX_DQS_MCK_OE[1][1] is 2
  535. TX_DQS_UI_OE[0][0] is 6
  536. TX_DQS_UI_OE[0][1] is 6
  537. TX_DQS_UI_OE[1][0] is 6
  538. TX_DQS_UI_OE[1][1] is 6
  539. TX_DQS_MCK[0][0] is 3
  540. TX_DQS_MCK[0][1] is 3
  541. TX_DQS_MCK[1][0] is 3
  542. TX_DQS_MCK[1][1] is 3
  543. TX_DQS_UI[0][0] is 1
  544. TX_DQS_UI[0][1] is 1
  545. TX_DQS_UI[1][0] is 1
  546. TX_DQS_UI[1][1] is 1
  547. DDRPHY_CLK_EN_COMB_TX_OPT is 1
  548. TX_DQS_PI[0][0] is 16
  549. TX_DQS_PI[0][1] is 16
  550. TX_DQS_PI[1][0] is 16
  551. TX_DQS_PI[1][1] is 16
  552. DDRPHY_CLK_EN_COMB_TX_PICG_CNT is 2
  553. DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P0 is 3
  554. DDRPHY_CLK_EN_COMB_TX_DQS_SEL_P1 is 4
  555. DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P0 is 3
  556. DDRPHY_CLK_EN_COMB_TX_DQ_RK0_SEL_P1 is 4
  557. DDRPHY_CLK_EN_COMB_TX_DQ_RK1_SEL_P0 is 3
  558. DDRPHY_CLK_EN_COMB_TX_DQ_RK1_SEL_P1 is 4
  559. DPHY_TX_DCM_EXTCNT is 0
  560. TX_PI_UPD_MODE is 1
  561. TX_PI_UPDCTL_B0 is 0
  562. TX_PI_UPDCTL_B1 is 0
  563. TX_RANKINCTL_ROOT is 0
  564. TX_RANKINCTL is 1
  565. TX_RANKINCTL_TXDLY is 2
  566. DDRPHY_CLK_DYN_GATING_SEL is 5
  567. DDRPHY_CLK_EN_OPT is 1
  568. ARPI_CMD is 0
  569. TDMY is 9
  570. TXOEN_AUTOSET_DQ_OFFSET is 3
  571. TXOEN_AUTOSET_DQS_OFFSET is 3
  572. TXOEN_AUTOSET_EN is 1
  573. TXPICG_AUTOSET_OPT is 0
  574. TXPICG_AUTOSET_EN is 1
  575. TXPICG_DQ_MCK_OFFSET_LAG is 0
  576. TXPICG_DQS_MCK_OFFSET_LAG is 0
  577. TXPICG_DQ_UI_OFFSET_LEAD is 0
  578. TXPICG_DQ_UI_OFFSET_LAG is 1
  579. TXPICG_DQS_UI_OFFSET_LEAD is 1
  580. TXPICG_DQS_UI_OFFSET_LAG is 0
  581. ===========================================
  582. set APHY_PI_CKCGH_CNT is 4 when not fake_mode, cur data_rate is 3200
  583. [DIG_SHUF_CONFIG] MISC >>>>>, group_id=0
  584. [DIG_SHUF_CONFIG] MISC <<<<<<, group_id=0
  585. [DIG_SHUF_CONFIG] DBI >>>>>>, group_id=0
  586. [DIG_SHUF_CONFIG] DBI <<<<<<, group_id=0
  587. dramc_dram_ratio: 4
  588. DDR4_DivMode: 1
  589. freq_index: 1600
  590. match AC timing 3
  591. [DDR4_ac_timing_setting]start
  592. [PC4 WR preamble settings]>>>>>>>> group_id = 0.
  593. [PC4 WR preamble settings]<<<<<<<< group_id = 0.
  594. clk_dramc_ref_sel FREQ=16
  595. fmem_ck_bfe_dcm_ch0 FREQ=253
  596. fmem_ck_aft_dcm_ch0 FREQ=253
  597. SetClkFreeRun enter => DRAM clock free run mode = ON.
  598. [DDR4] Pull Down reset.
  599. [DDR4] cke fix low 10ns at least.
  600. [DDR4] Delay 200 us.
  601. [DDR4] Pull Up reset.
  602. [DDR4] Delay 500 us.
  603. [DDR4] DRAM initilization RK:0 Enter >>>>>>>>
  604. [DDR4] Delay TXPR TRFC+10ns - 350ns(8Gb density)+10ns
  605. [DDR4_MRS] RK:0-MA:2-OP:0x[DDR4_MRS] RK:0-MA:3-OP:0x[DDR4_MRS] RK:0-MA:1-OP:0x[DDR4_MRS] RK:0-MA:4-OP:0x[DDR4_MRS] RK:0-MA:5-OP:0x[DDR4] DQ Vref calibration>>>>>>>
  606. [DDR4] DQ Vref Enable DQ vref calibration.
  607. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] wait tVREFDQE-150ns
  608. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] DQ Vref modify range and value
  609. [DDR4] DQ Vref Exit DQ vref calibration.
  610. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4] wait tVREFDQx-150ns
  611. [DDR4] DQ Vref calibration<<<<<<<
  612. [DDR4_MRS] RK:0-MA:0-OP:0x[DDR4_ZQ] RK:0 Enter >>>>>>>>
  613. [DDR4_ZQ] RK:0 Exit <<<<<<<<
  614. [DDR4] Delay ZQinit - 718ns for 1333 at least max(512Mck,640ns)
  615. [DDR4] DRAM initilization RK:0 Exit <<<<<<<
  616. [DDR4] Enable refresh.....All bank refresh only
  617. SetClkFreeRun enter => DRAM clock free run mode = OFF.
  618. [DIG_HW_NONSHUF_ZQCAL_SWITCH],Configuration Enter
  619. [DIG_HW_NONSHUF_DQSG_SWITCH],Configuration Enter
  620. SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
  621. [MiockJmeterHQA]
  622. ===============================================================================
  623. Dram Type= 4, Freq= 1600, CH_0, rank 0
  624. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  625. ===============================================================================
  626.  
  627. [DramcMiockJmeter] u1RxGatingPI = 0
  628. 0 : 2196, 2196
  629. 1 : 2192, 2192
  630. 2 : 2191, 2191
  631. 3 : 2187, 2187
  632. 4 : 2191, 2191
  633. 5 : 2191, 2191
  634. 6 : 2191, 2191
  635. 7 : 2191, 2191
  636. 8 : 2197, 2197
  637. 9 : 2197, 2197
  638. 10 : 2192, 2192
  639. 11 : 2191, 2191
  640. 12 : 2192, 2192
  641. 13 : 2191, 2191
  642. 14 : 2187, 2187
  643. 15 : 2192, 2192
  644. 16 : 2191, 2191
  645. 17 : 2191, 2191
  646. 18 : 2192, 2192
  647. 19 : 2191, 2191
  648. 20 : 2192, 2192
  649. 21 : 2192, 2192
  650. 22 : 2187, 2187
  651. 23 : 2191, 2191
  652. 24 : 2191, 2191
  653. 25 : 2197, 2197
  654. 26 : 2191, 2191
  655. 27 : 2191, 2191
  656. 28 : 2192, 2192
  657. 29 : 2191, 2191
  658. 30 : 2192, 2192
  659. 31 : 2191, 2191
  660. 32 : 2191, 2191
  661. 33 : 2192, 2192
  662. 34 : 2197, 2197
  663. 35 : 2191, 2191
  664. 36 : 2187, 2187
  665. 37 : 2196, 2196
  666. 38 : 2187, 2169
  667. 39 : 2196, 0
  668. 40 : 2191, 0
  669. 41 : 2192, 0
  670. 42 : 2187, 0
  671. 43 : 2191, 0
  672. 44 : 2192, 0
  673. 45 : 2191, 0
  674. 46 : 2191, 0
  675. 47 : 2187, 0
  676. 48 : 2192, 0
  677. 49 : 2196, 0
  678. 50 : 2192, 0
  679. 51 : 2187, 0
  680. 52 : 2191, 0
  681. 53 : 2192, 0
  682. 54 : 2191, 0
  683. 55 : 2192, 0
  684. 56 : 2191, 0
  685. 57 : 2192, 0
  686. 58 : 2187, 0
  687. 59 : 2191, 0
  688. 60 : 2191, 0
  689. 61 : 2192, 0
  690. 62 : 2191, 0
  691. 63 : 2197, 0
  692. 64 : 2192, 0
  693. 65 : 2191, 0
  694. 66 : 2192, 0
  695. 67 : 2191, 0
  696. 68 : 2191, 0
  697. 69 : 2192, 0
  698. 70 : 2191, 0
  699. 71 : 2196, 0
  700. 72 : 2192, 0
  701. 73 : 2191, 0
  702. 74 : 2191, 0
  703. 75 : 2192, 0
  704. 76 : 2191, 0
  705. 77 : 2192, 0
  706. 78 : 2191, 0
  707. 79 : 2192, 0
  708. 80 : 2187, 0
  709. 81 : 2197, 0
  710. 82 : 2191, 0
  711. 83 : 2191, 0
  712. 84 : 2192, 0
  713. 85 : 2191, 0
  714. 86 : 2196, 0
  715. 87 : 2187, 0
  716. 88 : 2196, 0
  717. 89 : 2192, 1411
  718. 90 : 2191, 2189
  719. 91 : 2192, 2192
  720. 92 : 2191, 2191
  721. 93 : 2197, 2197
  722. 94 : 2191, 2191
  723. 95 : 2192, 2192
  724. 96 : 2191, 2191
  725. 97 : 2192, 2192
  726. 98 : 2192, 2192
  727. 99 : 2191, 2191
  728. 100 : 2192, 2192
  729. 101 : 2192, 2192
  730. 102 : 2191, 2191
  731. 103 : 2187, 2187
  732. 104 : 2187, 2187
  733. 105 : 2191, 2191
  734. 106 : 2191, 2191
  735. 107 : 2192, 2192
  736. 108 : 2192, 2192
  737. 109 : 2192, 2192
  738. 110 : 2191, 2191
  739. 111 : 2187, 2187
  740. 112 : 2187, 2187
  741. 113 : 2187, 2187
  742. 114 : 2192, 2192
  743. 115 : 2187, 2187
  744. 116 : 2192, 2192
  745. 117 : 2192, 2192
  746. 118 : 2192, 2192
  747. 119 : 2192, 2192
  748. 120 : 2197, 2197
  749. 121 : 2196, 2196
  750. 122 : 2191, 2191
  751. 123 : 2192, 2192
  752. 124 : 2191, 2191
  753. 125 : 2196, 2196
  754. 126 : 2192, 2192
  755. 127 : 2192, 2192
  756.  
  757. MIOCK jitter meter ch=0
  758.  
  759. 1T = (89-39)*2 = 100 dly cells
  760. Clock freq = 1560 MHz, period = 641 ps, 1 dly cell = 641/100 ps
  761.  
  762. ----->DramcWriteLeveling(PI) begin...
  763. ===============================================================================
  764. Dram Type= 4, Freq= 1600, CH_0, rank 0
  765. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  766. ===============================================================================
  767. Begin: 0, End: 63, Step: 1, Bound: 64
  768. [DDR4_MRS] RK:0-MA:2-OP:0x[DDR4_MRS] RK:0-MA:1-OP:0x[Write Leveling]
  769. delay byte0 byte1 byte2 byte3
  770.  
  771. 0 O1( 1 1
  772. 1 O1( 1 1
  773. 2 O1( 1 1
  774. 3 O1( 1 1
  775. 4 O1( 1 1
  776. 5 O1( 1 1
  777. 6 O1( 1 1
  778. 7 O1( 1 1
  779. 8 O1( 1 1
  780. 9 O1( 1 1
  781. 10 O1( 1 0
  782. 11 O1( 1 0
  783. 12 O1( 1 0
  784. 13 O1( 1 0
  785. 14 O1( 1 0
  786. 15 O1( 1 0
  787. 16 O1( 0 0
  788. 17 O1( 0 0
  789. 18 O1( 0 0
  790. 19 O1( 0 0
  791. 20 O1( 0 0
  792. 21 O1( 0 0
  793. 22 O1( 0 0
  794. 23 O1( 0 0
  795. 24 O1( 0 0
  796. 25 O1( 0 0
  797. 26 O1( 0 0
  798. 27 O1( 0 0
  799. 28 O1( 0 0
  800. 29 O1( 0 0
  801. 30 O1( 0 0
  802. 31 O1( 0 0
  803. 32 O1( 0 0
  804. 33 O1( 0 0
  805. 34 O1( 0 0
  806. 35 O1( 0 0
  807. 36 O1( 0 0
  808. 37 O1( 0 0
  809. 38 O1( 0 0
  810. 39 O1( 0 0
  811. 40 O1( 0 1
  812. 41 O1( 0 1
  813. 42 O1( 0 1
  814. 43 O1( 0 1
  815. 44 O1( 0 1
  816. 45 O1( 1 1
  817. 46 O1( 1 1
  818. 47 O1( 1 1
  819. 48 O1( 1 1
  820. 49 O1( 1 1
  821. 50 O1( 1 1
  822. 51 O1( 1 1
  823. Early breakpass bytecount = 0xff (0xff: all bytes pass)
  824.  
  825. [DDR4_MRS] RK:0-MA:1-OP:0x[DDR4_MRS] RK:0-MA:2-OP:0xWrite leveling (Byte 0): 45 => 45
  826. Write leveling (Byte 1): 40 => 40
  827. DramcWriteLeveling(PI) end<-----
  828.  
  829. ===============================================================================
  830. Dram Type= 4, Freq= 1600, CH_0, rank 0
  831. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  832. ===============================================================================
  833. [Gating] SW mode calibration
  834. [get_gating_start_pos] calculated gating ui = 15
  835. 12 0 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  836. 12 4 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  837. 12 8 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  838. 12 12 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  839. 12 16 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  840. 12 20 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  841. 12 24 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  842. 12 28 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  843. 13 0 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  844. 13 4 | B1->B0 | 0 0 | 0 0 | (0 0) (0 0)
  845. 13 8 | B1->B0 | 1111 0 | 1 1 | (0 0) (0 0)
  846. 13 12 | B1->B0 | 1111 1111 | 1 1 | (0 0) (0 0)
  847. 13 16 | B1->B0 | 1111 1111 | 1 1 | (0 0) (0 0)
  848. 13 20 | B1->B0 | 1111 1111 | 1 1 | (0 0) (0 0)
  849. 13 24 | B1->B0 | 1111 1111 | 1 1 | (0 0) (0 0)
  850. 13 28 | B1->B0 | 1111 1111 | 1 1 | (0 0) (0 0)
  851. 14 0 | B1->B0 | 1111 1111 | 1 1 | (0 0) (0 0)
  852. 14 4 | B1->B0 | 1111 1111 | 1 1 | (0 0) (0 0)
  853. 14 8 | B1->B0 | 1111 1111 | 1 1 | (0 0) (0 0)
  854. 14 12 | B1->B0 | 1111 1111 | 1 1 | (0 1) (0 1)
  855. 14 16 | B1->B0 | 1111 1111 | 1 1 | (1 1) (0 1)
  856. 14 20 | B1->B0 | 1111 1111 | 1 1 | (1 1) (1 1)
  857. 14 24 | B1->B0 | 1111 1111 | 1 1 | (1 1) (1 1)
  858. 14 28 | B1->B0 | 1111 1111 | 1 1 | (1 1) (1 1)
  859. 15 0 | B1->B0 | 1111 1111 | 1 1 | (1 1) (1 1)
  860. 15 4 | B1->B0 | 1111 1111 | 1 1 | (1 1) (1 1)
  861. 15 8 | B1->B0 | 2121 1111 | 1 1 | (0 0) (1 1)
  862. 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  863. 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  864. 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  865. 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  866. 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  867. 16 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  868. 16 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  869. 16 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  870. 16 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
  871. 16 16 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
  872. 16 20 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  873. 16 24 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  874. 16 28 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  875. 17 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  876. 17 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  877. 17 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  878. 17 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  879. 17 16 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  880. 17 20 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  881. 17 24 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  882. 17 28 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  883. 18 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  884. 18 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  885. 18 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
  886. 18 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
  887. 18 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
  888. 18 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  889. 18 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  890. 18 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  891. 19 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  892. 19 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  893. 19 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  894. 19 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  895. 19 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  896. best dqsien dly found for B1: (18, 12)
  897. 19 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
  898. best dqsien dly found for B0: (18, 14)
  899. best DQS0 dly(UI, PI) = (18, 14)
  900. best DQS1 dly(UI, PI) = (18, 12)
  901.  
  902. [Gating] SW calibration Done
  903. [DDR4_MRS] RK:0-MA:3-OP:0x===============================================================================
  904. Dram Type= 4, Freq= 1600, CH_0, rank 0
  905. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  906. ===============================================================================
  907. Start DQ dly to find pass range UseTestEngine =0
  908. UseTestEngine: 0
  909. RX Vref Scan: 0
  910.  
  911. RX Vref 0 -> 0, step: 1
  912.  
  913. RX Delay -48 -> 63, step: 4
  914. -48, [0] xxxxxxxx xxxxxxxx [MSB]
  915. -44, [0] xxxxxxxx xxxxxxxx [MSB]
  916. -40, [0] xxxxxxxx xxxxxxxx [MSB]
  917. -36, [0] xxxxxxxx xxxxxxxx [MSB]
  918. -32, [0] xxxxxxxx xxxxxxxx [MSB]
  919. -28, [0] xxxxxxxx xxxxxxxx [MSB]
  920. -24, [0] xxxxxxxx xxxxxxxx [MSB]
  921. -20, [0] xxxxxxxx xxxxxxxx [MSB]
  922. -16, [0] xxxxxxxx xxxxxxxx [MSB]
  923. -12, [0] xxxxxxxx xxxxxxxx [MSB]
  924. -8, [0] xxxxxxxx xxxxxxxx [MSB]
  925. -4, [0] xxxxxxox xxxxxxxx [MSB]
  926. 0, [0] xxoxoxox xxoxoxxx [MSB]
  927. 4, [0] oooooooo oooooooo [MSB]
  928. 8, [0] oooooooo oooooooo [MSB]
  929. 12, [0] oooooooo oooooooo [MSB]
  930. 16, [0] oooooooo oooooooo [MSB]
  931. 20, [0] oooooooo oooooooo [MSB]
  932. 24, [0] oooooooo oooooooo [MSB]
  933. 28, [0] oooooooo oooooooo [MSB]
  934. 32, [0] oooooooo oooooooo [MSB]
  935. 36, [0] ooooooxo oooooooo [MSB]
  936. 40, [0] ooxoxoxo oooooooo [MSB]
  937. 44, [0] xoxxxxxx xoxxxxxx [MSB]
  938. 48, [0] xxxxxxxx xxxxxxxx [MSB]
  939. RX Vref B0= 0, Window Sum 324, worse bit 0, min window 40
  940. iDelay=48, Bit 0, Center 23 (4 ~ 43) 40
  941. iDelay=48, Bit 1, Center 25 (4 ~ 47) 44
  942. iDelay=48, Bit 2, Center 19 (0 ~ 39) 40
  943. iDelay=48, Bit 3, Center 23 (4 ~ 43) 40
  944. iDelay=48, Bit 4, Center 19 (0 ~ 39) 40
  945. iDelay=48, Bit 5, Center 23 (4 ~ 43) 40
  946. iDelay=48, Bit 6, Center 15 (-4 ~ 35) 40
  947. iDelay=48, Bit 7, Center 23 (4 ~ 43) 40
  948. RX Vref B1= 0, Window Sum 332, worse bit 8, min window 40
  949. iDelay=48, Bit 8, Center 23 (4 ~ 43) 40
  950. iDelay=48, Bit 9, Center 25 (4 ~ 47) 44
  951. iDelay=48, Bit 10, Center 21 (0 ~ 43) 44
  952. iDelay=48, Bit 11, Center 23 (4 ~ 43) 40
  953. iDelay=48, Bit 12, Center 21 (0 ~ 43) 44
  954. iDelay=48, Bit 13, Center 23 (4 ~ 43) 40
  955. iDelay=48, Bit 14, Center 23 (4 ~ 43) 40
  956. iDelay=48, Bit 15, Center 23 (4 ~ 43) 40
  957. [DDR4_MRS] RK:0-MA:3-OP:0x===============================================================================
  958. Dram Type= 4, Freq= 1600, CH_0, rank 0
  959. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  960. ===============================================================================
  961. DQS Delay:
  962. DQS0 = 0, DQS1 = 0
  963. DQM Delay:
  964. DQM0 = 21, DQM1 = 22
  965. DQ Delay:
  966. DQ0 =23, DQ1 =25, DQ2 =19, DQ3 =23
  967. DQ4 =19, DQ5 =23, DQ6 =15, DQ7 =23
  968. DQ8 =23, DQ9 =25, DQ10 =21, DQ11 =23
  969. DQ12 =21, DQ13 =23, DQ14 =23, DQ15 =23
  970.  
  971.  
  972. ===============================================================================
  973. Dram Type= 4, Freq= 1600, CH_0, rank 0
  974. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  975. ===============================================================================
  976. [TxWindowPerbitCal] caltype:2 Autok:0
  977.  
  978.  
  979. TX Vref Scan disable
  980. 808 |3 0 40|[0] xxxxxxxx xxxxxxxx [MSB]
  981. 810 |3 0 42|[0] xxxxxxox xxxxoxxx [MSB]
  982. 812 |3 0 44|[0] xxoxxxox xxoxoxxx [MSB]
  983. 814 |3 0 46|[0] oxoxoxox oxoooooo [MSB]
  984. 816 |3 0 48|[0] oxoxoxox oooooooo [MSB]
  985. 836 |3 2 4|[0] oooooooo ooxooxoo [MSB]
  986. 838 |3 2 6|[0] ooooooxo xxxxxxxx [MSB]
  987. 840 |3 2 8|[0] ooxoooxo xxxxxxxx [MSB]
  988. 842 |3 2 10|[0] xoxoxoxo xxxxxxxx [MSB]
  989. 844 |3 2 12|[0] xoxoxxxo xxxxxxxx [MSB]
  990. 846 |3 2 14|[0] xxxxxxxx xxxxxxxx [MSB]
  991. TX Bit0 (814~840) 28 827, Bit8 (814~836) 24 825,
  992. TX Bit1 (818~844) 28 831, Bit9 (816~836) 22 826,
  993. TX Bit2 (812~838) 28 825, Bit10 (812~834) 24 823,
  994. TX Bit3 (818~844) 28 831, Bit11 (814~836) 24 825,
  995. TX Bit4 (814~840) 28 827, Bit12 (810~836) 28 823,
  996. TX Bit5 (818~842) 26 830, Bit13 (814~834) 22 824,
  997. TX Bit6 (810~836) 28 823, Bit14 (814~836) 24 825,
  998. TX Bit7 (818~844) 28 831, Bit15 (814~836) 24 825,
  999.  
  1000. == TX Byte 0 ==
  1001. Update DQ dly =827 (3 ,0, 59) DQ OEN =(2 ,5)
  1002. Update DQM dly =827 (3 ,0, 59) DQM OEN =(2 ,5)
  1003.  
  1004. == TX Byte 1 ==
  1005. Update DQ dly =824 (3 ,0, 56) DQ OEN =(2 ,5)
  1006. Update DQM dly =824 (3 ,0, 56) DQM OEN =(2 ,5)
  1007.  
  1008. ===============================================================================
  1009. Dram Type= 4, Freq= 1600, CH_0, rank 0
  1010. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1011. ===============================================================================
  1012. [TxWindowPerbitCal] caltype:0 Autok:0
  1013. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 0
  1014. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 2
  1015. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 4
  1016. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 6
  1017. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 8
  1018. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 10
  1019. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 12
  1020. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 14
  1021. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 16
  1022. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 18
  1023. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 20
  1024. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 22
  1025. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 24
  1026. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 26
  1027. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 28
  1028. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 30
  1029. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 32
  1030. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 34
  1031. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 36
  1032. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 38
  1033. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 40
  1034. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 42
  1035. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 44
  1036. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 46
  1037. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 48
  1038.  
  1039. TX Vref early break, caculate TX vref
  1040. TX Vref=0, minBit 10, minWin=13, winSum=256
  1041. TX Vref=2, minBit 10, minWin=12, winSum=264
  1042. TX Vref=4, minBit 10, minWin=13, winSum=274
  1043. TX Vref=6, minBit 10, minWin=14, winSum=282
  1044. TX Vref=8, minBit 10, minWin=14, winSum=292
  1045. TX Vref=10, minBit 2, minWin=16, winSum=304
  1046. TX Vref=12, minBit 2, minWin=16, winSum=306
  1047. TX Vref=14, minBit 2, minWin=16, winSum=311
  1048. TX Vref=16, minBit 10, minWin=17, winSum=321
  1049. TX Vref=18, minBit 10, minWin=17, winSum=329
  1050. TX Vref=20, minBit 2, minWin=19, winSum=341
  1051. TX Vref=22, minBit 10, minWin=19, winSum=349
  1052. TX Vref=24, minBit 10, minWin=19, winSum=357
  1053. TX Vref=26, minBit 2, minWin=21, winSum=366
  1054. TX Vref=28, minBit 10, minWin=21, winSum=375
  1055. TX Vref=30, minBit 10, minWin=22, winSum=380
  1056. TX Vref=32, minBit 4, minWin=23, winSum=389
  1057. TX Vref=34, minBit 10, minWin=21, winSum=391
  1058. TX Vref=36, minBit 4, minWin=23, winSum=395
  1059. TX Vref=38, minBit 10, minWin=22, winSum=394
  1060. TX Vref=40, minBit 10, minWin=22, winSum=392
  1061. TX Vref=42, minBit 12, minWin=20, winSum=385
  1062. TX Vref=44, minBit 10, minWin=21, winSum=378
  1063. TX Vref=46, minBit 12, minWin=20, winSum=378
  1064. TX Vref=48, minBit 10, minWin=19, winSum=362
  1065. [TxChooseVref] Worse bit 4, Min win 23, Win sum 395, Final Vref 36
  1066. [DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DDR4_MRS] RK:0-MA:6-OP:0x[DramcTXSetVref] TX Vref : CH0 Rank0, TX Range 1 Vref 36
  1067.  
  1068. Final TX Range 1 Vref 36
  1069.  
  1070. ===============================================================================
  1071. Dram Type= 4, Freq= 1600, CH_0, rank 0
  1072. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1073. ===============================================================================
  1074. [TxWindowPerbitCal] caltype:0 Autok:0
  1075.  
  1076.  
  1077. TX Vref Scan disable
  1078. 808 |3 0 40|[0] xxxxxxxx xxxxxxxx [MSB]
  1079. 809 |3 0 41|[0] xxxxxxxx xxxxxxxx [MSB]
  1080. 810 |3 0 42|[0] xxxxxxxx xxxxxxxx [MSB]
  1081. 811 |3 0 43|[0] xxxxxxxx xxxxxxxx [MSB]
  1082. 812 |3 0 44|[0] xxxxxxox xxxxxxxx [MSB]
  1083. 813 |3 0 45|[0] xxxxxxox xxoxoxxx [MSB]
  1084. 814 |3 0 46|[0] xxxxxxox oxoooooo [MSB]
  1085. 815 |3 0 47|[0] xxoxxxox oooooooo [MSB]
  1086. 816 |3 0 48|[0] oxoxxxox oooooooo [MSB]
  1087. 817 |3 0 49|[0] oooxooox oooooooo [MSB]
  1088. 835 |3 2 3|[0] oooooooo ooxooooo [MSB]
  1089. 836 |3 2 4|[0] oooooooo ooxoxooo [MSB]
  1090. 837 |3 2 5|[0] ooooooxo ooxoxooo [MSB]
  1091. 838 |3 2 6|[0] ooooooxo ooxxxooo [MSB]
  1092. 839 |3 2 7|[0] ooxoooxo xoxxxoxo [MSB]
  1093. 840 |3 2 8|[0] ooxoxoxo xxxxxxxx [MSB]
  1094. 841 |3 2 9|[0] xoxoxoxo xxxxxxxx [MSB]
  1095. 842 |3 2 10|[0] xxxoxxxx xxxxxxxx [MSB]
  1096. 843 |3 2 11|[0] xxxxxxxx xxxxxxxx [MSB]
  1097. TX Bit0 (816~840) 25 828, Bit8 (814~838) 25 826,
  1098. TX Bit1 (817~841) 25 829, Bit9 (815~839) 25 827,
  1099. TX Bit2 (815~838) 24 826, Bit10 (813~834) 22 823,
  1100. TX Bit3 (818~842) 25 830, Bit11 (814~837) 24 825,
  1101. TX Bit4 (817~839) 23 828, Bit12 (813~835) 23 824,
  1102. TX Bit5 (817~841) 25 829, Bit13 (814~839) 26 826,
  1103. TX Bit6 (812~836) 25 824, Bit14 (814~838) 25 826,
  1104. TX Bit7 (818~841) 24 829, Bit15 (814~839) 26 826,
  1105.  
  1106. [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =641/100 ps
  1107. == TX Byte 0 ==
  1108. u2DelayCellOfst[0]=6 cells (4 PI)
  1109. u2DelayCellOfst[1]=7 cells (5 PI)
  1110. u2DelayCellOfst[2]=3 cells (2 PI)
  1111. u2DelayCellOfst[3]=9 cells (6 PI)
  1112. u2DelayCellOfst[4]=6 cells (4 PI)
  1113. u2DelayCellOfst[5]=7 cells (5 PI)
  1114. u2DelayCellOfst[6]=0 cells (0 PI)
  1115. u2DelayCellOfst[7]=7 cells (5 PI)
  1116. Update DQ dly =824 (3 ,0, 56) DQ OEN =(2 ,5)
  1117. Update DQM dly =827 (3 ,0, 59) DQM OEN =(2 ,5)
  1118.  
  1119. == TX Byte 1 ==
  1120. u2DelayCellOfst[8]=4 cells (3 PI)
  1121. u2DelayCellOfst[9]=6 cells (4 PI)
  1122. u2DelayCellOfst[10]=0 cells (0 PI)
  1123. u2DelayCellOfst[11]=3 cells (2 PI)
  1124. u2DelayCellOfst[12]=1 cells (1 PI)
  1125. u2DelayCellOfst[13]=4 cells (3 PI)
  1126. u2DelayCellOfst[14]=4 cells (3 PI)
  1127. u2DelayCellOfst[15]=4 cells (3 PI)
  1128. Update DQ dly =823 (3 ,0, 55) DQ OEN =(2 ,5)
  1129. Update DQM dly =825 (3 ,0, 57) DQM OEN =(2 ,5)
  1130.  
  1131. ===============================================================================
  1132. Dram Type= 4, Freq= 1600, CH_0, rank 0
  1133. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1134. ===============================================================================
  1135. DATLAT Default: 0xc
  1136. 0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0x10, 0x11, 0x12, 0x13, 0xbest_step = 11
  1137.  
  1138. ===============================================================================
  1139. Dram Type= 4, Freq= 1600, CH_0, rank 0
  1140. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1141. ===============================================================================
  1142. Start DQ dly to find pass range UseTestEngine =1
  1143. UseTestEngine: 1
  1144. RX Vref Scan: 1
  1145.  
  1146. Set Vref Range= 9 -> 21
  1147.  
  1148. RX Vref 9 -> 21, step: 1
  1149.  
  1150. RX Delay -14 -> 63, step: 2
  1151.  
  1152. Set Vref, RX VrefLevel [Byte0]: 9 [Byte1]: 9
  1153. RX Vref B0= 9, Window Sum 234, worse bit 0, min window 28
  1154. RX Vref B1= 9, Window Sum 206, worse bit 8, min window 24
  1155.  
  1156. Set Vref, RX VrefLevel [Byte0]: 10 [Byte1]: 10
  1157. RX Vref B0= 10, Window Sum 240, worse bit 2, min window 28
  1158. RX Vref B1= 10, Window Sum 220, worse bit 8, min window 26
  1159.  
  1160. Set Vref, RX VrefLevel [Byte0]: 11 [Byte1]: 11
  1161. RX Vref B0= 11, Window Sum 250, worse bit 0, min window 30
  1162. RX Vref B1= 11, Window Sum 228, worse bit 8, min window 26
  1163.  
  1164. Set Vref, RX VrefLevel [Byte0]: 12 [Byte1]: 12
  1165. RX Vref B0= 12, Window Sum 262, worse bit 2, min window 30
  1166. RX Vref B1= 12, Window Sum 240, worse bit 10, min window 28
  1167.  
  1168. Set Vref, RX VrefLevel [Byte0]: 13 [Byte1]: 13
  1169. RX Vref B0= 13, Window Sum 268, worse bit 0, min window 32
  1170. RX Vref B1= 13, Window Sum 250, worse bit 10, min window 28
  1171.  
  1172. Set Vref, RX VrefLevel [Byte0]: 14 [Byte1]: 14
  1173. RX Vref B0= 14, Window Sum 278, worse bit 0, min window 34
  1174. RX Vref B1= 14, Window Sum 258, worse bit 10, min window 30
  1175.  
  1176. Set Vref, RX VrefLevel [Byte0]: 15 [Byte1]: 15
  1177. RX Vref B0= 15, Window Sum 284, worse bit 2, min window 34
  1178. RX Vref B1= 15, Window Sum 266, worse bit 10, min window 30
  1179.  
  1180. Set Vref, RX VrefLevel [Byte0]: 16 [Byte1]: 16
  1181. RX Vref B0= 16, Window Sum 290, worse bit 2, min window 34
  1182. RX Vref B1= 16, Window Sum 272, worse bit 8, min window 32
  1183.  
  1184. Set Vref, RX VrefLevel [Byte0]: 17 [Byte1]: 17
  1185. RX Vref B0= 17, Window Sum 296, worse bit 2, min window 34
  1186. RX Vref B1= 17, Window Sum 280, worse bit 10, min window 32
  1187.  
  1188. Set Vref, RX VrefLevel [Byte0]: 18 [Byte1]: 18
  1189. RX Vref B0= 18, Window Sum 300, worse bit 2, min window 36
  1190. RX Vref B1= 18, Window Sum 292, worse bit 8, min window 34
  1191.  
  1192. Set Vref, RX VrefLevel [Byte0]: 19 [Byte1]: 19
  1193.  
  1194. Set Vref, RX VrefLevel [Byte0]: 20 [Byte1]: 20
  1195.  
  1196. Set Vref, RX VrefLevel [Byte0]: 21 [Byte1]: 21
  1197.  
  1198. Final RX Vref Byte 0 = 18 to rank0 to rank1
  1199.  
  1200. Final RX Vref Byte 1 = 18 to rank0 to rank1
  1201. ===============================================================================
  1202. Dram Type= 4, Freq= 1600, CH_0, rank 0
  1203. fsp= 0, odt_onoff= 1, Byte mode= 0, DivMode= 1
  1204. ===============================================================================
  1205. DQS Delay:
  1206. DQS0 = 0, DQS1 = 0
  1207. DQM Delay:
  1208. DQM0 = 21, DQM1 = 22
  1209. DQ Delay:
  1210. DQ0 =22, DQ1 =26, DQ2 =17, DQ3 =24
  1211. DQ4 =19, DQ5 =23, DQ6 =14, DQ7 =23
  1212. DQ8 =22, DQ9 =24, DQ10 =21, DQ11 =24
  1213. DQ12 =21, DQ13 =24, DQ14 =21, DQ15 =23
  1214.  
  1215.  
  1216. [DualRankRxdatlatCal] RK0: 11, RK1: 0, Final_Datlat 11
  1217.  
  1218.  
  1219. [Calibration Summary] Freqency 1600
  1220. CH 0, Rank 0
  1221. SW Impedance : PASS
  1222. DUTY Scan : NO K
  1223. ZQ Calibration : PASS
  1224. Jitter Meter : NO K
  1225. CBT Training : NO K
  1226. Write leveling : PASS
  1227. RX DQS gating : PASS
  1228. RX DQ/DQS(RDDQC) : PASS
  1229. TX DQ/DQS : PASS
  1230. RX DATLAT : PASS
  1231. RX DQ/DQS(Engine): PASS
  1232. TX OE : NO K
  1233. All Pass.
  1234.  
  1235. TX_TRACKING: OFF
  1236. [AUTO] write start address pass, BASE_ADDR : 0x0, OFFSET : 0x3
  1237. [AUTO] Detect DramSize: 0x8000000
  1238. [AUTO] BASE_ADDR : 0x8000000, OFFSET : 0x3
  1239. [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  1240.  
  1241.  
  1242. [AUTO] Detect DramSize: 0x10000000
  1243. [AUTO] BASE_ADDR : 0x10000000, OFFSET : 0x3
  1244. [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  1245.  
  1246.  
  1247. [AUTO] Detect DramSize: 0x20000000
  1248. [AUTO] BASE_ADDR : 0x20000000, OFFSET : 0x3
  1249. [AUTO] BASE_ADDR : 0x0, OFFSET : 0x3
  1250. [AUTO] TA2 read check fail, u4err_value = 65535, 3
  1251. [AUTO] Detect full size
  1252.  
  1253.  
  1254. u4DramSize 0x20000000
  1255. NOTICE: EMI: Detected DRAM size: 512MB
  1256.  
  1257. [MEM_TEST] 02: After DFS, before run time config
  1258. [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count = 16384, Fail count = 0)
  1259.  
  1260. [TA2_TEST]
  1261. === TA2 HW
  1262. === OFFSET:0x200
  1263. TA2 PAT: 3
  1264.  
  1265. TA2 Trigger Write
  1266. HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
  1267. [DramcRunTimeConfig]: ON
  1268. !!! DPM_CONTROL_AFTERK: OFF
  1269. !!! DPM could not control APHY
  1270. PER_BANK_REFRESH: OFF
  1271. REFRESH_OVERHEAD_REDUCTION: ON
  1272. CMD_PICG_NEW_MODE: OFF
  1273. TX_TRACKING: OFF
  1274. RDSEL_TRACKING: OFF
  1275. DQS Precalculation for DVFS: OFF
  1276. RX_TRACKING: OFF
  1277. DDR_HW_GATING DBG: ON
  1278. DDR_ZQCS_ENABLE: ON
  1279. RX_PICG_NEW_MODE: ON
  1280. TX_PICG_NEW_MODE: ON
  1281. ENABLE_RX_DCM_DPHY: ON
  1282. LOWPOWER_GOLDEN_SETTINGS(DCM): ON
  1283. DUMMY_READ_FOR_TRACKING: OFF
  1284. !!! SPM_CONTROL_AFTERK: OFF
  1285. !!! SPM could not control APHY
  1286. IMPEDANCE_TRACKING: OFF
  1287. HW_SAVE_FOR_SR: OFF
  1288. CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
  1289. PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
  1290. Read ODT Tracking: OFF
  1291. Refresh Rate DeBounce: OFF
  1292. DFS_NO_QUEUE_FLUSH: OFF
  1293. DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
  1294. ENABLE_DFS_RUNTIME_MRW: OFF
  1295. DDR_RESERVE_NEW_MODE: ON
  1296. =========================
  1297.  
  1298. [MEM_TEST] 03: After run time config
  1299. [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count = 16384, Fail count = 0)
  1300.  
  1301. [TA2_TEST]
  1302. === TA2 HW
  1303. === OFFSET:0x200
  1304.  
  1305. TA2 Trigger Write
  1306. HW channel(0) Rank(0), TA2 pass, pass_cnt:2, err_cnt:0
  1307.  
  1308. Init_DRAM:2513: init PCDDR4 dram End
  1309. EMI: complex real chip dram calibration
  1310.  
  1311. drm_dram_reserved: MTK_DRM_MODE(22000000)
  1312.  
  1313. Verify pattern 1 (0x00~0xff)...
  1314. EMI: mem8_base[0] = pattern8 = 0x0
  1315. Verify pattern 2 (0x00~0xffff)...
  1316. EMI: mem16_base[0] = pattern16 = 0x0
  1317. Verify pattern 3 (0x00~0xffffffff)...
  1318. EMI: mem32_base[0] = pattern32 = 0x0
  1319. NOTICE: EMI: complex R/W mem test passed
  1320. INFO: PP COPY 0 CRC read: 0x1ccd, compute: 0x1ccd
  1321. NOTICE: SPI_NAND parses attributes from parameter page.
  1322. NOTICE: SPI_NAND Detected ID 0xc8
  1323. NOTICE: Page size 2048, Block size 131072, size 134217728
  1324. NOTICE: Initializing NMBM ...
  1325. NOTICE: Signature found at block 1023 [0x07fe0000]
  1326. NOTICE: First info table with writecount 0 found in block 960
  1327. NOTICE: Second info table with writecount 0 found in block 963
  1328. NOTICE: NMBM has been successfully attached in read-only mode
  1329. INFO: BL2: Loading image id 3
  1330. INFO: Loading image id=3 at address 0x42000000
  1331. INFO: Image id=3 loaded: 0x42000000 - 0x42009061
  1332. INFO: BL2: Loading image id 5
  1333. INFO: Loading image id=5 at address 0x42000000
  1334. INFO: Image id=5 loaded: 0x42000000 - 0x420ae288
  1335. NOTICE: BL2: Booting BL31
  1336. INFO: Entry point address = 0x43001000
  1337. INFO: SPSR = 0x3cd
  1338. INFO: Total CPU count: 4
  1339. INFO: MCUSYS: Disable 512KB L2C shared SRAM
  1340. INFO: check_ver = 0
  1341. INFO: Secondary bootloader is AArch64
  1342. INFO: GICv3 without legacy support detected.
  1343. INFO: ARM GICv3 driver initialized in EL3
  1344. INFO: Maximum SPI INTID supported: 671
  1345. INFO: SPMC: Changed to SPMC mode
  1346. NOTICE: BL31: v2.6(release):8b2bdeec64-dirty
  1347. NOTICE: BL31: Built : 09:23:25, Jan 30 2023
  1348. INFO: [MPU](Region0)sa:0x0300, ea:0x0302
  1349. INFO: [MPU](Region0)apc0:0x80b6db69, apc1:0x00b6db6d
  1350. INFO: [MPU](Region1)sa:0x0000, ea:0x0000
  1351. INFO: [MPU](Region1)apc0:0x00000000, apc1:0x00000000
  1352. INFO: [MPU](Region2)sa:0x0000, ea:0x0000
  1353. INFO: [MPU](Region2)apc0:0x00000000, apc1:0x00000000
  1354. INFO: [MPU](Region3)sa:0x0000, ea:0x0000
  1355. INFO: [MPU](Region3)apc0:0x00000000, apc1:0x00000000
  1356. INFO: [DEVAPC] devapc_init done
  1357. INFO: BL31: Initializing runtime services
  1358. INFO: BL31: Preparing for EL3 exit to normal world
  1359. INFO: Entry point address = 0x41e00000
  1360. INFO: SPSR = 0x3c9
  1361. In: serial@11002000
  1362. Out: serial@11002000
  1363. Err: serial@11002000
  1364. Net: eth0: ethernet@15100000
  1365.  
  1366. *** U-Boot Boot Menu ***
  1367.  
  1368. 1. Startup system (Default)
  1369. 2. Startup firmware0
  1370. 3. Startup firmware1
  1371. 4. Upgrade firmware
  1372. 5. Upgrade ATF BL2
  1373. 6. Upgrade ATF FIP
  1374. 7. Upgrade single image
  1375. 8. Load image
  1376. 0. U-Boot console
  1377.  
  1378.  
  1379. Press UP/DOWN to move, ENTER to select, ESC/CTRL+C to quit
  1380.  
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