sweet16 additions

6502 opcodes:
     S16 - switch to SWEET16 mode

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Register OPS-
     1n        SET       Rn     Constant  (Set)
     2n        LD        Rn     (Load)
     3n        ST        Rn     (Store)
     4n        LD        @Rn    (Load Indirect)
     5n        ST        @Rn    (Store Indirect)
     6n        LDD       @Rn    (Load Double Indirect)
     7n        STD       @Rn    (Store Double Indirect)
     8n        POP       @Rn    (Pop Indirect)
     9n        STP       @Rn    (Store POP Indirect)
     An        ADD       Rn     (Add)
     Bn        SUB       Rn     (Sub)
     Cn        POPD      @Rn    (Pop Double Indirect)
     Dn        CPR       Rn     (Compare)
     En        INR       Rn     (Increment)
     Fn        DCR       Rn     (Decrement)
Non-register OPS-
     00        RTN              (Return to 6502 mode)
     01        BR        ea     (Branch always)
     02        BNC       ea     (Branch if No Carry)
     03        BC        ea     (Branch if Carry)
     04        BP        ea     (Branch if Plus)
     05        BM        ea     (Branch if Minus)
     06        BZ        ea     (Branch if Zero)
     07        BNZ       ea     (Branch if NonZero)
     08        BM1       ea     (Branch if Minus 1)
     09        BNM1      ea     (Branch if Not Minus 1)
     0A        BK               (Break)
     0B        RS               (Return from Subroutine)
     0C        BS        ea     (Branch to Subroutine)
     0D                         (Escape code 1)
     0E                         (Unassigned)
     0F                         (Unassigned)

Extended ops:
     0D 0n     OR        Rn     (Bitwise OR)
     0D 1n     AND       Rn     (Bitwise AND)
     0D 2n     XOR       Rn     (Bitwise XOR)
     0D 3n     NEG       Rn     (Rn = -Rn)
     0D 4n     CPL       Rn     (Rn = ~Rn)
     0D 5n     EX        Rn     (Exchange with register)
     0D 6n     SHL       Rn     (Rn <<= 1)
     0D 7n     SHR       Rn     (Rn >>= 1)
     0D 8n     MUL       Rn     (R0 *= Rn, unsigned)
     0D 9n     MULS      Rn     (R0 *= Rn, signed)
     0D An     SHL0      n      (R0 <<= n)
     0D Bn     SHR0      n      (R0 >>= n)
     0D Cn     IND       Rn     (Rn = *Rn)
     0D Dn
     0D En
     0D Fn