Advertisement
cofyye

JK FLIP-FLOP SYNC

Apr 30th, 2023
511
0
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
VHDL 1.63 KB | Source Code | 0 0
  1. -- design.vhd
  2.  
  3. library IEEE;
  4. use IEEE.std_logic_1164.all;
  5.  
  6. entity jk_flipflop_sync is
  7.     port(J, K, clock : in std_logic;
  8.          Q, Qn : out std_logic);
  9. end entity jk_flipflop_sync;
  10.  
  11. architecture jk_flipflop_sync_arch of jk_flipflop_sync is
  12. begin
  13.     process(clock)
  14.     begin
  15.         if(clock'event and clock = '1') then
  16.           if(J = '0' and K = '0') then
  17.               Q <= Q;
  18.               Qn <= Qn;
  19.           elsif(J = '0' and K = '1') then
  20.               Q <= '0';
  21.               Qn <= '1';
  22.           elsif(J = '1' and K = '0') then
  23.               Q <= '1';
  24.               Qn <= '0';
  25.           elsif(J = '1' and K = '1') then
  26.               Q <= Qn;
  27.               Qn <= Q;
  28.           else
  29.               Q <= 'Z';
  30.               Qn <= 'Z';
  31.           end if;
  32.         end if;
  33.     end process;
  34. end architecture jk_flipflop_sync_arch;
  35.    
  36. -- testbench.vhd
  37.  
  38. library IEEE;
  39. use IEEE.std_logic_1164.all;
  40.  
  41. entity jk_flipflop_sync_tb is
  42. end entity jk_flipflop_sync_tb;
  43.  
  44. architecture jk_flipflop_sync_tb_arch of jk_flipflop_sync_tb is
  45.     signal J, K, clock, Q, Qn : std_logic;
  46. begin
  47.     DUT1 : entity work.jk_flipflop_sync(jk_flipflop_sync_arch)
  48.            port map(J, K, clock, Q, Qn);
  49.     CLOCK_PROCESS : process
  50.     begin
  51.         clock <= '0'; wait for 10ns;
  52.         clock <= '1'; wait for 10ns;
  53.     end process CLOCK_PROCESS;
  54.     STIMULUS : process
  55.     begin
  56.         J <= '0'; K <= '0'; wait for 10ns;
  57.         J <= '1'; K <= '0'; wait for 10ns;
  58.         J <= '0'; K <= '1'; wait for 10ns;
  59.         J <= '1'; K <= '1'; wait for 10ns;
  60.         J <= 'X'; K <= 'X'; wait for 10ns;
  61.     end process STIMULUS;
  62. end architecture jk_flipflop_sync_tb_arch;
Tags: VHDL
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement