STM32F1x.cfg Bluepill STLINK (For 2b model board)

# script for stm32f1x family

#
# stm32 devices support both JTAG and SWD transports.
#
source [find swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME stm32f1x
}

if { [info exists CONNECT_UNDER_RESET] } {
   set _CONNECT_UNDER_RESET $CONNECT_UNDER_RESET
} else {
   set _CONNECT_UNDER_RESET 0
}

if { [info exists ENABLE_LOW_POWER] } {
   set _ENABLE_LOW_POWER $ENABLE_LOW_POWER
} else {
   set _ENABLE_LOW_POWER 0
}

if { [info exists STOP_WATCHDOG] } {
   set _STOP_WATCHDOG $STOP_WATCHDOG
} else {
   set _STOP_WATCHDOG 0
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 4kB (as found on some STM32F100s)
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1000
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      # See STM Document RM0008 Section 26.6.3
      set _CPUTAPID 0x3ba00477
   } {
      # this is the SW-DP tap id not the jtag tap id
      set _CPUTAPID 0x2ba01477
   }
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME

# check for second flash bank
if { [regexp -nocase {stm32f101.g..} $_CHIPNAME] || [regexp -nocase {stm32f101.f..} $_CHIPNAME] || [regexp -nocase {stm32f103.g..} $_CHIPNAME] || [regexp -nocase {stm32f103.f..} $_CHIPNAME] } {
	# STM32F101/103xG 1Mo & STM32F101/103xF 768K have a dual bank flash (XL family).
	# Add the second flash bank.
	set _FLASHNAME $_CHIPNAME.flash1
	flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
}

if { [info exists CLOCK_FREQ] } {
	set _CLOCK_FREQ $CLOCK_FREQ
} else {
	set _CLOCK_FREQ 4000
}
adapter_khz $_CLOCK_FREQ

adapter_nsrst_delay 100
if {[using_jtag]} {
	jtag_ntrst_delay 100
}

if {![using_hla]} {
    # if srst is not fitted use SYSRESETREQ to
    # perform a soft reset
    cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
global _ENABLE_LOW_POWER
global _STOP_WATCHDOG

	if { [expr ($_ENABLE_LOW_POWER == 1)] } {
		# Enable debug during low power modes (uses more power)
		# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
		mmw 0xE0042004 0x00000007 0
	}
	if { [expr ($_ENABLE_LOW_POWER == 0)] } {
		# Disable debug during low power modes
		# DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP)
		mmw 0xE0042004 0 0x00000007
	}
	if { [expr ($_STOP_WATCHDOG == 1)] } {
		# Stop watchdog counters during halt
		# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP
		mmw 0xE0042004 0x00000300 0
	}
	if { [expr ($_STOP_WATCHDOG == 0)] } {
		# Don't stop watchdog counters during halt
		# DBGMCU_CR |= ~(DBG_WWDG_STOP | DBG_IWDG_STOP)
		mmw 0xE0042004 0 0x00000300
	}
}

$_TARGETNAME configure -event reset-init {
global _CLOCK_FREQ

	adapter_khz $_CLOCK_FREQ
}

$_TARGETNAME configure -event gdb-attach {
global _CONNECT_UNDER_RESET

	# Needed to be able to use the connect_assert_srst in reset_config
	# otherwise, wrong value when reading device flash size register
	if { [expr ($_CONNECT_UNDER_RESET == 1)] } {
		reset init
	}
}

$_TARGETNAME configure -event trace-config {
	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
	# change this value accordingly to configure trace pins
	# assignment
	mmw 0xE0042004 0x00000020 0
}

$_TARGETNAME configure -event gdb-detach {
	# to close connection if debug mode entered
	shutdown
}