block RAM?

`timescale 1ns / 1ps

module blockram
    (input clkA, // chipmunk clock
     input clkB, // m2
     input [7:0] dataInA,
     output [7:0] dataOutA,
     input [7:0] dataInB,
     output [7:0] dataOutB,
     input [11:0] addrBusA,
     input [11:0] addrBusB,
     input weMemA,
     input weMemB,
     input enableA,
     input enableB);

    reg [7:0] dataBusOutputA;
    reg [7:0] dataBusOutputB;

    wire enable1A = addrBusA[11:9] == 3'b000 && enableA;
    wire enable1B = addrBusB[11:9] == 3'b000 && enableB;
    wire enable2A = addrBusA[11:9] == 3'b001 && enableA;
    wire enable2B = addrBusB[11:9] == 3'b001 && enableB;
    wire enable3A = addrBusA[11:9] == 3'b010 && enableA;
    wire enable3B = addrBusB[11:9] == 3'b010 && enableB;
    wire enable4A = addrBusA[11:9] == 3'b011 && enableA;
    wire enable4B = addrBusB[11:9] == 3'b011 && enableB;
    wire enable5A = addrBusA[11:9] == 3'b100 && enableA;
    wire enable5B = addrBusB[11:9] == 3'b100 && enableB;
    wire enable6A = addrBusA[11:9] == 3'b101 && enableA;
    wire enable6B = addrBusB[11:9] == 3'b101 && enableB;

    wire [7:0] out1A;
    wire [7:0] out1B;
    wire [7:0] out2A;
    wire [7:0] out2B;
    wire [7:0] out3A;
    wire [7:0] out3B;
    wire [7:0] out4A;
    wire [7:0] out4B;
    wire [7:0] out5A;
    wire [7:0] out5B;
    wire [7:0] out6A;
    wire [7:0] out6B;

    RAMB4_S8_S8 ram1(.ADDRA(addrBusA[8:0]),
                        .CLKA(clkA),
                        .DIA(dataInA),
                        .ENA(enable1A),
                        .RSTA(),
                        .WEA(weMemA),
                        .DOA(out1A),
                        .ADDRB(addrBusB[8:0]),
                        .CLKB(clkB),
                        .DIB(dataInB),
                        .ENB(enable1B),
                        .RSTB(),
                        .WEB(weMemB),
                        .DOB(out1B)
                        );

    RAMB4_S8_S8 ram2(.ADDRA(addrBusA[8:0]),
                        .CLKA(clkA),
                        .DIA(dataInA),
                        .ENA(enable2A),
                        .RSTA(),
                        .WEA(weMemA),
                        .DOA(out2A),
                        .ADDRB(addrBusB[8:0]),
                        .CLKB(clkB),
                        .DIB(dataInB),
                        .ENB(enable2B),
                        .RSTB(),
                        .WEB(weMemB),
                        .DOB(out2B)
                        );
    RAMB4_S8_S8 ram3(.ADDRA(addrBusA[8:0]),
                        .CLKA(clkA),
                        .DIA(dataInA),
                        .ENA(enable3A),
                        .RSTA(),
                        .WEA(weMemA),
                        .DOA(out3A),
                        .ADDRB(addrBusB[8:0]),
                        .CLKB(clkB),
                        .DIB(dataInB),
                        .ENB(enable3B),
                        .RSTB(),
                        .WEB(weMemB),
                        .DOB(out3B)
                        );
    RAMB4_S8_S8 ram4(.ADDRA(addrBusA[8:0]),
                        .CLKA(clkA),
                        .DIA(dataInA),
                        .ENA(enable4A),
                        .RSTA(),
                        .WEA(weMemA),
                        .DOA(out4A),
                        .ADDRB(addrBusB[8:0]),
                        .CLKB(clkB),
                        .DIB(dataInB),
                        .ENB(enable4B),
                        .RSTB(),
                        .WEB(weMemB),
                        .DOB(out4B)
                        );
    RAMB4_S8_S8 ram5(.ADDRA(addrBusA[8:0]),
                        .CLKA(clkA),
                        .DIA(dataInA),
                        .ENA(enable5A),
                        .RSTA(),
                        .WEA(weMemA),
                        .DOA(out5A),
                        .ADDRB(addrBusB[8:0]),
                        .CLKB(clkB),
                        .DIB(dataInB),
                        .ENB(enable5B),
                        .RSTB(),
                        .WEB(weMemB),
                        .DOB(out5B)
                        );
    RAMB4_S8_S8 ram6(.ADDRA(addrBusA[8:0]),
                        .CLKA(clkA),
                        .DIA(dataInA),
                        .ENA(enable6A),
                        .RSTA(),
                        .WEA(weMemA),
                        .DOA(out6A),
                        .ADDRB(addrBusB[8:0]),
                        .CLKB(clkB),
                        .DIB(dataInB),
                        .ENB(enable6B),
                        .RSTB(),
                        .WEB(weMemB),
                        .DOB(out6B)
                        );

        always @* begin
            case (addrBusA[11:9])
                3'b000:
                    dataBusOutputA = out1A;
                3'b001:
                    dataBusOutputA = out2A;
                3'b010:
                    dataBusOutputA = out3A;
                3'b011:
                    dataBusOutputA = out4A;
                3'b100:
                    dataBusOutputA = out5A;
                3'b101:
                    dataBusOutputA = out6A;
                default:
                    dataBusOutputA = 0;
            endcase
        end

        always @* begin
            case (addrBusB[11:9])
                3'b000:
                    dataBusOutputB = out1B;
                3'b001:
                    dataBusOutputB = out2B;
                3'b010:
                    dataBusOutputB = out3B;
                3'b011:
                    dataBusOutputB = out4B;
                3'b100:
                    dataBusOutputB = out5B;
                3'b101:
                    dataBusOutputB = out6B;
                default:
                    dataBusOutputB = 0;
            endcase
        end

        assign dataOutA = dataBusOutputA;
        assign dataOutB = dataBusOutputB;

endmodule