Lab5

// SCROLL.V

module scroll(
    input clk,rst,
    output [15:0] display
    );

    reg [3:0] count;

    always @(posedge clk)
    begin
         if (rst)
             count <= 4'b0000;
         else
             count <= count + 1'b1;
    end

    wire [3:0] a,b,c,d;

    assign a = count;
    assign b = count+1;
    assign c = count+2;
    assign d = count+3;

    wire [3:0] seg_a, seg_b, seg_c, seg_d;

    convert conv_a (.in(a),.out(seg_a));
    convert conv_b (.in(b),.out(seg_b));
    convert conv_c (.in(c),.out(seg_c));
    convert conv_d (.in(d),.out(seg_d));

    assign display = {seg_a,seg_b,seg_c,seg_d};

endmodule



// CONVERT.V

module convert (
    input [3:0] in,
    output [3:0] out
    );

    always @ *
        case (in)
            4'd0 : out = 4'hA;
            4'd1 : out = 4'hA;
            4'd2 : out = 4'hC;
            4'd3 : out = 4'h0;
            4'd4 : out = 4'hF;
            4'd5 : out = 4'hF;
            4'd6 : out = 4'hE;
            4'd7 : out = 4'hE;
            4'd8 : out = 4'hA;
            4'd9 : out = 4'h1;
            4'd10 : out = 4'h5;
            4'd11 : out = 4'hA;
            4'd12 : out = 4'h9;
            4'd13 : out = 4'h0;
            4'd14 : out = 4'h0;
            4'd15 : out = 4'hD;
            default: out = 4'hA;
        endcase

endmodule



// LAB5_TOP.V

module Lab5_top(input clk, rst, sel, output [6:0] seg_L, output [3:0] anode_L);

    // declare necessary wires here
    wire [15:0] value;
    wire s_clk;

    // instantiate modules here
    scroll uut1 (.clk(s_clk),.rst(rst),.display(value));
    slow_clkgen uut2 (.clk(clk),.rst(rst),clk_out(s_clk));
    seg7_driver uut3 (.clk(clk), .rst(rst), .sel(sel), .value(value), .anode_d(4'b0000), .seg_L(seg_L), .anode_L(anode_L));

endmodule