library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;




entity dzielnik is

    Port ( clock : in  STD_LOGIC;
           wyj : out  STD_LOGIC);
end dzielnik;

architecture Behavioral of dzielnik is
signal liczenie : std_logic_vector(7 downto 0):="00000000";
begin
    process(clock)
        begin
if clock = '1' and clock'event then
    liczenie <= liczenie+1;
    end if;
    end process;
    wyj <= liczenie(7);

end Behavioral;