Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- # ////////////////////////////////////////////////////////////////////
- # File name : functional.tcl
- # Author : Anatoly A. Sharapov
- # Email : a.a.sharapov@gmail.com
- # Phone : +7 903 231-11-26
- # Company : PJS MIEA
- # Dep : 311
- # Description : Functional simulation script
- # Last revision : 20.02.2021
- # /////////////////////////////////////////////////////////////////////
- if {!([vsimAuth] == "ALTERA STARTER EDITION")} {
- # https://electronix.ru/forum/index.php?app=forums&module=forums&controller=topic&id=122907
- # main window at full screen
- wm state . zoomed
- }
- # clear transript window of ModelSim or QuestaSim
- .main clear
- # create library
- if [file exists work] {
- vdel -all
- }
- vlib work
- # SystemVerilog Project Files
- variable Project_Path ../RTL/Project
- variable Project_SystemVerilog_Files_Compiled 0
- variable Project_SystemVerilog_Files [glob -nocomplain $Project_Path/*.sv]
- if {[llength $Project_SystemVerilog_Files]} {
- vlog +acc +include+$Project_Path $Project_Path/*.sv
- variable Project_SystemVerilog_Files_Compiled 1
- }
- # Compile SystemVerilog TestBench's Files
- variable TestBench_Path ../RTL/TestBench
- variable TestBench_SystemVerilog_Files_Compiled 0
- variable TestBench_SystemVerilog_Files [glob -nocomplain $TestBench_Path/*.sv]
- if {[llength $TestBench_SystemVerilog_Files]} {
- vlog +acc $TestBench_Path/*.sv
- variable TestBench_SystemVerilog_Files_Compiled 1
- }
- if {!($Project_SystemVerilog_Files_Compiled &&
- $TestBench_SystemVerilog_Files_Compiled )} {
- puts "Error compiling files!"
- Exit
- }
- variable testbench clk1MHzFrom64MHzena_tb
- vsim -L work work.$testbench
- variable wave_window_kind "white_foreground_and_black_background"
- source wave_window_signals.tcl
- wave_window_signals $wave_window_kind $testbench
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement