Zustandsautomat MipsCtrl

library ieee;
use ieee.std_logic_1164.all;

library work;
use work.proc_config.mips_ctrl_state_type;
use work.mipsISA.all;

entity mipsCtrlFsm is
port(clk : in std_logic;
	 rst : in std_logic;
	 op : in std_logic_vector(5 downto 0);
	 jr : in std_logic;
	 regDst : out std_logic_vector(1 downto 0);
	 memRead : out std_logic;
	 memToReg : out std_logic;
	 aluOp : out std_logic_vector(1 downto 0);
	 memWrite : out std_logic;
	 regWrite : out std_logic;
	 aluSrcA : out std_logic;
	 aluSrcB : out std_logic_vector(1 downto 0);
	 pcSrc : out std_logic_vector(1 downto 0);
	 irWrite : out std_logic;
	 IorD : out std_logic;
	 pcWrite : out std_logic;
	 pcWriteCond : out std_logic;
	 lui : out std_logic;

	 -- debug port
	 mipsCtrlState_debug : out mips_ctrl_state_type);
end mipsCtrlFsm;

architecture behavioral of mipsCtrlFsm is
	signal state_reg : mips_ctrl_state_type;
	signal zustand : mips_ctrl_state_type;
	signal folge : mips_ctrl_state_type;
	begin
		z_speicher: process (clk, rst)
		begin
			if clk = '1' and  clk'event then
					if rst = '1' then zustand <= INSTR_FETCH;
					else
						zustand <= folge;
					end if;
				end if;
 		end process z_speicher;

		uebergang: process(op, jr, zustand) -- Folgezustandsberechnung
 		begin


	case zustand is

 	when INSTR_FETCH => folge <= INSTR_DECODE;

 	when INSTR_DECODE => if (op = "100011" or op = "101011") then folge <= MEM_ADDR_CALC;--Memory address computation, LW/SW
 						elsif (op = "001000") or (op = "001001") then folge <= ADDI_CALC; -- ADDI Computation, ADDI/ADDIU
						elsif (op = "000000") then folge <= EXECUTION; --Execution, R-type
						elsif (op = "000011") then folge <= JAL_ADD; --JAL add, JAL
						elsif (op = "000010") then folge <= JUMP_COMPL; -- Jump completion, J
						elsif (op = "001111") then folge <= LUI_COMPL; -- LUI completion, LUI
						elsif (op = "000100") then folge <= BRANCH_COMPL; --Branch completion, BEQ
						else folge <= INSTR_FETCH; --Instruction Fetch
						end if;

	when MEM_ADDR_CALC => if (op = "100011") then folge <= MEM_READ; --Memory access, LW
						 else folge <= MEM_WRITE; --Memory access, SW
						 end if;

	when ADDI_CALC => folge <= ITYPE_COMPL; --I-type completion step

	when EXECUTION => if (jr = '1') then folge <= JR_COMPL; -- JR completion, JR = 1
					   else folge <= RTYPE_COMPL; -- R-type completion step, others
					   end if;

	when JAL_ADD => folge <= LR_WRITE; -- LR write

	when LR_WRITE => folge <= JUMP_COMPL;

	when MEM_READ => folge <= MEM_READ_COMPL;

	--Letzter Uebergang, um die Schaltung zyklisch zu machen
	when MEM_READ_COMPL | MEM_WRITE | ITYPE_COMPL | RTYPE_COMPL | JR_COMPL | JUMP_COMPL | LUI_COMPL | BRANCH_COMPL =>
					folge <= INSTR_FETCH;

 	end case;
	end process uebergang;

	-- noch ein Prozess fuer Ausgabeberechnung;

	ausgabe: process(zustand)
	begin
		--alle Ausgabesignale auf 0 setzen
	regDst <= "00";
	memRead <= '0';
	memToReg <= '0';
	aluOp <= "00";
	memWrite <= '0';
	regWrite <= '0';
	aluSrcA <= '0';
	aluSrcB <= "00";
	pcSrc <= "00";
	irWrite <= '0';
	IorD <= '0';
	pcWrite <= '0';
	pcWriteCond <= '0';
	lui <= '0';

	case zustand is

	when INSTR_FETCH =>
					memRead <= '1'; aluSrcA <= '0'; IorD <= '0'; irWrite <= '1'; aluSrcB <= "01"; aluOp <= "00"; pcWrite <= '1';
  					pcSrc <= "00";
	when INSTR_DECODE =>
					aluSrcA <= '0'; aluSrcB <= "11"; aluOp <= "00";
	when MEM_ADDR_CALC =>
					aluSrcA <= '1'; aluSrcB <= "10"; aluOp <= "00";
	when ADDI_CALC =>
					aluSrcA <= '1'; aluSrcB <= "10"; aluOp <= "00";
	when EXECUTION =>
					aluSrcA <= '1'; aluSrcB <= "00"; aluOp <= "10";
	when JAL_ADD =>
					aluSrcA <= '0'; aluSrcB <= "01"; aluOp <= "00";
	when LUI_COMPL =>
					regDst <= "00"; regWrite <= '1'; memToReg <= '0'; lui <= '1';
	when BRANCH_COMPL =>
					aluSrcA <= '1'; aluSrcB <= "00"; aluOp <= "01"; pcWriteCond <= '1'; pcSrc <= "01";
	when LR_WRITE =>
					regDst <= "10"; regWrite <= '1'; memToReg <= '0'; lui <= '0';
	when MEM_READ =>
					memRead <= '1'; IorD <= '1';
	when MEM_WRITE =>
					memWrite <= '1'; IorD <= '1';
	when ITYPE_COMPL =>
					regDst <= "00"; regWrite <= '1'; memToReg <= '0'; lui <= '0';
	when RTYPE_COMPL =>
					regDst <= "01"; regWrite <= '1'; memToReg <= '0'; lui <= '0';
	when JR_COMPL =>
					pcWrite <= '1'; pcSrc <= "01";
	when JUMP_COMPL =>
					pcWrite <= '1'; pcSrc <= "10";
	when MEM_READ_COMPL =>
					regDst <= "00"; regWrite <= '1'; memToReg <= '1';
	end case;
	end process ausgabe;
	mipsCtrlState_debug <= zustand;

end behavioral;