#richtiger Code

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
use work.proc_config.all;

entity mipsCpu is
	generic(PROG_FILE_NAME : string;
			DATA_FILE_NAME : string
	);
	port(clk : in std_logic;
		 rst : in std_logic;

		 -- instruction insertion ports
		 testMode_debug : in std_logic;
		 testInstruction_debug : in std_logic_vector(31 downto 0);

		 -- ram access ports
		 ramInsertMode_debug : in std_logic; -- wenn das Signal = 1 , werden alle drei unteren weitergegeben; wenn 0 - drei MUX (um zu entscheiden ob unsere oder debug Signale genutyt werden sollen)
		 ramWriteEn_debug : in std_logic;
		 ramWriteAddr_debug : in std_logic_vector(LOG2_NUM_RAM_ELEMENTS - 1 downto 0);
		 ramWriteData_debug : in std_logic_vector(RAM_ELEMENT_WIDTH - 1 downto 0);
		 ramElements_debug : out ram_elements_type;

		 -- register file access port
		 registers_debug : out reg_vector_type;

		 -- intermediate result ports
		 pc_next_debug : out std_logic_vector(PC_WIDTH - 1 downto 0);
		 pc7SegDigits_debug : out pc_7seg_digits_type
	);
end mipsCpu;

architecture structural of mipsCpu is

--Signale Instruction Mux
signal instruction_rom : std_logic_vector(31 downto 0);
signal instruction : std_logic_vector(31 downto 0);

--Signale Instruction Memory
signal addr_pc : std_logic_vector(31 downto 0);

--Signale Control
signal regDst : std_logic;
signal branch : std_logic;
signal memRead : std_logic;
signal memToReg : std_logic;
signal aluOp : std_logic_vector(1 downto 0);
signal memWrite : std_logic;
signal aluSrc : std_logic;
signal regWrite : std_logic; --in bei RegisterFile

--Signale Registers (mittig)
signal writeReg : std_logic_vector(4 downto 0);
signal writeData : std_logic_vector(31 downto 0);

signal readData1 : std_logic_vector(31 downto 0);
signal readData2 : std_logic_vector(31 downto 0);

--Signale RAM
signal ramWriteEn : std_logic;
signal ramWriteAddr : std_logic_vector(9 downto 0);
signal ramWriteData : std_logic_vector(31 downto 0);
signal ramReadData : std_logic_vector(31 downto 0);

--Signale Sign Extend
signal signExtendNumber : std_logic_vector(31 downto 0);

--Signale Shift Left 2
signal shiftedNumber : std_logic_vector(31 downto 0);

--Signale ALU Control
signal operation : std_logic_vector(3 downto 0);

--Signale ALU
signal aluResult : std_logic_vector(31 downto 0);
signal zero : std_logic;
--zusaetzliche Signale
signal muxalu : std_logic_vector(31 downto 0); -- auch der 4. MUX
signal mux3 : std_logic_vector(31 downto 0);
signal muxRamOut : std_logic_vector(31 downto 0); -- auch der 2. Mux
signal muxRamIn : std_logic_vector(31 downto 0);

signal invClk : std_logic; -- invert clk

signal and_out : std_logic;


--Signale Addierer
signal add2 : std_logic_vector(31 downto 0);
signal add1: std_logic_vector(31 downto 0);


begin

	invClk <= not clk;


	with testMode_debug select
		instruction <= testInstruction_debug when '1',
		instruction_rom when others;

	-- Beschreibung der MIPS-CPU ergänzen


	control: entity work.mipsCtrl(structural)  --Beschreibung des Control MIPS
		port map( op(5 downto 0) => instruction(31 downto 26),
			regDst => regDst,
			branch => branch,
			memRead => memRead,
			memToReg => memToReg,
			aluOp(1 downto 0) => aluOp(1 downto 0),
			memWrite => memWrite,
			aluSrc => aluSrc,
			regWrite => regWrite);

	and_out <= branch and zero;


	--ramInsertMode_debug : in std_logic; -- wenn das Signal = 1 , werden alle drei unteren weitergegeben; wenn 0 - drei MUX (um zuentscheiden ob unsere oder debug Signale genutyt werden sollen)
	--ramWriteEn_debug : in std_logic;
	--ramWriteAddr_debug : in std_logic_vector(LOG2_NUM_RAM_ELEMENTS - 1 downto 0);
	--ramWriteData_debug : in std_logic_vector(RAM_ELEMENT_WIDTH - 1 downto 0);

	with ramInsertMode_debug select -- Beschreibung des MUX vor dem RAM (Kommentar oben)
		ramWriteEn <= ramWriteEn_debug when '1',
			      memWrite when others;
	with ramInsertMode_debug select
		ramWriteAddr <= ramWriteAddr_debug when '1',
				aluResult(11 downto 2) when others;
	with ramInsertMode_debug select
		ramWriteData <= ramWriteData_debug when '1',
				readData2 when others;



	with regDst select --Beschreibung des ersten MUXs
		writeReg <= instruction(20 downto 16) when '0',
			    instruction(15 downto 11) when others;

	with memToReg select -- Beschreibung zweites MUXs
		muxRamOut <= ramReadData when '1',
			  aluResult when others;

	with and_out select -- Beschreibung des dritten MUXs
		mux3 <= add1 when '0',
			add2 when others;

	with aluSrc select -- Beschreibung des vierten MUXs
		muxalu <= readData2 when '0',
			  signExtendNumber when others;


	signextend : entity work.signExtend(behavioral) --Beschreibung des SignExtend
 		generic map(INPUT_WIDTH => 16,
    				OUTPUT_WIDTH => 32)
 		port map(number => signed(instruction(15 downto 0)),
    			std_logic_vector(signExtNumber) => signExtendNumber(31 downto 0)); --(31 downto 0) rechts - noetig?


    	shiftleft2 : entity work.leftShifter --Beschreibung ShiftLeft
 		generic map(WIDTH => 32,
   			SHIFT_AMOUNT => 2)
 		port map(number => signExtendNumber,
    			shiftedNumber => shiftedNumber);

    	alucontrol : entity work.aluCtrl --Beschreibung ALU Control
 		port map(f(5 downto 0) => instruction(5 downto 0),
    			aluOp(1 downto 0) => aluOp(1 downto 0),
    			operation(3 downto 0) => operation(3 downto 0));

	alu : entity work.mipsAlu -- Beschreibung ALU
		generic map(WIDTH => 32)
 		port map(ctrl(3 downto 0) => operation(3 downto 0),
    			a => readData1,
    			b => muxalu,
    			result => aluResult,
    			zero => zero);


    	-- Beschreibung Addierers

    	add1 <= std_logic_vector(4 + unsigned(addr_pc));
    	add2 <= std_logic_vector(unsigned(add1) + unsigned(shiftedNumber));

    	--Beschreibung BinToChars
    	binToChar1 : entity work.bin2Char
    	port map(bin => addr_pc(3 downto 0),
	     bitmask => pc7SegDigits_debug(0));

	binToChar2 : entity work.bin2Char
    	port map(bin => addr_pc(7 downto 4),
	     bitmask => pc7SegDigits_debug(1));

	binToChar3 : entity work.bin2Char
    	port map(bin => addr_pc(11 downto 8),
	     bitmask => pc7SegDigits_debug(2));

    	binToChar4 : entity work.bin2Char
    	port map(bin => addr_pc(15 downto 12),
	     bitmask => pc7SegDigits_debug(3));


    	--Beschreibung von RegFile
    	regFile : entity work.regFile
    		generic map(NUM_REGS => 32,
			LOG2_NUM_REGS => 5,
			REG_WIDTH => 32)
    		port map(clk => clk,
    			 rst => rst,
    			 readAddr1 => instruction(25 downto 21),-- in
		 	 readData1 => readData1, --out
		 	 readAddr2 => instruction(20 downto 16), --in
		 	 readData2 => readData2, --out
		 	 writeEn => regWrite, -- Eingang hier, Ausgang von MIPS Control
		 	 writeAddr => writeReg, -- eingang WriteRegister, Ausgang des ersten MUXs
		  	 writeData => muxRamOut, -- eingang WriteData = Ausgang des zweiten MUXs
		 	 reg_vect_debug => registers_debug);


	-- Instruction Memory
	INSTR_ROM: entity work.flashROM(behavioral) -- nutzen Worte (4 Bits) -- PC auf 4 teilen
		generic map(NUM_ELEMENTS => 1024,
		            LOG2_NUM_ELEMENTS => 10,
					ELEMENT_WIDTH => 32,
					INIT_FILE_NAME => PROG_FILE_NAME)
		port map(address => addr_pc(11 downto 2), -- pc_next_debug?
				 readData => instruction_rom);

	-- Data Memory
	DATA_RAM: entity work.flashRAM(behavioral)
		generic map(NUM_ELEMENTS => 1024 ,
					LOG2_NUM_ELEMENTS => 10,
					ELEMENT_WIDTH => 32,
					INIT_FILE_NAME => DATA_FILE_NAME)
		port map(clk => invClk,
				 address => ramWriteAddr,
				 writeEn => ramWriteEn,
				 writeData => ramWriteData,
				 readEn => memRead,
				 readData => ramReadData,
				 ramElements_debug => ramElements_debug);

	PC: entity work.reg --Beschreibung PC
	generic map(
		WIDTH => 32)
	port map(
		clk => clk,
		rst => rst,
		en  => not testMode_debug, -- kA obs richtig is
		D  => mux3,-- in, Ausgang 3 MUXs
		Q  => addr_pc); -- out

	pc_next_debug <= mux3;

end architecture;