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vedic_div32.syr.9ee0fb1

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May 11th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 2.00 secs
  8. Total CPU time to Xst completion: 0.08 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 2.00 secs
  15. Total CPU time to Xst completion: 0.08 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-1-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : NO
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Auto
  74. Reduce Control Sets : Auto
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 2
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" in Library work.
  115. Entity <vedic_div32> compiled.
  116. Entity <vedic_div32> (Architecture <rtl>) compiled.
  117.  
  118. =========================================================================
  119. * Design Hierarchy Analysis *
  120. =========================================================================
  121. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  122.  
  123.  
  124. =========================================================================
  125. * HDL Analysis *
  126. =========================================================================
  127. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  128. WARNING:Xst:2096 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 84: Use of null array slice on signal <d_init_re_reg> is not supported.
  129. WARNING:Xst:2096 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 85: Use of null array slice on signal <init_reg.re_reg> is not supported.
  130. INFO:Xst:2679 - Register <d_init_quo_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  131. INFO:Xst:2679 - Register <init_reg.re_reg<35>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  132. INFO:Xst:2679 - Register <init_reg.re_reg<34>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  133. INFO:Xst:2679 - Register <init_reg.re_reg<33>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  134. INFO:Xst:2679 - Register <init_reg.re_reg<32>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  135. INFO:Xst:2679 - Register <init_reg.re_reg<31>> in unit <vedic_div32> has a constant value of 0 during circuit operation. The register is replaced by logic.
  136. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  137.  
  138.  
  139. =========================================================================
  140. * HDL Synthesis *
  141. =========================================================================
  142.  
  143. Performing bidirectional port resolution...
  144.  
  145. Synthesizing Unit <vedic_div32>.
  146. Related source file is "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd".
  147. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  148. WARNING:Xst:646 - Signal <d_state> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  149. WARNING:Xst:646 - Signal <d_re_tmp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  150. WARNING:Xst:646 - Signal <d_re> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  151. WARNING:Xst:646 - Signal <d_main_re_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  152. WARNING:Xst:1780 - Signal <d_init_re_reg<31>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
  153. WARNING:Xst:646 - Signal <d_init_re_reg<30:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  154. WARNING:Xst:646 - Signal <d_init_quo_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
  155. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  156. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  157. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  158. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  159. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  160. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  161. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  162. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  163. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  164. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  165. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  166. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  167. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  168. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  169. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  170. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  171. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  172. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  173. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  174. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  175. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  176. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  177. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  178. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  179. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  180. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  181. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  182. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  183. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  184. INFO:Xst:1608 - Relative priorities of control signals on register <init_reg.re_reg> differ from those commonly found in the selected device family. This will result in additional logic around the register.
  185. Found finite state machine <FSM_0> for signal <state>.
  186. -----------------------------------------------------------------------
  187. | States | 4 |
  188. | Transitions | 9 |
  189. | Inputs | 3 |
  190. | Outputs | 4 |
  191. | Clock | mclk1 (rising_edge) |
  192. | Reset | state$and0000 (positive) |
  193. | Reset type | synchronous |
  194. | Reset State | fin_state |
  195. | Power Up State | init_state |
  196. | Encoding | automatic |
  197. | Implementation | LUT |
  198. -----------------------------------------------------------------------
  199. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  200. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  201. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  202. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  203. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  204. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  205. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  206. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  207. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  208. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  209. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  210. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  211. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  212. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  213. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  214. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  215. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  216. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  217. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  218. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  219. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  220. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  221. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  222. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  223. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  224. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  225. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  226. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  227. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  228. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  229. WARNING:Xst:737 - Found 5-bit latch for signal <shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  230. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  231. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_4>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  232. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_5>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  233. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_6>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  234. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_7>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  235. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_8>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  236. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.re_reg_9>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  237. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_10>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  238. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_11>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  239. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_12>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  240. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_13>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  241. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_14>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  242. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  243. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_15>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  244. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_20>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  245. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_16>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  246. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_21>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  247. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_17>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  248. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_22>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  249. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_23>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  250. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_18>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  251. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_19>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  252. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_24>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  253. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_25>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  254. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_30>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  255. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_26>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  256. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_31>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  257. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_27>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  258. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_28>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  259. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_29>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  260. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  261. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_1>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  262. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_2>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  263. WARNING:Xst:737 - Found 1-bit latch for signal <init_reg.quo_reg_3>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  264. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 123: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  265. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  266. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  267. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  268. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  269. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  270. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  271. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 34x5-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  272. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 34x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  273. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 122: The result of a 33x32-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  274. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 33x3-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  275. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  276. WARNING:Xst:643 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 208: The result of a 33x4-bit multiplication is partially used. Only the 32 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
  277. Found 34x4-bit multiplier for signal <$mult0000> created at line 208.
  278. Found 34x5-bit multiplier for signal <$mult0001> created at line 208.
  279. Found 34x4-bit multiplier for signal <$mult0002> created at line 208.
  280. Found 34x5-bit multiplier for signal <$mult0003> created at line 208.
  281. Found 5-bit register for signal <i>.
  282. Found 5-bit subtractor for signal <i$addsub0000> created at line 156.
  283. Found 32-bit register for signal <i_quo>.
  284. Found 32-bit register for signal <i_re>.
  285. Found 32-bit register for signal <k_reg.quo>.
  286. Found 36-bit register for signal <k_reg.re_reg>.
  287. Found 1-bit register for signal <k_reg.re_sign>.
  288. Found 32-bit register for signal <main_reg.quo>.
  289. Found 32-bit adder for signal <main_reg.quo$addsub0000> created at line 115.
  290. Found 32-bit subtractor for signal <main_reg.quo$addsub0001> created at line 117.
  291. Found 32-bit register for signal <main_reg.quo_reg>.
  292. Found 32-bit adder for signal <main_reg.quo_reg$addsub0000> created at line 136.
  293. Found 1-bit register for signal <main_reg.quo_sign>.
  294. Found 36-bit register for signal <main_reg.re_reg>.
  295. Found 36-bit adder for signal <main_reg.re_reg$addsub0000> created at line 140.
  296. Found 36-bit adder for signal <main_reg.re_reg$addsub0001> created at line 145.
  297. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 139.
  298. Found 1-bit register for signal <main_reg.re_sign>.
  299. Found 32-bit adder for signal <quo$addsub0000> created at line 242.
  300. Found 32-bit adder for signal <quo$addsub0001> created at line 242.
  301. Found 32-bit adder for signal <quo$addsub0002> created at line 242.
  302. Found 32-bit adder for signal <quo$addsub0003> created at line 242.
  303. Found 32-bit adder for signal <quo$addsub0004> created at line 242.
  304. Found 32-bit adder for signal <quo$addsub0005> created at line 242.
  305. Found 32-bit adder for signal <quo$addsub0006> created at line 242.
  306. Found 32-bit adder for signal <quo$addsub0007> created at line 242.
  307. Found 32-bit subtractor for signal <quo$addsub0008> created at line 242.
  308. Found 32-bit subtractor for signal <quo$addsub0009> created at line 242.
  309. Found 32-bit subtractor for signal <quo$addsub0010> created at line 242.
  310. Found 32-bit subtractor for signal <quo$addsub0011> created at line 242.
  311. Found 32-bit subtractor for signal <quo$addsub0012> created at line 242.
  312. Found 32-bit subtractor for signal <quo$addsub0013> created at line 242.
  313. Found 32-bit subtractor for signal <quo$addsub0014> created at line 242.
  314. Found 32-bit subtractor for signal <quo$addsub0015> created at line 242.
  315. Found 33-bit subtractor for signal <quo_reg_sub$sub0000> created at line 124.
  316. Found 33x32-bit multiplier for signal <quo_tmp$mult0001> created at line 122.
  317. Found 32-bit subtractor for signal <re$addsub0000> created at line 208.
  318. Found 32-bit subtractor for signal <re$addsub0001> created at line 208.
  319. Found 32-bit subtractor for signal <re$addsub0002> created at line 208.
  320. Found 32-bit subtractor for signal <re$addsub0003> created at line 208.
  321. Found 32-bit subtractor for signal <re$addsub0004> created at line 208.
  322. Found 32-bit subtractor for signal <re$addsub0005> created at line 208.
  323. Found 32-bit subtractor for signal <re$addsub0006> created at line 208.
  324. Found 32-bit subtractor for signal <re$addsub0007> created at line 208.
  325. Found 32-bit adder for signal <re$addsub0008> created at line 208.
  326. Found 32-bit adder for signal <re$addsub0009> created at line 208.
  327. Found 32-bit adder for signal <re$addsub0010> created at line 208.
  328. Found 32-bit adder for signal <re$addsub0011> created at line 208.
  329. Found 32-bit adder for signal <re$addsub0012> created at line 208.
  330. Found 32-bit adder for signal <re$addsub0013> created at line 208.
  331. Found 32-bit adder for signal <re$addsub0014> created at line 208.
  332. Found 32-bit adder for signal <re$addsub0015> created at line 208.
  333. Found 29-bit comparator greatequal for signal <re$cmp_ge0000> created at line 208.
  334. Found 32-bit comparator greatequal for signal <re$cmp_ge0001> created at line 208.
  335. Found 31-bit comparator greatequal for signal <re$cmp_ge0002> created at line 208.
  336. Found 32-bit comparator greatequal for signal <re$cmp_ge0003> created at line 208.
  337. Found 30-bit comparator greatequal for signal <re$cmp_ge0004> created at line 208.
  338. Found 32-bit comparator greatequal for signal <re$cmp_ge0005> created at line 208.
  339. Found 31-bit comparator greatequal for signal <re$cmp_ge0006> created at line 208.
  340. Found 32-bit comparator greatequal for signal <re$cmp_ge0007> created at line 208.
  341. Found 32-bit comparator greatequal for signal <re$cmp_ge0008> created at line 208.
  342. Found 32-bit comparator greatequal for signal <re$cmp_ge0009> created at line 208.
  343. Found 31-bit comparator greatequal for signal <re$cmp_ge0010> created at line 208.
  344. Found 32-bit comparator greatequal for signal <re$cmp_ge0011> created at line 208.
  345. Found 30-bit comparator greatequal for signal <re$cmp_ge0012> created at line 208.
  346. Found 32-bit comparator greatequal for signal <re$cmp_ge0013> created at line 208.
  347. Found 31-bit comparator greatequal for signal <re$cmp_ge0014> created at line 208.
  348. Found 32-bit comparator greatequal for signal <re$cmp_ge0015> created at line 208.
  349. Found 33x4-bit multiplier for signal <re$mult0005> created at line 208.
  350. Found 33x3-bit multiplier for signal <re$mult0006> created at line 208.
  351. Found 33x4-bit multiplier for signal <re$mult0007> created at line 208.
  352. Found 33x3-bit multiplier for signal <re$mult0008> created at line 208.
  353. Found 33x3-bit multiplier for signal <re$mult0010> created at line 208.
  354. Found 33x4-bit multiplier for signal <re$mult0011> created at line 208.
  355. Found 33x4-bit multiplier for signal <re$mult0012> created at line 208.
  356. Found 32-bit adder for signal <re$sub0000> created at line 208.
  357. Found 31-bit adder for signal <re$sub0001> created at line 208.
  358. Found 32-bit adder for signal <re$sub0002> created at line 208.
  359. Found 30-bit adder for signal <re$sub0003> created at line 208.
  360. Found 32-bit adder for signal <re$sub0004> created at line 208.
  361. Found 31-bit adder for signal <re$sub0005> created at line 208.
  362. Found 32-bit adder for signal <re$sub0006> created at line 208.
  363. Found 37-bit subtractor for signal <re_reg_sub$sub0000> created at line 125.
  364. Found 33x32-bit multiplier for signal <re_tmp$mult0001> created at line 123.
  365. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 123.
  366. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 123.
  367. Found 32-bit register for signal <tmp_quo_reg>.
  368. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_0$mux0000> created at line 110.
  369. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_1$mux0000> created at line 110.
  370. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_2$mux0000> created at line 110.
  371. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_3$mux0000> created at line 110.
  372. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_4$mux0000> created at line 110.
  373. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_5$mux0000> created at line 110.
  374. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_6$mux0000> created at line 110.
  375. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_7$mux0000> created at line 110.
  376. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_8$mux0000> created at line 110.
  377. Found 1-bit 32-to-1 multiplexer for signal <tmp_quo_reg_shifted_0$mux0000> created at line 112.
  378. Found 36-bit adder for signal <v_re$addsub0000> created at line 197.
  379. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 201.
  380. Found 1-bit 32-to-1 multiplexer for signal <v_reg.quo_reg_30$mux0000> created at line 120.
  381. Summary:
  382. inferred 1 Finite State Machine(s).
  383. inferred 272 D-type flip-flop(s).
  384. inferred 48 Adder/Subtractor(s).
  385. inferred 13 Multiplier(s).
  386. inferred 16 Comparator(s).
  387. inferred 42 Multiplexer(s).
  388. inferred 1 Combinational logic shifter(s).
  389. Unit <vedic_div32> synthesized.
  390.  
  391.  
  392. =========================================================================
  393. HDL Synthesis Report
  394.  
  395. Macro Statistics
  396. # Multipliers : 13
  397. 33x3-bit multiplier : 3
  398. 33x32-bit multiplier : 2
  399. 33x4-bit multiplier : 4
  400. 34x4-bit multiplier : 2
  401. 34x5-bit multiplier : 2
  402. # Adders/Subtractors : 48
  403. 30-bit adder : 1
  404. 31-bit adder : 2
  405. 32-bit adder : 22
  406. 32-bit subtractor : 17
  407. 33-bit subtractor : 1
  408. 36-bit adder : 3
  409. 37-bit subtractor : 1
  410. 5-bit subtractor : 1
  411. # Registers : 43
  412. 1-bit register : 35
  413. 32-bit register : 5
  414. 36-bit register : 2
  415. 5-bit register : 1
  416. # Latches : 65
  417. 1-bit latch : 63
  418. 31-bit latch : 1
  419. 5-bit latch : 1
  420. # Comparators : 16
  421. 29-bit comparator greatequal : 1
  422. 30-bit comparator greatequal : 2
  423. 31-bit comparator greatequal : 4
  424. 32-bit comparator greatequal : 9
  425. # Multiplexers : 42
  426. 1-bit 31-to-1 multiplexer : 1
  427. 1-bit 32-to-1 multiplexer : 41
  428. # Logic shifters : 1
  429. 36-bit shifter arithmetic right : 1
  430. # Xors : 1
  431. 1-bit xor2 : 1
  432.  
  433. =========================================================================
  434.  
  435. =========================================================================
  436. * Advanced HDL Synthesis *
  437. =========================================================================
  438.  
  439. Analyzing FSM <FSM_0> for best encoding.
  440. Optimizing FSM <state/FSM> on signal <state[1:4]> with one-hot encoding.
  441. ------------------------
  442. State | Encoding
  443. ------------------------
  444. init_state | 0001
  445. main_state | 0100
  446. wait_state | 1000
  447. fin_state | 0010
  448. ------------------------
  449.  
  450. =========================================================================
  451. Advanced HDL Synthesis Report
  452.  
  453. Macro Statistics
  454. # FSMs : 1
  455. # Multipliers : 13
  456. 33x3-bit multiplier : 3
  457. 33x32-bit multiplier : 2
  458. 33x4-bit multiplier : 4
  459. 34x4-bit multiplier : 2
  460. 34x5-bit multiplier : 2
  461. # Adders/Subtractors : 48
  462. 30-bit adder : 1
  463. 31-bit adder : 2
  464. 32-bit adder : 22
  465. 32-bit subtractor : 17
  466. 33-bit subtractor : 1
  467. 36-bit adder : 3
  468. 37-bit subtractor : 1
  469. 5-bit subtractor : 1
  470. # Registers : 271
  471. Flip-Flops : 271
  472. # Latches : 65
  473. 1-bit latch : 63
  474. 31-bit latch : 1
  475. 5-bit latch : 1
  476. # Comparators : 16
  477. 29-bit comparator greatequal : 1
  478. 30-bit comparator greatequal : 2
  479. 31-bit comparator greatequal : 4
  480. 32-bit comparator greatequal : 9
  481. # Multiplexers : 42
  482. 1-bit 31-to-1 multiplexer : 1
  483. 1-bit 32-to-1 multiplexer : 41
  484. # Logic shifters : 1
  485. 36-bit shifter arithmetic right : 1
  486. # Xors : 1
  487. 1-bit xor2 : 1
  488.  
  489. =========================================================================
  490.  
  491. =========================================================================
  492. * Low Level Synthesis *
  493. =========================================================================
  494. WARNING:Xst:2677 - Node <Mmult_quo_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  495. WARNING:Xst:2677 - Node <Mmult_re_tmp_mult00013> of sequential type is unconnected in block <vedic_div32>.
  496.  
  497. Optimizing unit <vedic_div32> ...
  498.  
  499. Mapping all equations...
  500. Building and optimizing final netlist ...
  501. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 25.
  502.  
  503. Final Macro Processing ...
  504.  
  505. =========================================================================
  506. Final Register Report
  507.  
  508. Macro Statistics
  509. # Registers : 274
  510. Flip-Flops : 274
  511.  
  512. =========================================================================
  513.  
  514. =========================================================================
  515. * Partition Report *
  516. =========================================================================
  517.  
  518. Partition Implementation Status
  519. -------------------------------
  520.  
  521. No Partitions were found in this design.
  522.  
  523. -------------------------------
  524.  
  525. =========================================================================
  526. * Final Report *
  527. =========================================================================
  528. Final Results
  529. RTL Top Level Output File Name : vedic_div32.ngr
  530. Top Level Output File Name : vedic_div32
  531. Output Format : NGC
  532. Optimization Goal : Speed
  533. Keep Hierarchy : No
  534.  
  535. Design Statistics
  536. # IOs : 130
  537.  
  538. Cell Usage :
  539. # BELS : 9204
  540. # GND : 1
  541. # INV : 530
  542. # LUT1 : 258
  543. # LUT2 : 1088
  544. # LUT3 : 320
  545. # LUT4 : 788
  546. # LUT5 : 425
  547. # LUT6 : 1668
  548. # MUXCY : 2092
  549. # MUXF7 : 117
  550. # VCC : 1
  551. # XORCY : 1916
  552. # FlipFlops/Latches : 373
  553. # FD : 185
  554. # FDE : 72
  555. # FDR : 2
  556. # FDS : 15
  557. # LDC : 1
  558. # LDCP : 98
  559. # Clock Buffers : 2
  560. # BUFG : 1
  561. # BUFGP : 1
  562. # IO Buffers : 129
  563. # IBUF : 65
  564. # OBUF : 64
  565. # DSPs : 6
  566. # DSP48E : 6
  567. =========================================================================
  568.  
  569. Device utilization summary:
  570. ---------------------------
  571.  
  572. Selected Device : 5vlx50tff1136-1
  573.  
  574.  
  575. Slice Logic Utilization:
  576. Number of Slice Registers: 373 out of 28800 1%
  577. Number of Slice LUTs: 5077 out of 28800 17%
  578. Number used as Logic: 5077 out of 28800 17%
  579.  
  580. Slice Logic Distribution:
  581. Number of LUT Flip Flop pairs used: 5154
  582. Number with an unused Flip Flop: 4781 out of 5154 92%
  583. Number with an unused LUT: 77 out of 5154 1%
  584. Number of fully used LUT-FF pairs: 296 out of 5154 5%
  585. Number of unique control sets: 107
  586.  
  587. IO Utilization:
  588. Number of IOs: 130
  589. Number of bonded IOBs: 130 out of 480 27%
  590.  
  591. Specific Feature Utilization:
  592. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  593. Number of DSP48Es: 6 out of 48 12%
  594.  
  595. ---------------------------
  596. Partition Resource Summary:
  597. ---------------------------
  598.  
  599. No Partitions were found in this design.
  600.  
  601. ---------------------------
  602.  
  603.  
  604. =========================================================================
  605. TIMING REPORT
  606.  
  607. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  608. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  609. GENERATED AFTER PLACE-and-ROUTE.
  610.  
  611. Clock Information:
  612. ------------------
  613. -----------------------------------+------------------------+-------+
  614. Clock Signal | Clock buffer(FF name) | Load |
  615. -----------------------------------+------------------------+-------+
  616. mclk1 | BUFGP | 274 |
  617. divisor<0> | IBUF+BUFG | 99 |
  618. -----------------------------------+------------------------+-------+
  619.  
  620. Asynchronous Control Signals Information:
  621. ----------------------------------------
  622. -------------------------------------------------------------+--------------------------+-------+
  623. Control Signal | Buffer(FF name) | Load |
  624. -------------------------------------------------------------+--------------------------+-------+
  625. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  626. b_n_0__and0001(b_n_mux0031<0>1:O) | NONE(b_n_0) | 1 |
  627. b_n_10__and0000(b_n_10__and00001:O) | NONE(b_n_10) | 1 |
  628. b_n_10__and0001(b_n_10__and00011:O) | NONE(b_n_10) | 1 |
  629. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  630. b_n_11__and0001(b_n_11__and00011:O) | NONE(b_n_11) | 1 |
  631. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  632. b_n_12__and0001(b_n_12__and00011:O) | NONE(b_n_12) | 1 |
  633. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  634. b_n_13__and0001(b_n_13__and00011:O) | NONE(b_n_13) | 1 |
  635. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  636. b_n_14__and0001(b_n_14__and00011:O) | NONE(b_n_14) | 1 |
  637. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  638. b_n_15__and0001(b_n_15__and00011:O) | NONE(b_n_15) | 1 |
  639. b_n_16__and0000(b_n_16__and00001:O) | NONE(b_n_16) | 1 |
  640. b_n_16__and0001(b_n_16__and00011:O) | NONE(b_n_16) | 1 |
  641. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  642. b_n_17__and0001(b_n_17__and00011:O) | NONE(b_n_17) | 1 |
  643. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  644. b_n_18__and0001(b_n_18__and00011:O) | NONE(b_n_18) | 1 |
  645. b_n_19__and0000(b_n_19__and00001:O) | NONE(b_n_19) | 1 |
  646. b_n_19__and0001(b_n_19__and00011:O) | NONE(b_n_19) | 1 |
  647. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  648. b_n_1__and0001(b_n_1__and00011:O) | NONE(b_n_1) | 1 |
  649. b_n_20__and0000(b_n_20__and00001:O) | NONE(b_n_20) | 1 |
  650. b_n_20__and0001(b_n_20__and00011:O) | NONE(b_n_20) | 1 |
  651. b_n_21__and0000(b_n_21__and00001:O) | NONE(b_n_21) | 1 |
  652. b_n_21__and0001(b_n_21__and00011:O) | NONE(b_n_21) | 1 |
  653. b_n_22__and0000(b_n_22__and00001:O) | NONE(b_n_22) | 1 |
  654. b_n_22__and0001(b_n_22__and00011:O) | NONE(b_n_22) | 1 |
  655. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  656. b_n_23__and0001(b_n_23__and00011:O) | NONE(b_n_23) | 1 |
  657. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  658. b_n_24__and0001(b_n_24__and00011:O) | NONE(b_n_24) | 1 |
  659. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  660. b_n_25__and0001(b_n_25__and00011:O) | NONE(b_n_25) | 1 |
  661. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  662. b_n_26__and0001(b_n_26__and00011:O) | NONE(b_n_26) | 1 |
  663. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  664. b_n_27__and0001(b_n_27__and00011:O) | NONE(b_n_27) | 1 |
  665. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  666. b_n_28__and0001(b_n_28__and00011:O) | NONE(b_n_28) | 1 |
  667. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  668. b_n_29__and0001(b_n_29__and00011:O) | NONE(b_n_29) | 1 |
  669. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  670. b_n_2__and0001(b_n_2__and00011:O) | NONE(b_n_2) | 1 |
  671. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  672. b_n_30__and0001(b_n_30__and00011:O) | NONE(b_n_30) | 1 |
  673. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  674. b_n_3__and0001(b_n_3__and00011:O) | NONE(b_n_3) | 1 |
  675. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  676. b_n_4__and0001(b_n_4__and00011:O) | NONE(b_n_4) | 1 |
  677. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  678. b_n_5__and0001(b_n_5__and00011:O) | NONE(b_n_5) | 1 |
  679. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  680. b_n_6__and0001(b_n_6__and00011:O) | NONE(b_n_6) | 1 |
  681. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  682. b_n_7__and0001(b_n_7__and00011:O) | NONE(b_n_7) | 1 |
  683. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  684. b_n_8__and0001(b_n_8__and00011:O) | NONE(b_n_8) | 1 |
  685. b_n_9__and0000(b_n_9__and00001:O) | NONE(b_n_9) | 1 |
  686. b_n_9__and0001(b_n_9__and00011:O) | NONE(b_n_9) | 1 |
  687. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  688. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  689. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O)| NONE(init_reg.quo_reg_10)| 1 |
  690. init_reg.quo_reg_10__or0000(init_reg.quo_reg_10__or0000:O) | NONE(init_reg.quo_reg_10)| 1 |
  691. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O)| NONE(init_reg.quo_reg_11)| 1 |
  692. init_reg.quo_reg_11__or0000(init_reg.quo_reg_11__or0000:O) | NONE(init_reg.quo_reg_11)| 1 |
  693. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O)| NONE(init_reg.quo_reg_12)| 1 |
  694. init_reg.quo_reg_12__or0000(init_reg.quo_reg_12__or00001:O) | NONE(init_reg.quo_reg_12)| 1 |
  695. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O)| NONE(init_reg.quo_reg_13)| 1 |
  696. init_reg.quo_reg_13__or0000(init_reg.quo_reg_13__or00001:O) | NONE(init_reg.quo_reg_13)| 1 |
  697. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O)| NONE(init_reg.quo_reg_14)| 1 |
  698. init_reg.quo_reg_14__or0000(init_reg.quo_reg_14__or00001:O) | NONE(init_reg.quo_reg_14)| 1 |
  699. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O)| NONE(init_reg.quo_reg_15)| 1 |
  700. init_reg.quo_reg_15__or0000(init_reg.quo_reg_15__or00001:O) | NONE(init_reg.quo_reg_15)| 1 |
  701. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O)| NONE(init_reg.quo_reg_16)| 1 |
  702. init_reg.quo_reg_16__or0000(init_reg.quo_reg_16__or00001:O) | NONE(init_reg.quo_reg_16)| 1 |
  703. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O)| NONE(init_reg.quo_reg_17)| 1 |
  704. init_reg.quo_reg_17__or0000(init_reg.quo_reg_17__or00001:O) | NONE(init_reg.quo_reg_17)| 1 |
  705. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O)| NONE(init_reg.quo_reg_18)| 1 |
  706. init_reg.quo_reg_18__or0000(init_reg.quo_reg_18__or00001:O) | NONE(init_reg.quo_reg_18)| 1 |
  707. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O)| NONE(init_reg.quo_reg_19)| 1 |
  708. init_reg.quo_reg_19__or0000(init_reg.quo_reg_19__or00001:O) | NONE(init_reg.quo_reg_19)| 1 |
  709. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  710. init_reg.quo_reg_1__or0000(init_reg.quo_reg_1__or00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  711. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O)| NONE(init_reg.quo_reg_20)| 1 |
  712. init_reg.quo_reg_20__or0000(init_reg.quo_reg_20__or00001:O) | NONE(init_reg.quo_reg_20)| 1 |
  713. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O)| NONE(init_reg.quo_reg_21)| 1 |
  714. init_reg.quo_reg_21__or0000(init_reg.quo_reg_21__or00001:O) | NONE(init_reg.quo_reg_21)| 1 |
  715. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O)| NONE(init_reg.quo_reg_22)| 1 |
  716. init_reg.quo_reg_22__or0000(init_reg.quo_reg_22__or00001:O) | NONE(init_reg.quo_reg_22)| 1 |
  717. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O)| NONE(init_reg.quo_reg_23)| 1 |
  718. init_reg.quo_reg_23__or0000(init_reg.quo_reg_23__or00001:O) | NONE(init_reg.quo_reg_23)| 1 |
  719. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O)| NONE(init_reg.quo_reg_24)| 1 |
  720. init_reg.quo_reg_24__or0000(init_reg.quo_reg_24__or00001:O) | NONE(init_reg.quo_reg_24)| 1 |
  721. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O)| NONE(init_reg.quo_reg_25)| 1 |
  722. init_reg.quo_reg_25__or0000(init_reg.quo_reg_25__or00001:O) | NONE(init_reg.quo_reg_25)| 1 |
  723. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O)| NONE(init_reg.quo_reg_26)| 1 |
  724. init_reg.quo_reg_26__or0000(init_reg.quo_reg_26__or00001:O) | NONE(init_reg.quo_reg_26)| 1 |
  725. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O)| NONE(init_reg.quo_reg_27)| 1 |
  726. init_reg.quo_reg_27__or0000(init_reg.quo_reg_27__or00001:O) | NONE(init_reg.quo_reg_27)| 1 |
  727. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O)| NONE(init_reg.quo_reg_28)| 1 |
  728. init_reg.quo_reg_28__or0000(init_reg.quo_reg_28__or00001:O) | NONE(init_reg.quo_reg_28)| 1 |
  729. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O)| NONE(init_reg.quo_reg_29)| 1 |
  730. init_reg.quo_reg_29__or0000(init_reg.quo_reg_29__or00001:O) | NONE(init_reg.quo_reg_29)| 1 |
  731. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  732. init_reg.quo_reg_2__or0000(init_reg.quo_reg_2__or00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  733. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O)| NONE(init_reg.quo_reg_30)| 1 |
  734. init_reg.quo_reg_30__or0000(init_reg.quo_reg_30__or00001:O) | NONE(init_reg.quo_reg_30)| 1 |
  735. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  736. init_reg.quo_reg_3__or0000(init_reg.quo_reg_3__or00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  737. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  738. init_reg.quo_reg_4__or0000(init_reg.quo_reg_4__or00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  739. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  740. init_reg.quo_reg_5__or0000(init_reg.quo_reg_5__or00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  741. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  742. init_reg.quo_reg_6__or0000(init_reg.quo_reg_6__or0000:O) | NONE(init_reg.quo_reg_6) | 1 |
  743. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  744. init_reg.quo_reg_7__or0000(init_reg.quo_reg_7__or00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  745. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  746. init_reg.quo_reg_8__or0000(init_reg.quo_reg_8__or00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  747. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  748. init_reg.quo_reg_9__or0000(init_reg.quo_reg_9__or0000:O) | NONE(init_reg.quo_reg_9) | 1 |
  749. init_reg.re_reg_0__and0000(init_reg.re_reg_0__and00001:O) | NONE(init_reg.re_reg_0) | 1 |
  750. init_reg.re_reg_0__or0000(init_reg.re_reg_0__or00001:O) | NONE(init_reg.re_reg_0) | 1 |
  751. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  752. init_reg.re_reg_10__or0000(init_reg.re_reg_10__or0000:O) | NONE(init_reg.re_reg_10) | 1 |
  753. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  754. init_reg.re_reg_11__or0000(init_reg.re_reg_11__or00001:O) | NONE(init_reg.re_reg_11) | 1 |
  755. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  756. init_reg.re_reg_12__or0000(init_reg.re_reg_12__or0000:O) | NONE(init_reg.re_reg_12) | 1 |
  757. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  758. init_reg.re_reg_13__or0000(init_reg.re_reg_13__or0000:O) | NONE(init_reg.re_reg_13) | 1 |
  759. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  760. init_reg.re_reg_14__or0000(init_reg.re_reg_14__or0000:O) | NONE(init_reg.re_reg_14) | 1 |
  761. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  762. init_reg.re_reg_15__or0000(init_reg.re_reg_15__or00001:O) | NONE(init_reg.re_reg_15) | 1 |
  763. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  764. init_reg.re_reg_16__or0000(init_reg.re_reg_16__or00001:O) | NONE(init_reg.re_reg_16) | 1 |
  765. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  766. init_reg.re_reg_17__or0000(init_reg.re_reg_17__or0000:O) | NONE(init_reg.re_reg_17) | 1 |
  767. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  768. init_reg.re_reg_18__or0000(init_reg.re_reg_18__or0000:O) | NONE(init_reg.re_reg_18) | 1 |
  769. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  770. init_reg.re_reg_19__or0000(init_reg.re_reg_19__or0000:O) | NONE(init_reg.re_reg_19) | 1 |
  771. init_reg.re_reg_1__and0000(init_reg_re_reg_1_mux00311:O) | NONE(init_reg.re_reg_1) | 1 |
  772. init_reg.re_reg_1__or0000(init_reg.re_reg_1__or00001:O) | NONE(init_reg.re_reg_1) | 1 |
  773. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  774. init_reg.re_reg_20__or0000(init_reg.re_reg_20__or0000:O) | NONE(init_reg.re_reg_20) | 1 |
  775. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  776. init_reg.re_reg_21__or0000(init_reg.re_reg_21__or00001:O) | NONE(init_reg.re_reg_21) | 1 |
  777. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  778. init_reg.re_reg_22__or0000(init_reg.re_reg_22__or00001:O) | NONE(init_reg.re_reg_22) | 1 |
  779. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  780. init_reg.re_reg_23__or0000(init_reg.re_reg_23__or00001:O) | NONE(init_reg.re_reg_23) | 1 |
  781. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  782. init_reg.re_reg_24__or0000(init_reg.re_reg_24__or0000:O) | NONE(init_reg.re_reg_24) | 1 |
  783. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  784. init_reg.re_reg_25__or0000(init_reg.re_reg_25__or0000:O) | NONE(init_reg.re_reg_25) | 1 |
  785. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  786. init_reg.re_reg_26__or0000(init_reg.re_reg_26__or0000:O) | NONE(init_reg.re_reg_26) | 1 |
  787. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  788. init_reg.re_reg_27__or0000(init_reg.re_reg_27__or00002:O) | NONE(init_reg.re_reg_27) | 1 |
  789. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  790. init_reg.re_reg_28__or0000(init_reg.re_reg_28__or0000:O) | NONE(init_reg.re_reg_28) | 1 |
  791. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  792. init_reg.re_reg_29__or0000(init_reg.re_reg_29__or0000:O) | NONE(init_reg.re_reg_29) | 1 |
  793. init_reg.re_reg_2__and0000(init_reg_re_reg_2_mux00311:O) | NONE(init_reg.re_reg_2) | 1 |
  794. init_reg.re_reg_2__or0000(init_reg.re_reg_2__or00001:O) | NONE(init_reg.re_reg_2) | 1 |
  795. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001:O) | NONE(init_reg.re_reg_30) | 1 |
  796. init_reg.re_reg_30__and0001(init_reg.re_reg_30__and00011:O) | NONE(init_reg.re_reg_30) | 1 |
  797. init_reg.re_reg_3__and0000(init_reg.re_reg_3__and00001:O) | NONE(init_reg.re_reg_3) | 1 |
  798. init_reg.re_reg_3__or0000(init_reg.re_reg_3__or0000:O) | NONE(init_reg.re_reg_3) | 1 |
  799. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  800. init_reg.re_reg_4__or0000(init_reg.re_reg_4__or00001:O) | NONE(init_reg.re_reg_4) | 1 |
  801. init_reg.re_reg_5__and0000(init_reg.re_reg_5__and00001:O) | NONE(init_reg.re_reg_5) | 1 |
  802. init_reg.re_reg_5__or0000(init_reg.re_reg_5__or0000:O) | NONE(init_reg.re_reg_5) | 1 |
  803. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  804. init_reg.re_reg_6__or0000(init_reg.re_reg_6__or0000:O) | NONE(init_reg.re_reg_6) | 1 |
  805. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and00001:O) | NONE(init_reg.re_reg_7) | 1 |
  806. init_reg.re_reg_7__or0000(init_reg.re_reg_7__or0000:O) | NONE(init_reg.re_reg_7) | 1 |
  807. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  808. init_reg.re_reg_8__or0000(init_reg.re_reg_8__or0000:O) | NONE(init_reg.re_reg_8) | 1 |
  809. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  810. init_reg.re_reg_9__or0000(init_reg.re_reg_9__or0000:O) | NONE(init_reg.re_reg_9) | 1 |
  811. init_reg_re_reg_30_or0000(init_reg_re_reg_30_or00001:O) | NONE(init_reg.quo_reg_31)| 1 |
  812. shift_val_0__or0000(shift_val_0__or00001:O) | NONE(shift_val_0) | 1 |
  813. shift_val_0__or0001(shift_val_0__or00011:O) | NONE(shift_val_0) | 1 |
  814. shift_val_1__and0000(shift_val_1__and00001:O) | NONE(shift_val_1) | 1 |
  815. shift_val_1__or0000(shift_val_1__or00001:O) | NONE(shift_val_1) | 1 |
  816. shift_val_2__and0000(shift_val_2__and00001:O) | NONE(shift_val_2) | 1 |
  817. shift_val_2__or0000(shift_val_2__or00001:O) | NONE(shift_val_2) | 1 |
  818. shift_val_3__and0000(shift_val_3__and00001:O) | NONE(shift_val_3) | 1 |
  819. shift_val_3__or0000(shift_val_3__or00001:O) | NONE(shift_val_3) | 1 |
  820. shift_val_4__and0000(shift_val_4__and00001:O) | NONE(shift_val_4) | 1 |
  821. shift_val_4__or0000(shift_val_4__or00001:O) | NONE(shift_val_4) | 1 |
  822. -------------------------------------------------------------+--------------------------+-------+
  823.  
  824. Timing Summary:
  825. ---------------
  826. Speed Grade: -1
  827.  
  828. Minimum period: 15.045ns (Maximum Frequency: 66.468MHz)
  829. Minimum input arrival time before clock: 11.467ns
  830. Maximum output required time after clock: 10.354ns
  831. Maximum combinational path delay: 14.683ns
  832.  
  833. Timing Detail:
  834. --------------
  835. All values displayed in nanoseconds (ns)
  836.  
  837. =========================================================================
  838. Timing constraint: Default period analysis for Clock 'mclk1'
  839. Clock period: 15.045ns (frequency: 66.468MHz)
  840. Total number of paths / destination ports: 6222480783 / 363
  841. -------------------------------------------------------------------------
  842. Delay: 15.045ns (Levels of Logic = 26)
  843. Source: state_FSM_FFd4 (FF)
  844. Destination: main_reg.quo_reg_31 (FF)
  845. Source Clock: mclk1 rising
  846. Destination Clock: mclk1 rising
  847.  
  848. Data Path: state_FSM_FFd4 to main_reg.quo_reg_31
  849. Gate Net
  850. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  851. ---------------------------------------- ------------
  852. FDR:C->Q 369 0.471 0.670 state_FSM_FFd4 (state_FSM_FFd4)
  853. LUT3:I2->O 7 0.094 0.743 reg_quo_reg<14>1 (reg_quo_reg<14>)
  854. LUT5:I2->O 1 0.094 0.480 tmp_quo_reg_10_mux000031 (N405)
  855. LUT5:I4->O 3 0.094 0.800 tmp_quo_reg_12_mux0000310 (N706)
  856. LUT6:I2->O 3 0.094 0.347 tmp_quo_reg_13_mux0000 (tmp_quo_reg_13_mux0000)
  857. DSP48E:B13->PCOUT43 1 3.832 0.000 Mmult_quo_tmp_mult0001 (Mmult_quo_tmp_mult0001_PCOUT_to_Mmult_quo_tmp_mult00011_PCIN_43)
  858. DSP48E:PCIN43->PCOUT18 1 2.013 0.000 Mmult_quo_tmp_mult00011 (Mmult_quo_tmp_mult00011_PCOUT_to_Mmult_quo_tmp_mult00012_PCIN_18)
  859. DSP48E:PCIN18->P0 1 1.816 0.480 Mmult_quo_tmp_mult00012 (quo_tmp_mult0001<17>)
  860. LUT6:I5->O 1 0.094 0.000 Msub_quo_reg_sub_sub0000_lut<17> (Msub_quo_reg_sub_sub0000_lut<17>)
  861. MUXCY:S->O 1 0.372 0.000 Msub_quo_reg_sub_sub0000_cy<17> (Msub_quo_reg_sub_sub0000_cy<17>)
  862. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<18> (Msub_quo_reg_sub_sub0000_cy<18>)
  863. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<19> (Msub_quo_reg_sub_sub0000_cy<19>)
  864. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<20> (Msub_quo_reg_sub_sub0000_cy<20>)
  865. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<21> (Msub_quo_reg_sub_sub0000_cy<21>)
  866. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<22> (Msub_quo_reg_sub_sub0000_cy<22>)
  867. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<23> (Msub_quo_reg_sub_sub0000_cy<23>)
  868. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<24> (Msub_quo_reg_sub_sub0000_cy<24>)
  869. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<25> (Msub_quo_reg_sub_sub0000_cy<25>)
  870. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<26> (Msub_quo_reg_sub_sub0000_cy<26>)
  871. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<27> (Msub_quo_reg_sub_sub0000_cy<27>)
  872. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<28> (Msub_quo_reg_sub_sub0000_cy<28>)
  873. MUXCY:CI->O 1 0.026 0.000 Msub_quo_reg_sub_sub0000_cy<29> (Msub_quo_reg_sub_sub0000_cy<29>)
  874. XORCY:CI->O 2 0.357 0.341 Msub_quo_reg_sub_sub0000_xor<30> (quo_reg_sub_sub0000<30>)
  875. INV:I->O 1 0.238 0.000 Madd_main_reg_quo_reg_not0000<30>1_INV_0 (Madd_main_reg_quo_reg_not0000<30>)
  876. MUXCY:S->O 0 0.372 0.000 Madd_main_reg.quo_reg_addsub0000_cy<30> (Madd_main_reg.quo_reg_addsub0000_cy<30>)
  877. XORCY:CI->O 1 0.357 0.480 Madd_main_reg.quo_reg_addsub0000_xor<31> (main_reg_quo_reg_addsub0000<31>)
  878. LUT3:I2->O 1 0.094 0.000 main_reg_quo_reg_mux0000<31>1 (main_reg_quo_reg_mux0000<31>)
  879. FD:D -0.018 main_reg.quo_reg_31
  880. ----------------------------------------
  881. Total 15.045ns (10.704ns logic, 4.341ns route)
  882. (71.1% logic, 28.9% route)
  883.  
  884. =========================================================================
  885. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  886. Total number of paths / destination ports: 7 / 7
  887. -------------------------------------------------------------------------
  888. Offset: 2.334ns (Levels of Logic = 2)
  889. Source: go (PAD)
  890. Destination: i_0 (FF)
  891. Destination Clock: mclk1 rising
  892.  
  893. Data Path: go to i_0
  894. Gate Net
  895. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  896. ---------------------------------------- ------------
  897. IBUF:I->O 3 0.818 0.491 go_IBUF (go_IBUF)
  898. LUT3:I2->O 5 0.094 0.358 i_or00011 (i_or0001)
  899. FDS:S 0.573 i_0
  900. ----------------------------------------
  901. Total 2.334ns (1.485ns logic, 0.849ns route)
  902. (63.6% logic, 36.4% route)
  903.  
  904. =========================================================================
  905. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  906. Total number of paths / destination ports: 10155 / 99
  907. -------------------------------------------------------------------------
  908. Offset: 11.467ns (Levels of Logic = 12)
  909. Source: divisor<31> (PAD)
  910. Destination: init_reg.re_reg_23 (LATCH)
  911. Destination Clock: divisor<0> falling
  912.  
  913. Data Path: divisor<31> to init_reg.re_reg_23
  914. Gate Net
  915. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  916. ---------------------------------------- ------------
  917. IBUF:I->O 183 0.818 0.731 divisor_31_IBUF (divisor_31_IBUF)
  918. LUT2:I0->O 28 0.094 0.703 shift_val_Q_1_or00001 (shift_val_Q_1_or0000)
  919. LUT6:I4->O 9 0.094 1.113 init_reg_re_reg_10_or00081 (init_reg_re_reg_10_or0008)
  920. LUT6:I0->O 13 0.094 1.135 init_reg_re_reg_15_or00021 (init_reg_re_reg_15_or0002)
  921. LUT6:I0->O 14 0.094 1.140 init_reg_re_reg_21_or00021 (init_reg_re_reg_21_or0002)
  922. LUT6:I0->O 1 0.094 0.973 init_reg_re_reg_23_mux0031129 (init_reg_re_reg_23_mux0031129)
  923. LUT6:I1->O 1 0.094 0.789 init_reg_re_reg_23_mux0031177_SW0 (N379)
  924. LUT6:I2->O 1 0.094 0.973 init_reg_re_reg_23_mux0031177 (init_reg_re_reg_23_mux0031177)
  925. LUT6:I1->O 1 0.094 0.480 init_reg_re_reg_23_mux0031240_SW0 (N381)
  926. LUT4:I3->O 1 0.094 0.789 init_reg_re_reg_23_mux0031240 (init_reg_re_reg_23_mux0031240)
  927. LUT6:I2->O 1 0.094 0.789 init_reg_re_reg_23_mux0031311_SW0 (N383)
  928. LUT6:I2->O 3 0.094 0.000 init_reg_re_reg_23_mux0031311 (init_reg_re_reg_23_mux0031)
  929. LDCP:D -0.071 init_reg.re_reg_23
  930. ----------------------------------------
  931. Total 11.467ns (1.852ns logic, 9.615ns route)
  932. (16.2% logic, 83.8% route)
  933.  
  934. =========================================================================
  935. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  936. Total number of paths / destination ports: 154455 / 64
  937. -------------------------------------------------------------------------
  938. Offset: 10.354ns (Levels of Logic = 22)
  939. Source: i_re_2 (FF)
  940. Destination: quo<31> (PAD)
  941. Source Clock: mclk1 rising
  942.  
  943. Data Path: i_re_2 to quo<31>
  944. Gate Net
  945. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  946. ---------------------------------------- ------------
  947. FD:C->Q 44 0.471 0.919 i_re_2 (i_re_2)
  948. LUT4:I0->O 1 0.094 0.000 Mcompar_re_cmp_ge0012_lut<0> (Mcompar_re_cmp_ge0012_lut<0>)
  949. MUXCY:S->O 1 0.372 0.000 Mcompar_re_cmp_ge0012_cy<0> (Mcompar_re_cmp_ge0012_cy<0>)
  950. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<1> (Mcompar_re_cmp_ge0012_cy<1>)
  951. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<2> (Mcompar_re_cmp_ge0012_cy<2>)
  952. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<3> (Mcompar_re_cmp_ge0012_cy<3>)
  953. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<4> (Mcompar_re_cmp_ge0012_cy<4>)
  954. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<5> (Mcompar_re_cmp_ge0012_cy<5>)
  955. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<6> (Mcompar_re_cmp_ge0012_cy<6>)
  956. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<7> (Mcompar_re_cmp_ge0012_cy<7>)
  957. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<8> (Mcompar_re_cmp_ge0012_cy<8>)
  958. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<9> (Mcompar_re_cmp_ge0012_cy<9>)
  959. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<10> (Mcompar_re_cmp_ge0012_cy<10>)
  960. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<11> (Mcompar_re_cmp_ge0012_cy<11>)
  961. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<12> (Mcompar_re_cmp_ge0012_cy<12>)
  962. MUXCY:CI->O 1 0.026 0.000 Mcompar_re_cmp_ge0012_cy<13> (Mcompar_re_cmp_ge0012_cy<13>)
  963. MUXCY:CI->O 71 0.254 1.204 Mcompar_re_cmp_ge0012_cy<14> (re_cmp_ge0012)
  964. LUT6:I0->O 1 0.094 0.710 re<9>66 (re<9>66)
  965. LUT6:I3->O 1 0.094 0.973 re<9>93 (re<9>93)
  966. LUT5:I0->O 1 0.094 0.789 re<9>125 (re<9>125)
  967. LUT6:I2->O 1 0.094 0.973 re<9>195 (re<9>195)
  968. LUT5:I0->O 1 0.094 0.336 re<9>233 (re_9_OBUF)
  969. OBUF:I->O 2.452 re_9_OBUF (re<9>)
  970. ----------------------------------------
  971. Total 10.354ns (4.451ns logic, 5.903ns route)
  972. (43.0% logic, 57.0% route)
  973.  
  974. =========================================================================
  975. Timing constraint: Default path analysis
  976. Total number of paths / destination ports: 82309045 / 64
  977. -------------------------------------------------------------------------
  978. Delay: 14.683ns (Levels of Logic = 44)
  979. Source: divisor<2> (PAD)
  980. Destination: quo<2> (PAD)
  981.  
  982. Data Path: divisor<2> to quo<2>
  983. Gate Net
  984. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  985. ---------------------------------------- ------------
  986. IBUF:I->O 116 0.818 0.719 divisor_2_IBUF (divisor_2_IBUF)
  987. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0012_Madd_lut<2> (Mmult_re_mult0012_Madd_lut<2>)
  988. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0012_Madd_cy<2> (Mmult_re_mult0012_Madd_cy<2>)
  989. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<3> (Mmult_re_mult0012_Madd_cy<3>)
  990. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<4> (Mmult_re_mult0012_Madd_cy<4>)
  991. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<5> (Mmult_re_mult0012_Madd_cy<5>)
  992. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<6> (Mmult_re_mult0012_Madd_cy<6>)
  993. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<7> (Mmult_re_mult0012_Madd_cy<7>)
  994. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<8> (Mmult_re_mult0012_Madd_cy<8>)
  995. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<9> (Mmult_re_mult0012_Madd_cy<9>)
  996. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<10> (Mmult_re_mult0012_Madd_cy<10>)
  997. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<11> (Mmult_re_mult0012_Madd_cy<11>)
  998. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<12> (Mmult_re_mult0012_Madd_cy<12>)
  999. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<13> (Mmult_re_mult0012_Madd_cy<13>)
  1000. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<14> (Mmult_re_mult0012_Madd_cy<14>)
  1001. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<15> (Mmult_re_mult0012_Madd_cy<15>)
  1002. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<16> (Mmult_re_mult0012_Madd_cy<16>)
  1003. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<17> (Mmult_re_mult0012_Madd_cy<17>)
  1004. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<18> (Mmult_re_mult0012_Madd_cy<18>)
  1005. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<19> (Mmult_re_mult0012_Madd_cy<19>)
  1006. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<20> (Mmult_re_mult0012_Madd_cy<20>)
  1007. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<21> (Mmult_re_mult0012_Madd_cy<21>)
  1008. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<22> (Mmult_re_mult0012_Madd_cy<22>)
  1009. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<23> (Mmult_re_mult0012_Madd_cy<23>)
  1010. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<24> (Mmult_re_mult0012_Madd_cy<24>)
  1011. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<25> (Mmult_re_mult0012_Madd_cy<25>)
  1012. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<26> (Mmult_re_mult0012_Madd_cy<26>)
  1013. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<27> (Mmult_re_mult0012_Madd_cy<27>)
  1014. MUXCY:CI->O 1 0.026 0.000 Mmult_re_mult0012_Madd_cy<28> (Mmult_re_mult0012_Madd_cy<28>)
  1015. XORCY:CI->O 1 0.357 0.576 Mmult_re_mult0012_Madd_xor<29> (Mmult_re_mult0012_Madd_29)
  1016. LUT2:I0->O 1 0.094 0.000 Mmult_re_mult0012_Madd1_lut<29> (Mmult_re_mult0012_Madd1_lut<29>)
  1017. MUXCY:S->O 1 0.372 0.000 Mmult_re_mult0012_Madd1_cy<29> (Mmult_re_mult0012_Madd1_cy<29>)
  1018. XORCY:CI->O 1 0.357 0.336 Mmult_re_mult0012_Madd1_xor<30> (re_mult0012<30>)
  1019. INV:I->O 1 0.238 0.000 Madd_re_not0006<30>1_INV_0 (Madd_re_not0006<30>)
  1020. MUXCY:S->O 0 0.372 0.000 Madd_re_sub0006_cy<30> (Madd_re_sub0006_cy<30>)
  1021. XORCY:CI->O 2 0.357 0.794 Madd_re_sub0006_xor<31> (re_sub0006<31>)
  1022. LUT4:I0->O 0 0.094 0.000 Mcompar_re_cmp_ge0015_lutdi15 (Mcompar_re_cmp_ge0015_lutdi15)
  1023. MUXCY:DI->O 8 0.590 0.518 Mcompar_re_cmp_ge0015_cy<15> (re_cmp_ge0015)
  1024. LUT4:I3->O 61 0.094 1.202 quo<2>1111 (N718)
  1025. LUT6:I0->O 1 0.094 0.710 re<2>186_SW0 (N483)
  1026. LUT6:I3->O 1 0.094 0.710 re<2>186 (re<2>186)
  1027. LUT6:I3->O 1 0.094 1.069 re<2>271_SW0 (N4051)
  1028. LUT6:I0->O 1 0.094 0.336 re<2>271 (re_2_OBUF)
  1029. OBUF:I->O 2.452 re_2_OBUF (re<2>)
  1030. ----------------------------------------
  1031. Total 14.683ns (7.713ns logic, 6.970ns route)
  1032. (52.5% logic, 47.5% route)
  1033.  
  1034. =========================================================================
  1035.  
  1036.  
  1037. Total REAL time to Xst completion: 1269.00 secs
  1038. Total CPU time to Xst completion: 1260.91 secs
  1039.  
  1040. -->
  1041.  
  1042.  
  1043. Total memory usage is 881508 kilobytes
  1044.  
  1045. Number of errors : 0 ( 0 filtered)
  1046. Number of warnings : 90 ( 0 filtered)
  1047. Number of infos : 36 ( 0 filtered)
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