library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity VGA is
    port
    (
        CLK : in std_logic;
        RST 	: in std_logic := '1';
		  HSYNC	: OUT STD_logic;
		  VSYNC	: OUT std_logic;
		  RGB		: OUT std_logic_vector(2 downto 0);
		  RGB_in	: IN STD_logic_vector(2 downto 0);
		  Reg_ADDR:	OUT	std_logic_vector(12 downto 0);
		  Reg_DATA:	IN		STD_logic_vector(7 downto 0)
    );

end entity;

architecture Behavioral of VGA is

constant HD	:	integer := 799;
constant HFP	:	integer := 40;
constant HSP	:	integer := 128;
constant HBP	:	integer := 88;

constant VD	:	integer := 599;
constant VFP	:	integer := 1;
constant VSP	:	integer := 4;
constant VBP	:	integer := 23;

-- 	constant HD	:	integer := 319;
-- 	constant HFP	:	integer := 8;
-- 	constant HSP	:	integer := 32;
-- 	constant HBP	:	integer := 40;
--
-- 	constant VD	:	integer := 199;
-- 	constant VFP	:	integer := 3;
-- 	constant VSP	:	integer := 6;
-- 	constant VBP	:	integer := 6;

--		constant HD	:	integer := 639;
--		constant HFP	:	integer := 16;
--		constant HSP	:	integer := 96;
--		constant HBP	:	integer := 48;
--
--		constant VD	:	integer := 479;
--		constant VFP	:	integer := 10;
--		constant VSP	:	integer := 2;
--		constant VBP	:	integer := 33;
	constant W_x_size		:	integer:= 512;
	constant	W_H_Start	:	integer:= ((HD - W_x_size)/2);
	constant W_y_size		:	integer:= 512;
	constant	W_V_Start	:	integer:= ((VD - W_y_size)/2);

	signal hPos		: integer :=0;
	signal vPos		: integer :=0;
	signal video_on:std_logic:='0';
	signal clk25	: std_logic;


begin


clk_div:process(CLK)
begin
--			if rising_edge(clk25) then
--				clk25 <= not clk25;
--			end if;

end process;

clk25 <= CLK;

Hor_pos_cnt:process(clk25,RST)
begin
	if (RST = '0') then
		hPos <= 0;
	elsif rising_edge(clk25) then
		if (hPos = (HD + HFP + HSP + HBP))then
			hPos <= 0;
		else
			hPos <= hPos +1;
		end if;
	end if;
end process;


Ver_pos_cnt:process(clk25,RST, hPos)
begin
	if (RST = '0') then
		vPos <= 0;
	elsif rising_edge(clk25) then
		if(hPos = (HD + HFP + HSP + HBP))then
			if (vPos = (VD + VFP + VSP + VBP))then
				vPos <= 0;
			else
				vPos <= vPos +1;
			end if;
		end if;
	end if;
end process;

Hor_sync:process(clk25,RST,hPos)
begin
	if (RST = '0') then
		HSYNC <= '0';
	elsif rising_edge(clk25) then
		if(hPos <= (HD + HFP) OR hPos >= (HD + HFP + HSP))then
			HSYNC <= '1';
		else
			HSYNC <= '0';
		end if;
	end if;
end process;

Ver_sync:process(clk25,RST,vPos)
begin
	if (RST = '0') then
		VSYNC <= '0';
	elsif rising_edge(clk25) then
		if(vPos <= (VD + VFP) OR vPos >= (VD + VFP + VSP))then
			VSYNC <= '1';
		else
			VSYNC <= '0';
		end if;
	end if;
end process;

videoOn:process(clk25,RST,hPos,vPos)
begin
	if (RST = '0') then
		video_on <= '0';
	elsif rising_edge(clk25) then
		if(hPos <= HD AND vPos <= VD)then
			video_on <= '1';
		else
			video_on <= '0';
		end if;
	end if;
end process;


draw:process(clk25, RST, hPos, vPos, video_on,RGB_in)
begin
	if(RST = '0')then
		RGB <= "000";
	elsif rising_edge(clk25) then
		if(video_on = '1')then
			if((hPos >= W_H_Start and hPos <= (W_H_Start + W_X_size)) AND (vPos >= W_V_Start and vPos <= (W_V_Start + W_y_size)))then
				--RGB <= "001";
				RGB <= RGB_in;
			else
				RGB <= "000";
			end if;
		else
			RGB <= "000";
		end if;
	end if;
end process;



draw_text:process(clk25,RST,hPos,vPos,video_on)
begin
if (RST = '0')then

elsif rising_edge(clk25)then
	if (video_on = '1')then
	Reg_ADDR <= hPos /8;
	end if;
end if;
end process;




--   Red_Line:process(CLK,vPos,hPos,video_on,RST)
--   begin
--   	if (RST = '0') then
--   		RGB <= "000";
--   	elsif rising_edge(CLK) then
--   		if (video_on = '1') then
--   			if (hPos >=300 and  hPos <= 600)then
--   				if(vPos >=100 and vPos <= 400)then
--   					RGB <= "111";
--   				else
--   					RGB <= "000";
--   				end if;
--   			end if;
--
--
--   		else
--   			RGB <= "000";
--   		end if;
--   	end if;
--   end process;

end Behavioral;