HWPTI_2024_Blatt2_Aufgabe1

------------------------------------------------------------------------------
--  Paket fuer die Funktionen zur die Abbildung von ARM-Registeradressen
--  auf Adressen des physischen Registerspeichers (5-Bit-Adressen)
------------------------------------------------------------------------------
--  Datum:      05.11.2013
--  Version:    0.1
------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ArmTypes.all;

--------------------------------------------------------------------------------
--  Bezeichner fuer die verschiedenen Registeradressen
--------------------------------------------------------------------------------
    subtype RegAddress is std_logic_vector(3 downto 0);
    constant R0 : RegAddress := "0000";
    constant R1 : RegAddress := "0001";
    constant R2 : RegAddress := "0010";
    constant R3 : RegAddress := "0011";
    constant R4 : RegAddress := "0100";
    constant R5 : RegAddress := "0101";
    constant R6 : RegAddress := "0110";
    constant R7 : RegAddress := "0111";
    constant R8 : RegAddress := "1000";
    constant R9 : RegAddress := "1001";
    constant R10    : RegAddress := "1010";
    constant R11    : RegAddress := "1011";
    constant R12    : RegAddress := "1100";
    constant R13    : RegAddress := "1101";
    constant R14    : RegAddress := "1110";
    constant R15    : RegAddress := "1111";
--------------------------------------------------------------------------------

package ArmRegaddressTranslation is

    function get_internal_address(
        EXT_ADDRESS: std_logic_vector(3 downto 0);
        THIS_MODE: std_logic_vector(4 downto 0);
        USER_BIT : std_logic)
    return std_logic_vector;

end package ArmRegaddressTranslation;

package body ArmRegAddressTranslation is

function get_internal_address(
    EXT_ADDRESS: std_logic_vector(3 downto 0);
    THIS_MODE: std_logic_vector(4 downto 0);
    USER_BIT : std_logic)
    return std_logic_vector
is
    Signal res : std_logic_vector(4 downto 0) := (others => '0');
    Signal d_out: integer;
--------------------------------------------------------------------------------
--  Raum fuer lokale Variablen innerhalb der Funktion
--------------------------------------------------------------------------------

    begin
--------------------------------------------------------------------------------
--  Functionscode
--------------------------------------------------------------------------------

   process(EXT_ADDRESS, USER_BIT, THIS_MODE)
   begin
    --fuer register R0-R7 unabhaengig vom modi einfach die gleiche adresse
    if((unsigned(EXT_ADDRESS) >=R0 and unsigned(EXT_ADDRESS) <=R7 or unsigned(EXT_ADDRESS) == R15 or
        USER_BIT = 1) then
            res(3 downto 0) <= EXT_ADDRESS;

    --fuer register R8-R12 entweder normal die gleiche adresse ODER wenn Mode = FIQ inkrementieren
    elsif (unsigned(EXT_ADDRESS) >= R8 and unsigned(EXT_ADDRESS) <= 12)) then
        if(THIS_MODE = FIQ) then
            d_out <= (to_integer(unsigned(EXT_ADRESS)) + 8);
            res <= to_std_logic_vector(d_out);
        else res(3 downto 0) <= EXT_ADDRESS;

     --fuer restlichen register je nach mode
     else
        if(THIS_MODE = IRQ) then
            d__out <= (to_integer(unsigned(EXT_ADRESS)) + 10);
            res <= to_std_logic_vector(d_out);
        elsif(THIS_MODE = SUPERVISOR) then
            d__out <= (to_integer(unsigned(EXT_ADRESS)) + 12);
            res <= to_std_logic_vector(d_out);
        elsif(THIS_MODE = UNDEFINED) then
            d__out <= (to_integer(unsigned(EXT_ADRESS)) + 14);
            res <= to_std_logic_vector(d_out);
        end if;

    end process;

    return res;

end function get_internal_address;

end package body ArmRegAddressTranslation;