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- Schematic:
- - See an almost identical use in my design to see how I dealt with this: https://github.com/tinyvision-ai-inc/Vision-FPGA-SoM
- - Himax analog supply is max of 3.0V. I wouldnt use an LDO set to 3.0V for this as it will exceed 3.0V due to part-part variations, why dont you use 2.8V?
- - You could solve the IO voltage issue to the Himax by setting the digital IO voltage to 2.8V. You will need to ensure the flash and SRAM can handle this though and its an unusual voltage for the IO.
- - Bring pixel clock into a global clock buffer if you can
- - Dual LDO is expensive, there are much cheaper alternatives for 7-10 cents. eg. https://octopart.com/search?autosugg_idx=0¤cy=USD&oq=ap2127k-3.3trg1&q=ap2127k-3.3trg1&specs=1
- - Replace D1 with a regular silicon diode, schottky will not drop enough to be within the spec., Also may save a few cents with an 1N4148.
- - Too much decoupling? Why do you need 3 decades of decoupling? Get rid of the 10nF?
- - Use a resistor network to pullup instead of discretes, will save you placement cost
- - Too many 10uF on the 3V
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