//code

module dff(
    input logic clk, d, rst,
    output logic q
    );
    always @(posedge rst, posedge clk)
    begin
    if(rst)
    q<=0;
    else
    q<=d;
    end
endmodule

//testbench

module test_tb();
logic clk, d, rst;
logic q;
dff uut(clk, d, rst, q);

initial
begin
clk = 0;
forever #10
clk = ~clk;
end

initial
begin
rst = 1; d=0;
#10
rst = 0; d = 1;
#5
rst = 1;
#10
rst = 0; d = 0;
#10
rst = 0; d = 0;
#10
$finish;
end
endmodule