CA_LAB12/13

module control_unit(
  input clk, //synchronization signal
  input reset_n, //asynchronous reset signal
  input begin_sig, //synchronous input; replaces the BEGIN signal due to begin being a reserved Verilog word
  output end_sig, //output; replaces signal END to avoid using the reserved Verilog word end
  input count_7, //synchronous input; marks the completion of the 7 iterations
  input q_0, //synchronous input; indicate the value of xi stored in Q[0]
  output [6:0] c //outputs; the control signals for the multiplier device
);

   reg [7:0] state,state_next;
   always @ (*) begin
    state_next = {state[6],state[5],state[4]& count_7, state[2] & ~q_0 |state[3] |  state[4] & ~count_7 & ~ q_0,state[2] & q_0 | state[4] &~ count_7 & q_0, state[1], begin_sig & state[0], state[0] & ~begin_sig | state[7] };
 end

 assign {c,end_sig} = state;
 always @ (posedge clk or negedge reset_n )
    if (!reset_n) state<= 8'd1;
    else state <= state_next;
 endmodule




==============================================================================================================

module counter(clk, count_up, clear, count_7);
  input clk; //synchronization signal
  input clear; //synchronous input; clears counter's content
  input count_up; //synchronous input; increment counter's content
  output count_7; //active when counter's content is 111

reg [2:0] state, state_next;

   always @(*) begin
       state_next = 3'd0;
       if (clear)
         state_next = 3'd0;
       else if (count_up)
          state_next = {state[2]^(state[1] & state[0]), state[1]^state[0], ~state[0] };
          else
          state_next = state;
          end
  always@(posedge clk or posedge clear)
      state <= state_next;

  assign count_7 = state[2] & state[1] & state[0]; // sau &state

endmodule



==============================================================================================================

module sm_multiplier(
  input clk, //synchronization signal
  input reset, //asynchronous reset signal
  input begin_sig, //synchronous input; external state signal triggering the start of the multiplication procedure
  output end_sig, //output; marks the completion of multiplication procedure
  input [7:0] inbus, //synchronous input; hold the operands to be read by the procedure
  output [7:0] outbus //output: outbus data lines; written only when load_outbus is active (high) and kept in high impedance otherwise
);
counter cnt (
   .clk(clk),
   .reset(~clear),
   .begin



==============================================================================================================

module register_a(clk, clear, load_adder_result, adder_result, load_sign, sign, shift, shift_out, load_outbus, outbus, accumulator_value);
  input clk; //synchronization signal
  input clear; //synchronous input; clears register's content
  input load_adder_result; //synchronous input; enables the loading of adder's result into the register
  input [7:0] adder_result; //input: the adder's result on 8 bits having the cout concatenated as on the msb position
  input load_sign; //synchronous input; enables the loading of the register's msb value
  input sign; //input: the value of the msb to be loaded into register when load_sign is active (high)
  input shift; //synchronous input; activates right-shifting of register's content with 1 position; the value shifted into is 0.
  output shift_out; //alias for register's lsb (the value that is to be lost because of the right-shifting)
  input load_outbus; //synchronous input; enables uploading the content of the register onto the outbus
  output reg [7:0] outbus; //output: outbus data lines; written only when load_outbus is active (high) and kept in high impedance otherwise
  output [6:0] accumulator_value; //output: the magnitude field of the register's stored number

reg [7:0] state, state_next;

always @(*) begin
   state_next = 8'd0;
   if (clear)
      state_next = 8'd0;
      else if (load_adder_result)
         state_next = adder_result;
   else if (load_sign)
      state_next = {sign , state[6:0]};
   else if (shift)
      state_next = { 1'd0, state[7:1] };
      else state_next = state;
end

always @ (*) begin
    if (load_outbus)
       outbus = state;
       else
       outbus = 8'bz;
end

 assign acumulator_value = outbus[6:0];
 assign shift_out = state[0];

 always @(posedge clk)
      state <= state_next;
endmodule




==============================================================================================================


module control_unit(
  input clk, //synchronization signal
  input reset_n, //asynchronous reset signal
  input begin_sig, //synchronous input; replaces the BEGIN signal due to begin being a reserved Verilog word
  output end_sig, //output; replaces signal END to avoid using the reserved Verilog word end
  input count_7, //synchronous input; marks the completion of the 7 iterations
  input q_0, //synchronous input; indicate the value of xi stored in Q[0]
  output [6:0] c //outputs; the control signals for the multiplier device
);

   reg [7:0] state,state_next;
   always @ (*) begin
    state_next = {state[6],state[5],state[4]& count_7, state[2] & ~q_0 |state[3] |  state[4] & ~count_7 & ~ q_0,state[2] & q_0 | state[4] &~ count_7 & q_0, state[1], begin_sig & state[0], state[0] & ~begin_sig | state[7] };
 end

 assign {c,end_sig} = state;
 always @ (posedge clk or negedge reset_n )
    if (!reset_n) state<= 8'd1;
    else state <= state_next;
 endmodule


==============================================================================================================


  input clk;
  input clear_bit_0;
  input load_inbus;
  input [7:0] inbus;
  input load_outbus;
  output reg [7:0] outbus;
  input shift;
  input shift_in;
  output content_bit_0;

reg [7:0] state,state_next;
always @(*) begin
    state_next = 8'd0;
    if (clear_bit_0) state_next = { state[7:1],1'b0};
    if (load_inbus) state_next = inbus;
    else state_next = state;
    if (shift == 1)
       state_next = {shift_in,state[7:1]};
       else state_next = state;
end

assign content_bit_0 = state[0];
always @ (posedge clk) begin
     state <= state_next;
end

 always @ (*) begin
    outbus = 8'bz;
    if (load_outbus) outbus = state;
    else outbus = 8'bz;
  end
endmodule