ADDWF(1998)

; Drive the ADDWF, etc

; ADDWF 42
; ADDWF 42,F
; ADDWF 42,W	<- Mask opcode with FF7F

rADDWF:			mov cx,cs:2[bx]		; Get the op-code

				; Now, get the register address. 7-bit

				call Get_Expr_7     ; Giz the immediate
		        jc ADDWF_Error		; Fail

    	        ; Build the op-code

				or cx,ax			; Merge op-code

				; Now, we can have a ",F" or a ",W" here

				call Skip_Spc		; Skip the spaces

				cmp al,","			; "," ?
				jne rADDWF_Plant	; No, assume we're done

				call Skip_1_Spc		; Skip ","

				; Now, we must have a "F" or "W"

    	        cmp al,icTok_LC     ; Token ?
        	    jne ADDWF_Syntax	; No, fail

            	mov al,es:1[di]     ; Get it

        	    inc di              ; Presume we can skip it
    	        inc di              ;

				; Now, this must be a "F" (t52) or a "W" (t53)

				cmp al,052h			; "F"?
				je rADDWF_Plant		; Yes, this is the default, plant it

				and cl,07Fh			; Presume it's a xxxx,W

				cmp al,053h			; "W"?
				je rADDWF_Plant		; Yes, the opcode is correct, plant it

				; Bugger, don't know.

				dec di				; Restore
				dec di				;

				; Fall into. . .

ADDWF_Syntax:	jmp rSyntax			; Vector

				; Plant CX

rADDWF_Plant:	mov ax,cx			; Get the opcode
				jmp Plant_Word		; Dump it

ADDWF_Error:	jmp rError			; Vector