dekoder416

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--(b) izgradnja dek 4/16 pomocu dek 1/2
-- warning: this file will not be saved if:
--     * following entity block contains any syntactic errors (e.g. port list isn't separated with ; character)
--     * following entity name and current file name differ (e.g. if file is named mux41 then entity must also be named mux41 and vice versa)
ENTITY dek416e IS port(
e: in std_logic;
a: in std_logic_vector(0 to 3);
y: out std_logic_vector(0 to 15) );
END dek416e;

ARCHITECTURE arch OF dek416e IS
    signal wire_00: std_logic;
    signal wire_01: std_logic;
    signal wire_02: std_logic;
    signal wire_03: std_logic;
    signal wire_04: std_logic;
    signal wire_05: std_logic;
    signal wire_06: std_logic;
    signal wire_07: std_logic;
    signal wire_08: std_logic;
    signal wire_09: std_logic;
    signal wire_10: std_logic;
    signal wire_11: std_logic;
    signal wire_12: std_logic;
    signal wire_13: std_logic;

    signal izl_00: std_logic;
    signal izl_01: std_logic;
    signal izl_02: std_logic;
    signal izl_03: std_logic;
    signal izl_04: std_logic;
    signal izl_05: std_logic;
    signal izl_06: std_logic;
    signal izl_07: std_logic;
    signal izl_08: std_logic;
    signal izl_09: std_logic;
    signal izl_10: std_logic;
    signal izl_11: std_logic;
    signal izl_12: std_logic;
    signal izl_13: std_logic;
    signal izl_14: std_logic;
    signal izl_15: std_logic;

    BEGIN
    c1: entity work.dekoder12 port map (e, a(0), wire_00, wire_01 );

    c2: entity work.dekoder12 port map (wire_00, a(1), wire_02, wire_03 );
    c3: entity work.dekoder12 port map (wire_01, a(1), wire_04, wire_05 );

    c4: entity work.dekoder12 port map (wire_02, a(2), wire_06, wire_07 );
    c5: entity work.dekoder12 port map (wire_03, a(2), wire_08, wire_09 );
    c6: entity work.dekoder12 port map (wire_04, a(2), wire_10, wire_11 );
    c7: entity work.dekoder12 port map (wire_05, a(2), wire_12, wire_13 );

    c8: entity work.dekoder12 port map (wire_06, a(3),izl_00, izl_01 );
    c9: entity work.dekoder12 port map (wire_07, a(3),izl_02, izl_03 );
    c10: entity work.dekoder12 port map (wire_08, a(3), izl_04, izl_05);
    c11: entity work.dekoder12 port map (wire_09, a(3), izl_06, izl_07);
    c12: entity work.dekoder12 port map (wire_10, a(3), izl_08, izl_09);
    c13: entity work.dekoder12 port map (wire_11, a(3), izl_10, izl_11);
    c14: entity work.dekoder12 port map (wire_12, a(3), izl_12, izl_13);
    c15: entity work.dekoder12 port map (wire_13, a(3), izl_14, izl_15);

    y <= izl_00 & izl_01 & izl_02 & izl_03 & izl_04 & izl_05 & izl_06 & izl_07 & izl_08 & izl_09 & izl_10 & izl_11 & izl_12 & izl_13 & izl_14 & izl_15;

END arch;