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vedic_div32.syr.a32edf712b961

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May 6th, 2015
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  1. Release 14.4 - xst P.49d (lin64)
  2. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
  3. -->
  4. Parameter TMPDIR set to xst/projnav.tmp
  5.  
  6.  
  7. Total REAL time to Xst completion: 0.00 secs
  8. Total CPU time to Xst completion: 0.07 secs
  9.  
  10. -->
  11. Parameter xsthdpdir set to xst
  12.  
  13.  
  14. Total REAL time to Xst completion: 0.00 secs
  15. Total CPU time to Xst completion: 0.07 secs
  16.  
  17. -->
  18. Reading design: vedic_div32.prj
  19.  
  20. TABLE OF CONTENTS
  21. 1) Synthesis Options Summary
  22. 2) HDL Compilation
  23. 3) Design Hierarchy Analysis
  24. 4) HDL Analysis
  25. 5) HDL Synthesis
  26. 5.1) HDL Synthesis Report
  27. 6) Advanced HDL Synthesis
  28. 6.1) Advanced HDL Synthesis Report
  29. 7) Low Level Synthesis
  30. 8) Partition Report
  31. 9) Final Report
  32. 9.1) Device utilization summary
  33. 9.2) Partition Resource Summary
  34. 9.3) TIMING REPORT
  35.  
  36.  
  37. =========================================================================
  38. * Synthesis Options Summary *
  39. =========================================================================
  40. ---- Source Parameters
  41. Input File Name : "vedic_div32.prj"
  42. Input Format : mixed
  43. Ignore Synthesis Constraint File : NO
  44.  
  45. ---- Target Parameters
  46. Output File Name : "vedic_div32"
  47. Output Format : NGC
  48. Target Device : xc5vlx50t-2-ff1136
  49.  
  50. ---- Source Options
  51. Top Module Name : vedic_div32
  52. Automatic FSM Extraction : YES
  53. FSM Encoding Algorithm : Auto
  54. Safe Implementation : No
  55. FSM Style : LUT
  56. RAM Extraction : Yes
  57. RAM Style : Auto
  58. ROM Extraction : Yes
  59. Mux Style : Auto
  60. Decoder Extraction : YES
  61. Priority Encoder Extraction : Yes
  62. Shift Register Extraction : YES
  63. Logical Shifter Extraction : YES
  64. XOR Collapsing : YES
  65. ROM Style : Auto
  66. Mux Extraction : Yes
  67. Resource Sharing : YES
  68. Asynchronous To Synchronous : NO
  69. Use DSP Block : Auto
  70. Automatic Register Balancing : No
  71.  
  72. ---- Target Options
  73. LUT Combining : Auto
  74. Reduce Control Sets : Auto
  75. Add IO Buffers : YES
  76. Global Maximum Fanout : 100000
  77. Add Generic Clock Buffer(BUFG) : 32
  78. Register Duplication : YES
  79. Slice Packing : YES
  80. Optimize Instantiated Primitives : NO
  81. Use Clock Enable : Auto
  82. Use Synchronous Set : Auto
  83. Use Synchronous Reset : Auto
  84. Pack IO Registers into IOBs : Auto
  85. Equivalent register Removal : YES
  86.  
  87. ---- General Options
  88. Optimization Goal : Speed
  89. Optimization Effort : 2
  90. Power Reduction : NO
  91. Keep Hierarchy : No
  92. Netlist Hierarchy : As_Optimized
  93. RTL Output : Yes
  94. Global Optimization : AllClockNets
  95. Read Cores : YES
  96. Write Timing Constraints : NO
  97. Cross Clock Analysis : NO
  98. Hierarchy Separator : /
  99. Bus Delimiter : <>
  100. Case Specifier : Maintain
  101. Slice Utilization Ratio : 100
  102. BRAM Utilization Ratio : 100
  103. DSP48 Utilization Ratio : 100
  104. Verilog 2001 : YES
  105. Auto BRAM Packing : NO
  106. Slice Utilization Ratio Delta : 5
  107.  
  108. =========================================================================
  109.  
  110.  
  111. =========================================================================
  112. * HDL Compilation *
  113. =========================================================================
  114. Compiling vhdl file "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" in Library work.
  115. Entity <vedic_div32> compiled.
  116. Entity <vedic_div32> (Architecture <rtl>) compiled.
  117.  
  118. =========================================================================
  119. * Design Hierarchy Analysis *
  120. =========================================================================
  121. Analyzing hierarchy for entity <vedic_div32> in library <work> (architecture <rtl>).
  122.  
  123.  
  124. =========================================================================
  125. * HDL Analysis *
  126. =========================================================================
  127. Analyzing Entity <vedic_div32> in library <work> (Architecture <rtl>).
  128. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 31-bit wide.
  129. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 1-bit wide.
  130. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 30-bit wide.
  131. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 2-bit wide.
  132. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 29-bit wide.
  133. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 3-bit wide.
  134. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 28-bit wide.
  135. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 4-bit wide.
  136. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 27-bit wide.
  137. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 5-bit wide.
  138. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 26-bit wide.
  139. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 6-bit wide.
  140. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 25-bit wide.
  141. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 7-bit wide.
  142. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 24-bit wide.
  143. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 8-bit wide.
  144. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 23-bit wide.
  145. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 9-bit wide.
  146. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 22-bit wide.
  147. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 10-bit wide.
  148. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 21-bit wide.
  149. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 11-bit wide.
  150. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 20-bit wide.
  151. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 12-bit wide.
  152. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 19-bit wide.
  153. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 13-bit wide.
  154. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 18-bit wide.
  155. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 14-bit wide.
  156. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 17-bit wide.
  157. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 15-bit wide.
  158. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 16-bit wide.
  159. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 16-bit wide.
  160. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 15-bit wide.
  161. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 17-bit wide.
  162. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 14-bit wide.
  163. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 18-bit wide.
  164. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 13-bit wide.
  165. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 19-bit wide.
  166. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 12-bit wide.
  167. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 20-bit wide.
  168. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 11-bit wide.
  169. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 21-bit wide.
  170. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 10-bit wide.
  171. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 22-bit wide.
  172. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 9-bit wide.
  173. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 23-bit wide.
  174. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 8-bit wide.
  175. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 24-bit wide.
  176. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 7-bit wide.
  177. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 25-bit wide.
  178. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 6-bit wide.
  179. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 26-bit wide.
  180. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 5-bit wide.
  181. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 27-bit wide.
  182. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 4-bit wide.
  183. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 28-bit wide.
  184. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 3-bit wide.
  185. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 29-bit wide.
  186. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 2-bit wide.
  187. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 30-bit wide.
  188. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 64: Width mismatch. <init_reg.quo_reg> has a width of 32 bits but assigned expression is 1-bit wide.
  189. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 68: Width mismatch. <init_reg.re_reg> has a width of 36 bits but assigned expression is 31-bit wide.
  190. WARNING:Xst:819 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 56: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
  191. <dividend>
  192. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 103: Width mismatch. <v_reg.quo_reg> has a width of 32 bits but assigned expression is 31-bit wide.
  193. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 106: Width mismatch. <quo_tmp> has a width of 32 bits but assigned expression is 63-bit wide.
  194. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 107: Width mismatch. <re_tmp> has a width of 32 bits but assigned expression is 63-bit wide.
  195. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 115: Width mismatch. <v_reg.quo_reg> has a width of 32 bits but assigned expression is 63-bit wide.
  196. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 117: Width mismatch. <v_reg.quo_reg> has a width of 32 bits but assigned expression is 63-bit wide.
  197. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 121: Width mismatch. <v_reg.re_reg> has a width of 36 bits but assigned expression is 63-bit wide.
  198. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 123: Width mismatch. <v_reg.re_reg> has a width of 36 bits but assigned expression is 63-bit wide.
  199. WARNING:Xst:1610 - "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd" line 125: Width mismatch. <v_reg.re_reg> has a width of 36 bits but assigned expression is 63-bit wide.
  200. Entity <vedic_div32> analyzed. Unit <vedic_div32> generated.
  201.  
  202.  
  203. =========================================================================
  204. * HDL Synthesis *
  205. =========================================================================
  206.  
  207. Performing bidirectional port resolution...
  208.  
  209. Synthesizing Unit <vedic_div32>.
  210. Related source file is "/home/calros/IS/Divider/vedicDivider/vedic_div32.vhd".
  211. WARNING:Xst:653 - Signal <init_reg.quo> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
  212. Found finite state machine <FSM_0> for signal <state>.
  213. -----------------------------------------------------------------------
  214. | States | 4 |
  215. | Transitions | 9 |
  216. | Inputs | 3 |
  217. | Outputs | 3 |
  218. | Clock | mclk1 (rising_edge) |
  219. | Reset | state$and0000 (positive) |
  220. | Reset type | synchronous |
  221. | Reset State | fin_state |
  222. | Power Up State | init_state |
  223. | Encoding | automatic |
  224. | Implementation | LUT |
  225. -----------------------------------------------------------------------
  226. WARNING:Xst:737 - Found 5-bit latch for signal <shift_val>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  227. WARNING:Xst:737 - Found 36-bit latch for signal <init_reg.re_reg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  228. WARNING:Xst:737 - Found 31-bit latch for signal <b_n>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  229. WARNING:Xst:737 - Found 32-bit latch for signal <init_reg.quo_reg>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
  230. Found 32-bit register for signal <quo>.
  231. Found 32-bit register for signal <re>.
  232. Found 31-bit shifter logical left for signal <b_n$shift0000> created at line 62.
  233. Found 5-bit register for signal <i>.
  234. Found 5-bit subtractor for signal <i$addsub0000> created at line 133.
  235. Found 17-bit shifter logical left for signal <init_reg.re_reg$shift0047> created at line 68.
  236. Found 18-bit shifter logical left for signal <init_reg.re_reg$shift0048> created at line 68.
  237. Found 19-bit shifter logical left for signal <init_reg.re_reg$shift0049> created at line 68.
  238. Found 20-bit shifter logical left for signal <init_reg.re_reg$shift0050> created at line 68.
  239. Found 21-bit shifter logical left for signal <init_reg.re_reg$shift0051> created at line 68.
  240. Found 22-bit shifter logical left for signal <init_reg.re_reg$shift0052> created at line 68.
  241. Found 23-bit shifter logical left for signal <init_reg.re_reg$shift0053> created at line 68.
  242. Found 24-bit shifter logical left for signal <init_reg.re_reg$shift0054> created at line 68.
  243. Found 25-bit shifter logical left for signal <init_reg.re_reg$shift0055> created at line 68.
  244. Found 26-bit shifter logical left for signal <init_reg.re_reg$shift0056> created at line 68.
  245. Found 27-bit shifter logical left for signal <init_reg.re_reg$shift0057> created at line 68.
  246. Found 28-bit shifter logical left for signal <init_reg.re_reg$shift0058> created at line 68.
  247. Found 29-bit shifter logical left for signal <init_reg.re_reg$shift0059> created at line 68.
  248. Found 30-bit shifter logical left for signal <init_reg.re_reg$shift0060> created at line 68.
  249. Found 31-bit shifter logical left for signal <init_reg.re_reg$shift0061> created at line 68.
  250. Found 16-bit shifter logical left for signal <init_reg.re_reg$shift0062> created at line 68.
  251. Found 15-bit shifter logical left for signal <init_reg.re_reg$shift0063> created at line 68.
  252. Found 14-bit shifter logical left for signal <init_reg.re_reg$shift0064> created at line 68.
  253. Found 13-bit shifter logical left for signal <init_reg.re_reg$shift0065> created at line 68.
  254. Found 12-bit shifter logical left for signal <init_reg.re_reg$shift0066> created at line 68.
  255. Found 11-bit shifter logical left for signal <init_reg.re_reg$shift0067> created at line 68.
  256. Found 10-bit shifter logical left for signal <init_reg.re_reg$shift0068> created at line 68.
  257. Found 9-bit shifter logical left for signal <init_reg.re_reg$shift0069> created at line 68.
  258. Found 8-bit shifter logical left for signal <init_reg.re_reg$shift0070> created at line 68.
  259. Found 7-bit shifter logical left for signal <init_reg.re_reg$shift0071> created at line 68.
  260. Found 6-bit shifter logical left for signal <init_reg.re_reg$shift0072> created at line 68.
  261. Found 5-bit shifter logical left for signal <init_reg.re_reg$shift0073> created at line 68.
  262. Found 4-bit shifter logical left for signal <init_reg.re_reg$shift0074> created at line 68.
  263. Found 3-bit shifter logical left for signal <init_reg.re_reg$shift0075> created at line 68.
  264. Found 2-bit shifter logical left for signal <init_reg.re_reg$shift0076> created at line 68.
  265. Found 1-bit shifter logical left for signal <init_reg.re_reg$shift0077> created at line 68.
  266. Found 32-bit register for signal <k_reg.quo>.
  267. Found 36-bit register for signal <k_reg.re_reg>.
  268. Found 1-bit register for signal <k_reg.re_sign>.
  269. Found 32-bit register for signal <main_reg.quo>.
  270. Found 32-bit addsub for signal <main_reg.quo$mux0000>.
  271. Found 32-bit register for signal <main_reg.quo_reg>.
  272. Found 63-bit comparator greater for signal <main_reg.quo_reg$cmp_gt0000> created at line 112.
  273. Found 32x31-bit multiplier for signal <main_reg.quo_reg$mult0002> created at line 106.
  274. Found 32-bit subtractor for signal <main_reg.quo_reg$mux0000>.
  275. Found 1-bit register for signal <main_reg.quo_sign>.
  276. Found 36-bit register for signal <main_reg.re_reg>.
  277. Found 63-bit comparator greater for signal <main_reg.re_reg$cmp_gt0000> created at line 121.
  278. Found 1-bit xor2 for signal <main_reg.re_reg$cmp_ne0000> created at line 120.
  279. Found 36-bit addsub for signal <main_reg.re_reg$mux0000>.
  280. Found 1-bit register for signal <main_reg.re_sign>.
  281. Found 32-bit adder for signal <quo$addsub0000> created at line 185.
  282. Found 32x31-bit multiplier for signal <re_tmp$mult0000> created at line 107.
  283. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<30:1>> created at line 107.
  284. Found 30-bit 31-to-1 multiplexer for signal <re_tmp$mux0000<0>> created at line 107.
  285. Found 63-bit shifter logical left for signal <re_tmp$shift0000> created at line 107.
  286. Found 32-bit shifter logical right for signal <tmp_quo_reg$shift0000> created at line 91.
  287. Found 36-bit subtractor for signal <v_re$addsub0000> created at line 184.
  288. Found 36-bit subtractor for signal <v_re$addsub0001> created at line 184.
  289. Found 36-bit subtractor for signal <v_re$addsub0002> created at line 184.
  290. Found 36-bit subtractor for signal <v_re$addsub0003> created at line 184.
  291. Found 36-bit subtractor for signal <v_re$addsub0004> created at line 184.
  292. Found 36-bit adder for signal <v_re$addsub0005> created at line 177.
  293. Found 36-bit subtractor for signal <v_re$addsub0006> created at line 184.
  294. Found 36-bit adder for signal <v_re$addsub0007> created at line 177.
  295. Found 36-bit subtractor for signal <v_re$addsub0008> created at line 184.
  296. Found 36-bit adder for signal <v_re$addsub0009> created at line 177.
  297. Found 36-bit subtractor for signal <v_re$addsub0010> created at line 184.
  298. Found 36-bit adder for signal <v_re$addsub0011> created at line 177.
  299. Found 36-bit subtractor for signal <v_re$addsub0012> created at line 184.
  300. Found 36-bit adder for signal <v_re$addsub0013> created at line 177.
  301. Found 36-bit adder for signal <v_re$addsub0014> created at line 177.
  302. Found 36-bit adder for signal <v_re$addsub0015> created at line 177.
  303. Found 36-bit adder for signal <v_re$addsub0016> created at line 177.
  304. Found 36-bit adder for signal <v_re$addsub0017> created at line 177.
  305. Found 36-bit adder for signal <v_re$addsub0018> created at line 170.
  306. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0000> created at line 183.
  307. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0001> created at line 183.
  308. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0002> created at line 183.
  309. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0003> created at line 183.
  310. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0004> created at line 183.
  311. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0005> created at line 183.
  312. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0006> created at line 183.
  313. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0007> created at line 183.
  314. Found 36-bit comparator greatequal for signal <v_re$cmp_ge0008> created at line 183.
  315. Found 36-bit comparator less for signal <v_re$cmp_lt0000> created at line 176.
  316. Found 36-bit comparator less for signal <v_re$cmp_lt0001> created at line 176.
  317. Found 36-bit comparator less for signal <v_re$cmp_lt0002> created at line 176.
  318. Found 36-bit comparator less for signal <v_re$cmp_lt0003> created at line 176.
  319. Found 36-bit comparator less for signal <v_re$cmp_lt0004> created at line 176.
  320. Found 36-bit comparator less for signal <v_re$cmp_lt0005> created at line 176.
  321. Found 36-bit comparator less for signal <v_re$cmp_lt0006> created at line 176.
  322. Found 36-bit comparator less for signal <v_re$cmp_lt0007> created at line 176.
  323. Found 36-bit comparator less for signal <v_re$cmp_lt0008> created at line 176.
  324. Found 36-bit shifter arithmetic right for signal <v_re$shift0000> created at line 173.
  325. Found 32-bit shifter logical left for signal <v_reg.quo$shift0000> created at line 95.
  326. Found 32-bit adder for signal <v_reg0.quo$add0000> created at line 185.
  327. Found 32-bit adder for signal <v_reg0.quo$add0001> created at line 185.
  328. Found 32-bit adder for signal <v_reg0.quo$add0002> created at line 185.
  329. Found 32-bit adder for signal <v_reg0.quo$add0003> created at line 185.
  330. Found 32-bit adder for signal <v_reg0.quo$add0004> created at line 185.
  331. Found 32-bit adder for signal <v_reg0.quo$add0005> created at line 185.
  332. Found 32-bit adder for signal <v_reg0.quo$add0006> created at line 185.
  333. Found 32-bit adder for signal <v_reg0.quo$add0007> created at line 185.
  334. Found 32-bit subtractor for signal <v_reg0.quo$sub0000> created at line 178.
  335. Found 32-bit subtractor for signal <v_reg0.quo$sub0001> created at line 178.
  336. Found 32-bit subtractor for signal <v_reg0.quo$sub0002> created at line 178.
  337. Found 32-bit subtractor for signal <v_reg0.quo$sub0003> created at line 178.
  338. Found 32-bit subtractor for signal <v_reg0.quo$sub0004> created at line 178.
  339. Found 32-bit subtractor for signal <v_reg0.quo$sub0005> created at line 178.
  340. Found 32-bit subtractor for signal <v_reg0.quo$sub0006> created at line 178.
  341. Found 32-bit subtractor for signal <v_reg0.quo$sub0007> created at line 178.
  342. Found 32-bit subtractor for signal <v_reg0.quo$sub0008> created at line 178.
  343. Summary:
  344. inferred 1 Finite State Machine(s).
  345. inferred 240 D-type flip-flop(s).
  346. inferred 41 Adder/Subtractor(s).
  347. inferred 2 Multiplier(s).
  348. inferred 20 Comparator(s).
  349. inferred 31 Multiplexer(s).
  350. inferred 36 Combinational logic shifter(s).
  351. Unit <vedic_div32> synthesized.
  352.  
  353. INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
  354.  
  355. =========================================================================
  356. HDL Synthesis Report
  357.  
  358. Macro Statistics
  359. # Multipliers : 2
  360. 32x31-bit multiplier : 2
  361. # Adders/Subtractors : 41
  362. 32-bit adder : 9
  363. 32-bit addsub : 1
  364. 32-bit subtractor : 10
  365. 36-bit adder : 10
  366. 36-bit addsub : 1
  367. 36-bit subtractor : 9
  368. 5-bit subtractor : 1
  369. # Registers : 11
  370. 1-bit register : 3
  371. 32-bit register : 5
  372. 36-bit register : 2
  373. 5-bit register : 1
  374. # Latches : 4
  375. 31-bit latch : 1
  376. 32-bit latch : 1
  377. 36-bit latch : 1
  378. 5-bit latch : 1
  379. # Comparators : 20
  380. 36-bit comparator greatequal : 9
  381. 36-bit comparator less : 9
  382. 63-bit comparator greater : 2
  383. # Multiplexers : 31
  384. 1-bit 31-to-1 multiplexer : 1
  385. 1-bit 32-to-1 multiplexer : 30
  386. # Logic shifters : 36
  387. 1-bit shifter logical left : 1
  388. 10-bit shifter logical left : 1
  389. 11-bit shifter logical left : 1
  390. 12-bit shifter logical left : 1
  391. 13-bit shifter logical left : 1
  392. 14-bit shifter logical left : 1
  393. 15-bit shifter logical left : 1
  394. 16-bit shifter logical left : 1
  395. 17-bit shifter logical left : 1
  396. 18-bit shifter logical left : 1
  397. 19-bit shifter logical left : 1
  398. 2-bit shifter logical left : 1
  399. 20-bit shifter logical left : 1
  400. 21-bit shifter logical left : 1
  401. 22-bit shifter logical left : 1
  402. 23-bit shifter logical left : 1
  403. 24-bit shifter logical left : 1
  404. 25-bit shifter logical left : 1
  405. 26-bit shifter logical left : 1
  406. 27-bit shifter logical left : 1
  407. 28-bit shifter logical left : 1
  408. 29-bit shifter logical left : 1
  409. 3-bit shifter logical left : 1
  410. 30-bit shifter logical left : 1
  411. 31-bit shifter logical left : 2
  412. 32-bit shifter logical left : 1
  413. 32-bit shifter logical right : 1
  414. 36-bit shifter arithmetic right : 1
  415. 4-bit shifter logical left : 1
  416. 5-bit shifter logical left : 1
  417. 6-bit shifter logical left : 1
  418. 63-bit shifter logical left : 1
  419. 7-bit shifter logical left : 1
  420. 8-bit shifter logical left : 1
  421. 9-bit shifter logical left : 1
  422. # Xors : 1
  423. 1-bit xor2 : 1
  424.  
  425. =========================================================================
  426.  
  427. =========================================================================
  428. * Advanced HDL Synthesis *
  429. =========================================================================
  430.  
  431. Analyzing FSM <FSM_0> for best encoding.
  432. Optimizing FSM <state/FSM> on signal <state[1:2]> with sequential encoding.
  433. ------------------------
  434. State | Encoding
  435. ------------------------
  436. init_state | 00
  437. main_state | 10
  438. wait_state | 11
  439. fin_state | 01
  440. ------------------------
  441. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <31>. This FF/Latch will be trimmed during the optimization process.
  442. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <32>. This FF/Latch will be trimmed during the optimization process.
  443. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <33>. This FF/Latch will be trimmed during the optimization process.
  444. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <34>. This FF/Latch will be trimmed during the optimization process.
  445. WARNING:Xst:1293 - FF/Latch <0> has a constant value of 0 in block <35>. This FF/Latch will be trimmed during the optimization process.
  446. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <main_reg.quo_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  447. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <main_reg.re_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  448. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <k_reg.re_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  449.  
  450. Synthesizing (advanced) Unit <vedic_div32>.
  451. The following registers are absorbed into accumulator <main_reg.quo>: 1 register on signal <main_reg.quo>.
  452. Unit <vedic_div32> synthesized (advanced).
  453.  
  454. =========================================================================
  455. Advanced HDL Synthesis Report
  456.  
  457. Macro Statistics
  458. # FSMs : 1
  459. # Multipliers : 2
  460. 32x31-bit multiplier : 2
  461. # Adders/Subtractors : 40
  462. 32-bit adder : 9
  463. 32-bit subtractor : 11
  464. 36-bit adder : 10
  465. 36-bit addsub : 1
  466. 36-bit subtractor : 8
  467. 5-bit subtractor : 1
  468. # Accumulators : 1
  469. 32-bit updown loadable accumulator : 1
  470. # Registers : 208
  471. Flip-Flops : 208
  472. # Latches : 4
  473. 31-bit latch : 1
  474. 32-bit latch : 1
  475. 36-bit latch : 1
  476. 5-bit latch : 1
  477. # Comparators : 20
  478. 36-bit comparator greatequal : 9
  479. 36-bit comparator less : 9
  480. 63-bit comparator greater : 2
  481. # Multiplexers : 31
  482. 1-bit 31-to-1 multiplexer : 1
  483. 1-bit 32-to-1 multiplexer : 30
  484. # Logic shifters : 36
  485. 1-bit shifter logical left : 1
  486. 10-bit shifter logical left : 1
  487. 11-bit shifter logical left : 1
  488. 12-bit shifter logical left : 1
  489. 13-bit shifter logical left : 1
  490. 14-bit shifter logical left : 1
  491. 15-bit shifter logical left : 1
  492. 16-bit shifter logical left : 1
  493. 17-bit shifter logical left : 1
  494. 18-bit shifter logical left : 1
  495. 19-bit shifter logical left : 1
  496. 2-bit shifter logical left : 1
  497. 20-bit shifter logical left : 1
  498. 21-bit shifter logical left : 1
  499. 22-bit shifter logical left : 1
  500. 23-bit shifter logical left : 1
  501. 24-bit shifter logical left : 1
  502. 25-bit shifter logical left : 1
  503. 26-bit shifter logical left : 1
  504. 27-bit shifter logical left : 1
  505. 28-bit shifter logical left : 1
  506. 29-bit shifter logical left : 1
  507. 3-bit shifter logical left : 1
  508. 30-bit shifter logical left : 1
  509. 31-bit shifter logical left : 2
  510. 32-bit shifter logical left : 1
  511. 32-bit shifter logical right : 1
  512. 36-bit shifter arithmetic right : 1
  513. 4-bit shifter logical left : 1
  514. 5-bit shifter logical left : 1
  515. 6-bit shifter logical left : 1
  516. 63-bit shifter logical left : 1
  517. 7-bit shifter logical left : 1
  518. 8-bit shifter logical left : 1
  519. 9-bit shifter logical left : 1
  520. # Xors : 1
  521. 1-bit xor2 : 1
  522.  
  523. =========================================================================
  524.  
  525. =========================================================================
  526. * Low Level Synthesis *
  527. =========================================================================
  528. WARNING:Xst:1293 - FF/Latch <main_reg.quo_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  529. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <main_reg.re_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  530. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <k_reg.re_sign> has a constant value of 0 in block <vedic_div32>. This FF/Latch will be trimmed during the optimization process.
  531. INFO:Xst:2261 - The FF/Latch <35> in Unit <LPM_LATCH_7> is equivalent to the following 4 FFs/Latches, which will be removed : <34> <33> <32> <31>
  532. WARNING:Xst:1293 - FF/Latch <35> has a constant value of 0 in block <LPM_LATCH_7>. This FF/Latch will be trimmed during the optimization process.
  533.  
  534. Optimizing unit <vedic_div32> ...
  535.  
  536. Mapping all equations...
  537. Building and optimizing final netlist ...
  538. Found area constraint ratio of 100 (+ 5) on block vedic_div32, actual ratio is 22.
  539. FlipFlop main_reg.re_reg_35 has been replicated 1 time(s)
  540.  
  541. Final Macro Processing ...
  542.  
  543. =========================================================================
  544. Final Register Report
  545.  
  546. Macro Statistics
  547. # Registers : 240
  548. Flip-Flops : 240
  549.  
  550. =========================================================================
  551.  
  552. =========================================================================
  553. * Partition Report *
  554. =========================================================================
  555.  
  556. Partition Implementation Status
  557. -------------------------------
  558.  
  559. No Partitions were found in this design.
  560.  
  561. -------------------------------
  562.  
  563. =========================================================================
  564. * Final Report *
  565. =========================================================================
  566. Final Results
  567. RTL Top Level Output File Name : vedic_div32.ngr
  568. Top Level Output File Name : vedic_div32
  569. Output Format : NGC
  570. Optimization Goal : Speed
  571. Keep Hierarchy : No
  572.  
  573. Design Statistics
  574. # IOs : 130
  575.  
  576. Cell Usage :
  577. # BELS : 7920
  578. # GND : 1
  579. # INV : 4
  580. # LUT2 : 144
  581. # LUT3 : 541
  582. # LUT4 : 933
  583. # LUT5 : 1158
  584. # LUT6 : 2224
  585. # MUXCY : 1463
  586. # MUXF7 : 131
  587. # VCC : 1
  588. # XORCY : 1320
  589. # FlipFlops/Latches : 339
  590. # FD : 165
  591. # FDE : 68
  592. # FDR : 1
  593. # FDS : 6
  594. # LDCP : 99
  595. # Clock Buffers : 2
  596. # BUFG : 1
  597. # BUFGP : 1
  598. # IO Buffers : 129
  599. # IBUF : 65
  600. # OBUF : 64
  601. # DSPs : 8
  602. # DSP48E : 8
  603. =========================================================================
  604.  
  605. Device utilization summary:
  606. ---------------------------
  607.  
  608. Selected Device : 5vlx50tff1136-2
  609.  
  610.  
  611. Slice Logic Utilization:
  612. Number of Slice Registers: 339 out of 28800 1%
  613. Number of Slice LUTs: 5004 out of 28800 17%
  614. Number used as Logic: 5004 out of 28800 17%
  615.  
  616. Slice Logic Distribution:
  617. Number of LUT Flip Flop pairs used: 5131
  618. Number with an unused Flip Flop: 4792 out of 5131 93%
  619. Number with an unused LUT: 127 out of 5131 2%
  620. Number of fully used LUT-FF pairs: 212 out of 5131 4%
  621. Number of unique control sets: 103
  622.  
  623. IO Utilization:
  624. Number of IOs: 130
  625. Number of bonded IOBs: 130 out of 480 27%
  626.  
  627. Specific Feature Utilization:
  628. Number of BUFG/BUFGCTRLs: 2 out of 32 6%
  629. Number of DSP48Es: 8 out of 48 16%
  630.  
  631. ---------------------------
  632. Partition Resource Summary:
  633. ---------------------------
  634.  
  635. No Partitions were found in this design.
  636.  
  637. ---------------------------
  638.  
  639.  
  640. =========================================================================
  641. TIMING REPORT
  642.  
  643. NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
  644. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
  645. GENERATED AFTER PLACE-and-ROUTE.
  646.  
  647. Clock Information:
  648. ------------------
  649. -----------------------------------+------------------------+-------+
  650. Clock Signal | Clock buffer(FF name) | Load |
  651. -----------------------------------+------------------------+-------+
  652. mclk1 | BUFGP | 240 |
  653. divisor<0> | IBUF+BUFG | 99 |
  654. -----------------------------------+------------------------+-------+
  655.  
  656. Asynchronous Control Signals Information:
  657. ----------------------------------------
  658. -------------------------------------------------------------+--------------------------+-------+
  659. Control Signal | Buffer(FF name) | Load |
  660. -------------------------------------------------------------+--------------------------+-------+
  661. N0(XST_GND:G) | NONE(init_reg.quo_reg_31)| 1 |
  662. b_n_0__and0000(b_n_0__and00001:O) | NONE(b_n_0) | 1 |
  663. b_n_0__and0001(b_n_0__and00011:O) | NONE(b_n_0) | 1 |
  664. b_n_10__and0000(b_n_10__and00001:O) | NONE(b_n_10) | 1 |
  665. b_n_10__and0001(b_n_10__and00011:O) | NONE(b_n_10) | 1 |
  666. b_n_11__and0000(b_n_11__and00001:O) | NONE(b_n_11) | 1 |
  667. b_n_11__and0001(b_n_11__and00011:O) | NONE(b_n_11) | 1 |
  668. b_n_12__and0000(b_n_12__and00001:O) | NONE(b_n_12) | 1 |
  669. b_n_12__and0001(b_n_12__and00011:O) | NONE(b_n_12) | 1 |
  670. b_n_13__and0000(b_n_13__and00001:O) | NONE(b_n_13) | 1 |
  671. b_n_13__and0001(b_n_13__and00011:O) | NONE(b_n_13) | 1 |
  672. b_n_14__and0000(b_n_14__and00001:O) | NONE(b_n_14) | 1 |
  673. b_n_14__and0001(b_n_14__and00011:O) | NONE(b_n_14) | 1 |
  674. b_n_15__and0000(b_n_15__and00001:O) | NONE(b_n_15) | 1 |
  675. b_n_15__and0001(b_n_15__and00011:O) | NONE(b_n_15) | 1 |
  676. b_n_16__and0000(b_n_16__and00001:O) | NONE(b_n_16) | 1 |
  677. b_n_16__and0001(b_n_16__and00011:O) | NONE(b_n_16) | 1 |
  678. b_n_17__and0000(b_n_17__and00001:O) | NONE(b_n_17) | 1 |
  679. b_n_17__and0001(b_n_17__and00011:O) | NONE(b_n_17) | 1 |
  680. b_n_18__and0000(b_n_18__and00001:O) | NONE(b_n_18) | 1 |
  681. b_n_18__and0001(b_n_18__and00011:O) | NONE(b_n_18) | 1 |
  682. b_n_19__and0000(b_n_19__and00001:O) | NONE(b_n_19) | 1 |
  683. b_n_19__and0001(b_n_19__and00011:O) | NONE(b_n_19) | 1 |
  684. b_n_1__and0000(b_n_1__and00001:O) | NONE(b_n_1) | 1 |
  685. b_n_1__and0001(b_n_1__and00011:O) | NONE(b_n_1) | 1 |
  686. b_n_20__and0000(b_n_20__and00001:O) | NONE(b_n_20) | 1 |
  687. b_n_20__and0001(b_n_20__and00011:O) | NONE(b_n_20) | 1 |
  688. b_n_21__and0000(b_n_21__and00001:O) | NONE(b_n_21) | 1 |
  689. b_n_21__and0001(b_n_21__and00011:O) | NONE(b_n_21) | 1 |
  690. b_n_22__and0000(b_n_22__and00001:O) | NONE(b_n_22) | 1 |
  691. b_n_22__and0001(b_n_22__and00011:O) | NONE(b_n_22) | 1 |
  692. b_n_23__and0000(b_n_23__and00001:O) | NONE(b_n_23) | 1 |
  693. b_n_23__and0001(b_n_23__and00011:O) | NONE(b_n_23) | 1 |
  694. b_n_24__and0000(b_n_24__and00001:O) | NONE(b_n_24) | 1 |
  695. b_n_24__and0001(b_n_24__and00011:O) | NONE(b_n_24) | 1 |
  696. b_n_25__and0000(b_n_25__and00001:O) | NONE(b_n_25) | 1 |
  697. b_n_25__and0001(b_n_25__and00011:O) | NONE(b_n_25) | 1 |
  698. b_n_26__and0000(b_n_26__and00001:O) | NONE(b_n_26) | 1 |
  699. b_n_26__and0001(b_n_26__and00011:O) | NONE(b_n_26) | 1 |
  700. b_n_27__and0000(b_n_27__and00001:O) | NONE(b_n_27) | 1 |
  701. b_n_27__and0001(b_n_27__and00011:O) | NONE(b_n_27) | 1 |
  702. b_n_28__and0000(b_n_28__and00001:O) | NONE(b_n_28) | 1 |
  703. b_n_28__and0001(b_n_28__and00011:O) | NONE(b_n_28) | 1 |
  704. b_n_29__and0000(b_n_29__and00001:O) | NONE(b_n_29) | 1 |
  705. b_n_29__and0001(b_n_29__and00011:O) | NONE(b_n_29) | 1 |
  706. b_n_2__and0000(b_n_2__and00001:O) | NONE(b_n_2) | 1 |
  707. b_n_2__and0001(b_n_2__and00011:O) | NONE(b_n_2) | 1 |
  708. b_n_30__and0000(b_n_30__and00001:O) | NONE(b_n_30) | 1 |
  709. b_n_30__and0001(b_n_30__and00011:O) | NONE(b_n_30) | 1 |
  710. b_n_3__and0000(b_n_3__and00001:O) | NONE(b_n_3) | 1 |
  711. b_n_3__and0001(b_n_3__and00011:O) | NONE(b_n_3) | 1 |
  712. b_n_4__and0000(b_n_4__and00001:O) | NONE(b_n_4) | 1 |
  713. b_n_4__and0001(b_n_4__and00011:O) | NONE(b_n_4) | 1 |
  714. b_n_5__and0000(b_n_5__and00001:O) | NONE(b_n_5) | 1 |
  715. b_n_5__and0001(b_n_5__and00011:O) | NONE(b_n_5) | 1 |
  716. b_n_6__and0000(b_n_6__and00001:O) | NONE(b_n_6) | 1 |
  717. b_n_6__and0001(b_n_6__and00011:O) | NONE(b_n_6) | 1 |
  718. b_n_7__and0000(b_n_7__and00001:O) | NONE(b_n_7) | 1 |
  719. b_n_7__and0001(b_n_7__and00011:O) | NONE(b_n_7) | 1 |
  720. b_n_8__and0000(b_n_8__and00001:O) | NONE(b_n_8) | 1 |
  721. b_n_8__and0001(b_n_8__and00011:O) | NONE(b_n_8) | 1 |
  722. b_n_9__and0000(b_n_9__and00001:O) | NONE(b_n_9) | 1 |
  723. b_n_9__and0001(b_n_9__and00011:O) | NONE(b_n_9) | 1 |
  724. init_reg.quo_reg_0__and0000(init_reg.quo_reg_0__and00001:O) | NONE(init_reg.quo_reg_0) | 1 |
  725. init_reg.quo_reg_0__and0001(init_reg.quo_reg_0__and00011:O) | NONE(init_reg.quo_reg_0) | 1 |
  726. init_reg.quo_reg_10__and0000(init_reg.quo_reg_10__and00001:O)| NONE(init_reg.quo_reg_10)| 1 |
  727. init_reg.quo_reg_10__and0001(init_reg.quo_reg_10__and00011:O)| NONE(init_reg.quo_reg_10)| 1 |
  728. init_reg.quo_reg_11__and0000(init_reg.quo_reg_11__and00001:O)| NONE(init_reg.quo_reg_11)| 1 |
  729. init_reg.quo_reg_11__and0001(init_reg.quo_reg_11__and00011:O)| NONE(init_reg.quo_reg_11)| 1 |
  730. init_reg.quo_reg_12__and0000(init_reg.quo_reg_12__and00001:O)| NONE(init_reg.quo_reg_12)| 1 |
  731. init_reg.quo_reg_12__and0001(init_reg.quo_reg_12__and00011:O)| NONE(init_reg.quo_reg_12)| 1 |
  732. init_reg.quo_reg_13__and0000(init_reg.quo_reg_13__and00001:O)| NONE(init_reg.quo_reg_13)| 1 |
  733. init_reg.quo_reg_13__and0001(init_reg.quo_reg_13__and00011:O)| NONE(init_reg.quo_reg_13)| 1 |
  734. init_reg.quo_reg_14__and0000(init_reg.quo_reg_14__and00001:O)| NONE(init_reg.quo_reg_14)| 1 |
  735. init_reg.quo_reg_14__and0001(init_reg.quo_reg_14__and00011:O)| NONE(init_reg.quo_reg_14)| 1 |
  736. init_reg.quo_reg_15__and0000(init_reg.quo_reg_15__and00001:O)| NONE(init_reg.quo_reg_15)| 1 |
  737. init_reg.quo_reg_15__and0001(init_reg.quo_reg_15__and00011:O)| NONE(init_reg.quo_reg_15)| 1 |
  738. init_reg.quo_reg_16__and0000(init_reg.quo_reg_16__and00001:O)| NONE(init_reg.quo_reg_16)| 1 |
  739. init_reg.quo_reg_16__and0001(init_reg.quo_reg_16__and00011:O)| NONE(init_reg.quo_reg_16)| 1 |
  740. init_reg.quo_reg_17__and0000(init_reg.quo_reg_17__and00001:O)| NONE(init_reg.quo_reg_17)| 1 |
  741. init_reg.quo_reg_17__and0001(init_reg.quo_reg_17__and00011:O)| NONE(init_reg.quo_reg_17)| 1 |
  742. init_reg.quo_reg_18__and0000(init_reg.quo_reg_18__and00001:O)| NONE(init_reg.quo_reg_18)| 1 |
  743. init_reg.quo_reg_18__and0001(init_reg.quo_reg_18__and00011:O)| NONE(init_reg.quo_reg_18)| 1 |
  744. init_reg.quo_reg_19__and0000(init_reg.quo_reg_19__and00001:O)| NONE(init_reg.quo_reg_19)| 1 |
  745. init_reg.quo_reg_19__and0001(init_reg.quo_reg_19__and00011:O)| NONE(init_reg.quo_reg_19)| 1 |
  746. init_reg.quo_reg_1__and0000(init_reg.quo_reg_1__and00001:O) | NONE(init_reg.quo_reg_1) | 1 |
  747. init_reg.quo_reg_1__and0001(init_reg.quo_reg_1__and00011:O) | NONE(init_reg.quo_reg_1) | 1 |
  748. init_reg.quo_reg_20__and0000(init_reg.quo_reg_20__and00001:O)| NONE(init_reg.quo_reg_20)| 1 |
  749. init_reg.quo_reg_20__and0001(init_reg.quo_reg_20__and00011:O)| NONE(init_reg.quo_reg_20)| 1 |
  750. init_reg.quo_reg_21__and0000(init_reg.quo_reg_21__and00001:O)| NONE(init_reg.quo_reg_21)| 1 |
  751. init_reg.quo_reg_21__and0001(init_reg.quo_reg_21__and00011:O)| NONE(init_reg.quo_reg_21)| 1 |
  752. init_reg.quo_reg_22__and0000(init_reg.quo_reg_22__and00001:O)| NONE(init_reg.quo_reg_22)| 1 |
  753. init_reg.quo_reg_22__and0001(init_reg.quo_reg_22__and00011:O)| NONE(init_reg.quo_reg_22)| 1 |
  754. init_reg.quo_reg_23__and0000(init_reg.quo_reg_23__and00001:O)| NONE(init_reg.quo_reg_23)| 1 |
  755. init_reg.quo_reg_23__and0001(init_reg.quo_reg_23__and00011:O)| NONE(init_reg.quo_reg_23)| 1 |
  756. init_reg.quo_reg_24__and0000(init_reg.quo_reg_24__and00001:O)| NONE(init_reg.quo_reg_24)| 1 |
  757. init_reg.quo_reg_24__and0001(init_reg.quo_reg_24__and00011:O)| NONE(init_reg.quo_reg_24)| 1 |
  758. init_reg.quo_reg_25__and0000(init_reg.quo_reg_25__and00001:O)| NONE(init_reg.quo_reg_25)| 1 |
  759. init_reg.quo_reg_25__and0001(init_reg.quo_reg_25__and00011:O)| NONE(init_reg.quo_reg_25)| 1 |
  760. init_reg.quo_reg_26__and0000(init_reg.quo_reg_26__and00001:O)| NONE(init_reg.quo_reg_26)| 1 |
  761. init_reg.quo_reg_26__and0001(init_reg.quo_reg_26__and00011:O)| NONE(init_reg.quo_reg_26)| 1 |
  762. init_reg.quo_reg_27__and0000(init_reg.quo_reg_27__and00001:O)| NONE(init_reg.quo_reg_27)| 1 |
  763. init_reg.quo_reg_27__and0001(init_reg.quo_reg_27__and00011:O)| NONE(init_reg.quo_reg_27)| 1 |
  764. init_reg.quo_reg_28__and0000(init_reg.quo_reg_28__and00001:O)| NONE(init_reg.quo_reg_28)| 1 |
  765. init_reg.quo_reg_28__and0001(init_reg.quo_reg_28__and00011:O)| NONE(init_reg.quo_reg_28)| 1 |
  766. init_reg.quo_reg_29__and0000(init_reg.quo_reg_29__and00001:O)| NONE(init_reg.quo_reg_29)| 1 |
  767. init_reg.quo_reg_29__and0001(init_reg.quo_reg_29__and00011:O)| NONE(init_reg.quo_reg_29)| 1 |
  768. init_reg.quo_reg_2__and0000(init_reg.quo_reg_2__and00001:O) | NONE(init_reg.quo_reg_2) | 1 |
  769. init_reg.quo_reg_2__and0001(init_reg.quo_reg_2__and00011:O) | NONE(init_reg.quo_reg_2) | 1 |
  770. init_reg.quo_reg_30__and0000(init_reg.quo_reg_30__and00001:O)| NONE(init_reg.quo_reg_30)| 1 |
  771. init_reg.quo_reg_30__and0001(init_reg.quo_reg_30__and00011:O)| NONE(init_reg.quo_reg_30)| 1 |
  772. init_reg.quo_reg_3__and0000(init_reg.quo_reg_3__and00001:O) | NONE(init_reg.quo_reg_3) | 1 |
  773. init_reg.quo_reg_3__and0001(init_reg.quo_reg_3__and00011:O) | NONE(init_reg.quo_reg_3) | 1 |
  774. init_reg.quo_reg_4__and0000(init_reg.quo_reg_4__and00001:O) | NONE(init_reg.quo_reg_4) | 1 |
  775. init_reg.quo_reg_4__and0001(init_reg.quo_reg_4__and00011:O) | NONE(init_reg.quo_reg_4) | 1 |
  776. init_reg.quo_reg_5__and0000(init_reg.quo_reg_5__and00001:O) | NONE(init_reg.quo_reg_5) | 1 |
  777. init_reg.quo_reg_5__and0001(init_reg.quo_reg_5__and00011:O) | NONE(init_reg.quo_reg_5) | 1 |
  778. init_reg.quo_reg_6__and0000(init_reg.quo_reg_6__and00001:O) | NONE(init_reg.quo_reg_6) | 1 |
  779. init_reg.quo_reg_6__and0001(init_reg.quo_reg_6__and00011:O) | NONE(init_reg.quo_reg_6) | 1 |
  780. init_reg.quo_reg_7__and0000(init_reg.quo_reg_7__and00001:O) | NONE(init_reg.quo_reg_7) | 1 |
  781. init_reg.quo_reg_7__and0001(init_reg.quo_reg_7__and00011:O) | NONE(init_reg.quo_reg_7) | 1 |
  782. init_reg.quo_reg_8__and0000(init_reg.quo_reg_8__and00001:O) | NONE(init_reg.quo_reg_8) | 1 |
  783. init_reg.quo_reg_8__and0001(init_reg.quo_reg_8__and00011:O) | NONE(init_reg.quo_reg_8) | 1 |
  784. init_reg.quo_reg_9__and0000(init_reg.quo_reg_9__and00001:O) | NONE(init_reg.quo_reg_9) | 1 |
  785. init_reg.quo_reg_9__and0001(init_reg.quo_reg_9__and00011:O) | NONE(init_reg.quo_reg_9) | 1 |
  786. init_reg.re_reg_0__and0000(init_reg.re_reg_0__and00001:O) | NONE(init_reg.re_reg_0) | 1 |
  787. init_reg.re_reg_0__and0001(init_reg_re_reg_mux0031<0>:O) | NONE(init_reg.re_reg_0) | 1 |
  788. init_reg.re_reg_10__and0000(init_reg.re_reg_10__and00001:O) | NONE(init_reg.re_reg_10) | 1 |
  789. init_reg.re_reg_10__and0001(init_reg.re_reg_10__and00011:O) | NONE(init_reg.re_reg_10) | 1 |
  790. init_reg.re_reg_11__and0000(init_reg.re_reg_11__and00001:O) | NONE(init_reg.re_reg_11) | 1 |
  791. init_reg.re_reg_11__and0001(init_reg.re_reg_11__and00011:O) | NONE(init_reg.re_reg_11) | 1 |
  792. init_reg.re_reg_12__and0000(init_reg.re_reg_12__and00001:O) | NONE(init_reg.re_reg_12) | 1 |
  793. init_reg.re_reg_12__and0001(init_reg.re_reg_12__and00011:O) | NONE(init_reg.re_reg_12) | 1 |
  794. init_reg.re_reg_13__and0000(init_reg.re_reg_13__and00001:O) | NONE(init_reg.re_reg_13) | 1 |
  795. init_reg.re_reg_13__and0001(init_reg.re_reg_13__and00011:O) | NONE(init_reg.re_reg_13) | 1 |
  796. init_reg.re_reg_14__and0000(init_reg.re_reg_14__and00001:O) | NONE(init_reg.re_reg_14) | 1 |
  797. init_reg.re_reg_14__and0001(init_reg.re_reg_14__and00011:O) | NONE(init_reg.re_reg_14) | 1 |
  798. init_reg.re_reg_15__and0000(init_reg.re_reg_15__and00001:O) | NONE(init_reg.re_reg_15) | 1 |
  799. init_reg.re_reg_15__and0001(init_reg.re_reg_15__and00011:O) | NONE(init_reg.re_reg_15) | 1 |
  800. init_reg.re_reg_16__and0000(init_reg.re_reg_16__and00001:O) | NONE(init_reg.re_reg_16) | 1 |
  801. init_reg.re_reg_16__and0001(init_reg.re_reg_16__and00011:O) | NONE(init_reg.re_reg_16) | 1 |
  802. init_reg.re_reg_17__and0000(init_reg.re_reg_17__and00001:O) | NONE(init_reg.re_reg_17) | 1 |
  803. init_reg.re_reg_17__and0001(init_reg.re_reg_17__and00011:O) | NONE(init_reg.re_reg_17) | 1 |
  804. init_reg.re_reg_18__and0000(init_reg.re_reg_18__and00001:O) | NONE(init_reg.re_reg_18) | 1 |
  805. init_reg.re_reg_18__and0001(init_reg.re_reg_18__and00011:O) | NONE(init_reg.re_reg_18) | 1 |
  806. init_reg.re_reg_19__and0000(init_reg.re_reg_19__and00001:O) | NONE(init_reg.re_reg_19) | 1 |
  807. init_reg.re_reg_19__and0001(init_reg.re_reg_19__and00011:O) | NONE(init_reg.re_reg_19) | 1 |
  808. init_reg.re_reg_1__and0000(init_reg.re_reg_1__and00001:O) | NONE(init_reg.re_reg_1) | 1 |
  809. init_reg.re_reg_1__and0001(init_reg.re_reg_1__and00011:O) | NONE(init_reg.re_reg_1) | 1 |
  810. init_reg.re_reg_20__and0000(init_reg.re_reg_20__and00001:O) | NONE(init_reg.re_reg_20) | 1 |
  811. init_reg.re_reg_20__and0001(init_reg.re_reg_20__and00011:O) | NONE(init_reg.re_reg_20) | 1 |
  812. init_reg.re_reg_21__and0000(init_reg.re_reg_21__and00001:O) | NONE(init_reg.re_reg_21) | 1 |
  813. init_reg.re_reg_21__and0001(init_reg.re_reg_21__and00011:O) | NONE(init_reg.re_reg_21) | 1 |
  814. init_reg.re_reg_22__and0000(init_reg.re_reg_22__and00001:O) | NONE(init_reg.re_reg_22) | 1 |
  815. init_reg.re_reg_22__and0001(init_reg.re_reg_22__and00011:O) | NONE(init_reg.re_reg_22) | 1 |
  816. init_reg.re_reg_23__and0000(init_reg.re_reg_23__and00001:O) | NONE(init_reg.re_reg_23) | 1 |
  817. init_reg.re_reg_23__and0001(init_reg.re_reg_23__and00011:O) | NONE(init_reg.re_reg_23) | 1 |
  818. init_reg.re_reg_24__and0000(init_reg.re_reg_24__and00001:O) | NONE(init_reg.re_reg_24) | 1 |
  819. init_reg.re_reg_24__and0001(init_reg.re_reg_24__and00011:O) | NONE(init_reg.re_reg_24) | 1 |
  820. init_reg.re_reg_25__and0000(init_reg.re_reg_25__and00001:O) | NONE(init_reg.re_reg_25) | 1 |
  821. init_reg.re_reg_25__and0001(init_reg.re_reg_25__and00011:O) | NONE(init_reg.re_reg_25) | 1 |
  822. init_reg.re_reg_26__and0000(init_reg.re_reg_26__and00001:O) | NONE(init_reg.re_reg_26) | 1 |
  823. init_reg.re_reg_26__and0001(init_reg.re_reg_26__and00011:O) | NONE(init_reg.re_reg_26) | 1 |
  824. init_reg.re_reg_27__and0000(init_reg.re_reg_27__and00001:O) | NONE(init_reg.re_reg_27) | 1 |
  825. init_reg.re_reg_27__and0001(init_reg.re_reg_27__and00011:O) | NONE(init_reg.re_reg_27) | 1 |
  826. init_reg.re_reg_28__and0000(init_reg.re_reg_28__and00001:O) | NONE(init_reg.re_reg_28) | 1 |
  827. init_reg.re_reg_28__and0001(init_reg.re_reg_28__and00011:O) | NONE(init_reg.re_reg_28) | 1 |
  828. init_reg.re_reg_29__and0000(init_reg.re_reg_29__and00001:O) | NONE(init_reg.re_reg_29) | 1 |
  829. init_reg.re_reg_29__and0001(init_reg.re_reg_29__and00011:O) | NONE(init_reg.re_reg_29) | 1 |
  830. init_reg.re_reg_2__and0000(init_reg.re_reg_2__and00001:O) | NONE(init_reg.re_reg_2) | 1 |
  831. init_reg.re_reg_2__and0001(init_reg.re_reg_2__and00011:O) | NONE(init_reg.re_reg_2) | 1 |
  832. init_reg.re_reg_30__and0000(init_reg.re_reg_30__and00001:O) | NONE(init_reg.re_reg_30) | 1 |
  833. init_reg.re_reg_30__and0001(init_reg.re_reg_30__and00011:O) | NONE(init_reg.re_reg_30) | 1 |
  834. init_reg.re_reg_3__and0000(init_reg.re_reg_3__and00001:O) | NONE(init_reg.re_reg_3) | 1 |
  835. init_reg.re_reg_3__and0001(init_reg.re_reg_3__and00011:O) | NONE(init_reg.re_reg_3) | 1 |
  836. init_reg.re_reg_4__and0000(init_reg.re_reg_4__and00001:O) | NONE(init_reg.re_reg_4) | 1 |
  837. init_reg.re_reg_4__and0001(init_reg.re_reg_4__and00011:O) | NONE(init_reg.re_reg_4) | 1 |
  838. init_reg.re_reg_5__and0000(init_reg.re_reg_5__and00001:O) | NONE(init_reg.re_reg_5) | 1 |
  839. init_reg.re_reg_5__and0001(init_reg.re_reg_5__and00011:O) | NONE(init_reg.re_reg_5) | 1 |
  840. init_reg.re_reg_6__and0000(init_reg.re_reg_6__and00001:O) | NONE(init_reg.re_reg_6) | 1 |
  841. init_reg.re_reg_6__and0001(init_reg.re_reg_6__and00011:O) | NONE(init_reg.re_reg_6) | 1 |
  842. init_reg.re_reg_7__and0000(init_reg.re_reg_7__and00001:O) | NONE(init_reg.re_reg_7) | 1 |
  843. init_reg.re_reg_7__and0001(init_reg.re_reg_7__and00011:O) | NONE(init_reg.re_reg_7) | 1 |
  844. init_reg.re_reg_8__and0000(init_reg.re_reg_8__and00001:O) | NONE(init_reg.re_reg_8) | 1 |
  845. init_reg.re_reg_8__and0001(init_reg.re_reg_8__and00011:O) | NONE(init_reg.re_reg_8) | 1 |
  846. init_reg.re_reg_9__and0000(init_reg.re_reg_9__and00001:O) | NONE(init_reg.re_reg_9) | 1 |
  847. init_reg.re_reg_9__and0001(init_reg.re_reg_9__and00011:O) | NONE(init_reg.re_reg_9) | 1 |
  848. init_reg_re_reg_or0001(init_reg_re_reg_or0001:O) | NONE(init_reg.quo_reg_31)| 1 |
  849. shift_val_0__or0000(shift_val_0__or00001:O) | NONE(shift_val_0) | 1 |
  850. shift_val_0__or0001(shift_val_0__or00011:O) | NONE(shift_val_0) | 1 |
  851. shift_val_1__and0000(shift_val_1__and00001:O) | NONE(shift_val_1) | 1 |
  852. shift_val_1__or0000(shift_val_1__or00001:O) | NONE(shift_val_1) | 1 |
  853. shift_val_2__and0000(shift_val_2__and00001:O) | NONE(shift_val_2) | 1 |
  854. shift_val_2__or0000(shift_val_2__or00001:O) | NONE(shift_val_2) | 1 |
  855. shift_val_3__and0000(shift_val_3__and00001:O) | NONE(shift_val_3) | 1 |
  856. shift_val_3__or0000(shift_val_3__or00001:O) | NONE(shift_val_3) | 1 |
  857. shift_val_4__and0000(shift_val_4__and00001:O) | NONE(shift_val_4) | 1 |
  858. shift_val_4__or0000(shift_val_4__or00001:O) | NONE(shift_val_4) | 1 |
  859. -------------------------------------------------------------+--------------------------+-------+
  860.  
  861. Timing Summary:
  862. ---------------
  863. Speed Grade: -2
  864.  
  865. Minimum period: 37.593ns (Maximum Frequency: 26.601MHz)
  866. Minimum input arrival time before clock: 35.949ns
  867. Maximum output required time after clock: 2.826ns
  868. Maximum combinational path delay: No path found
  869.  
  870. Timing Detail:
  871. --------------
  872. All values displayed in nanoseconds (ns)
  873.  
  874. =========================================================================
  875. Timing constraint: Default period analysis for Clock 'mclk1'
  876. Clock period: 37.593ns (frequency: 26.601MHz)
  877. Total number of paths / destination ports: 387317143681817135877658154893312 / 315
  878. -------------------------------------------------------------------------
  879. Delay: 37.593ns (Levels of Logic = 204)
  880. Source: k_reg.re_reg_31 (FF)
  881. Destination: re_0 (FF)
  882. Source Clock: mclk1 rising
  883. Destination Clock: mclk1 rising
  884.  
  885. Data Path: k_reg.re_reg_31 to re_0
  886. Gate Net
  887. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  888. ---------------------------------------- ------------
  889. FDE:C->Q 2 0.396 0.666 k_reg.re_reg_31 (k_reg.re_reg_31)
  890. LUT4:I0->O 3 0.086 0.421 v_reg0_re_reg_mux0000<31>1 (v_reg0_re_reg_mux0000<31>)
  891. LUT6:I5->O 1 0.086 0.000 Sh13621_G (N2365)
  892. MUXF7:I1->O 7 0.214 0.847 Sh13621 (Sh1362)
  893. LUT6:I1->O 1 0.086 0.000 Sh1406138_G (N2353)
  894. MUXF7:I1->O 4 0.214 0.425 Sh1406138 (Sh1406)
  895. LUT2:I1->O 1 0.086 0.000 Madd_v_re_addsub0017_lut<1> (Madd_v_re_addsub0017_lut<1>)
  896. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0017_cy<1> (Madd_v_re_addsub0017_cy<1>)
  897. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<2> (Madd_v_re_addsub0017_cy<2>)
  898. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<3> (Madd_v_re_addsub0017_cy<3>)
  899. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<4> (Madd_v_re_addsub0017_cy<4>)
  900. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<5> (Madd_v_re_addsub0017_cy<5>)
  901. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<6> (Madd_v_re_addsub0017_cy<6>)
  902. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<7> (Madd_v_re_addsub0017_cy<7>)
  903. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<8> (Madd_v_re_addsub0017_cy<8>)
  904. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<9> (Madd_v_re_addsub0017_cy<9>)
  905. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<10> (Madd_v_re_addsub0017_cy<10>)
  906. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<11> (Madd_v_re_addsub0017_cy<11>)
  907. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<12> (Madd_v_re_addsub0017_cy<12>)
  908. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0017_cy<13> (Madd_v_re_addsub0017_cy<13>)
  909. XORCY:CI->O 3 0.300 0.421 Madd_v_re_addsub0017_xor<14> (v_re_addsub0017<14>)
  910. LUT4:I3->O 1 0.086 0.000 Madd_v_re_addsub0016_lut<14> (Madd_v_re_addsub0016_lut<14>)
  911. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0016_cy<14> (Madd_v_re_addsub0016_cy<14>)
  912. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<15> (Madd_v_re_addsub0016_cy<15>)
  913. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<16> (Madd_v_re_addsub0016_cy<16>)
  914. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<17> (Madd_v_re_addsub0016_cy<17>)
  915. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<18> (Madd_v_re_addsub0016_cy<18>)
  916. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<19> (Madd_v_re_addsub0016_cy<19>)
  917. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<20> (Madd_v_re_addsub0016_cy<20>)
  918. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<21> (Madd_v_re_addsub0016_cy<21>)
  919. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<22> (Madd_v_re_addsub0016_cy<22>)
  920. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<23> (Madd_v_re_addsub0016_cy<23>)
  921. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<24> (Madd_v_re_addsub0016_cy<24>)
  922. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0016_cy<25> (Madd_v_re_addsub0016_cy<25>)
  923. XORCY:CI->O 3 0.300 0.421 Madd_v_re_addsub0016_xor<26> (v_re_addsub0016<26>)
  924. LUT5:I4->O 1 0.086 0.000 Madd_v_re_addsub0015_lut<26> (Madd_v_re_addsub0015_lut<26>)
  925. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0015_cy<26> (Madd_v_re_addsub0015_cy<26>)
  926. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0015_xor<27> (v_re_addsub0015<27>)
  927. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0014_lut<27> (Madd_v_re_addsub0014_lut<27>)
  928. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0014_cy<27> (Madd_v_re_addsub0014_cy<27>)
  929. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0014_xor<28> (v_re_addsub0014<28>)
  930. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0013_lut<28> (Madd_v_re_addsub0013_lut<28>)
  931. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0013_cy<28> (Madd_v_re_addsub0013_cy<28>)
  932. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0013_xor<29> (v_re_addsub0013<29>)
  933. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0011_lut<29> (Madd_v_re_addsub0011_lut<29>)
  934. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0011_cy<29> (Madd_v_re_addsub0011_cy<29>)
  935. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0011_xor<30> (v_re_addsub0011<30>)
  936. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0009_lut<30> (Madd_v_re_addsub0009_lut<30>)
  937. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0009_cy<30> (Madd_v_re_addsub0009_cy<30>)
  938. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0009_xor<31> (v_re_addsub0009<31>)
  939. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0007_lut<31> (Madd_v_re_addsub0007_lut<31>)
  940. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0007_cy<31> (Madd_v_re_addsub0007_cy<31>)
  941. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0007_xor<32> (v_re_addsub0007<32>)
  942. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0005_lut<32> (Madd_v_re_addsub0005_lut<32>)
  943. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0005_cy<32> (Madd_v_re_addsub0005_cy<32>)
  944. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0005_xor<33> (v_re_addsub0005<33>)
  945. LUT6:I5->O 6 0.086 0.685 v_re_mux0009<33>1 (v_re_mux0009<33>)
  946. LUT4:I0->O 1 0.086 0.819 Mcompar_v_re_cmp_ge0008_lut<16> (Mcompar_v_re_cmp_ge0008_lut<16>)
  947. LUT5:I0->O 279 0.086 0.559 Mcompar_v_re_cmp_ge0008_cy<16>1 (v_re_cmp_ge0008)
  948. LUT3:I2->O 2 0.086 0.666 v_re_mux0010<0>1 (v_re_mux0010<0>)
  949. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0007_lut<0> (Mcompar_v_re_cmp_ge0007_lut<0>)
  950. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0007_cy<0> (Mcompar_v_re_cmp_ge0007_cy<0>)
  951. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<1> (Mcompar_v_re_cmp_ge0007_cy<1>)
  952. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<2> (Mcompar_v_re_cmp_ge0007_cy<2>)
  953. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<3> (Mcompar_v_re_cmp_ge0007_cy<3>)
  954. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<4> (Mcompar_v_re_cmp_ge0007_cy<4>)
  955. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<5> (Mcompar_v_re_cmp_ge0007_cy<5>)
  956. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<6> (Mcompar_v_re_cmp_ge0007_cy<6>)
  957. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<7> (Mcompar_v_re_cmp_ge0007_cy<7>)
  958. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<8> (Mcompar_v_re_cmp_ge0007_cy<8>)
  959. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<9> (Mcompar_v_re_cmp_ge0007_cy<9>)
  960. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<10> (Mcompar_v_re_cmp_ge0007_cy<10>)
  961. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<11> (Mcompar_v_re_cmp_ge0007_cy<11>)
  962. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<12> (Mcompar_v_re_cmp_ge0007_cy<12>)
  963. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<13> (Mcompar_v_re_cmp_ge0007_cy<13>)
  964. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0007_cy<14> (Mcompar_v_re_cmp_ge0007_cy<14>)
  965. LUT5:I4->O 255 0.086 0.555 Mcompar_v_re_cmp_ge0007_cy<16>1 (v_re_cmp_ge0007)
  966. LUT5:I4->O 6 0.086 0.685 v_re_mux0011<0>1 (v_re_mux0011<0>)
  967. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0006_lut<0> (Mcompar_v_re_cmp_ge0006_lut<0>)
  968. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0006_cy<0> (Mcompar_v_re_cmp_ge0006_cy<0>)
  969. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<1> (Mcompar_v_re_cmp_ge0006_cy<1>)
  970. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<2> (Mcompar_v_re_cmp_ge0006_cy<2>)
  971. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<3> (Mcompar_v_re_cmp_ge0006_cy<3>)
  972. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<4> (Mcompar_v_re_cmp_ge0006_cy<4>)
  973. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<5> (Mcompar_v_re_cmp_ge0006_cy<5>)
  974. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<6> (Mcompar_v_re_cmp_ge0006_cy<6>)
  975. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<7> (Mcompar_v_re_cmp_ge0006_cy<7>)
  976. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<8> (Mcompar_v_re_cmp_ge0006_cy<8>)
  977. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<9> (Mcompar_v_re_cmp_ge0006_cy<9>)
  978. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<10> (Mcompar_v_re_cmp_ge0006_cy<10>)
  979. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<11> (Mcompar_v_re_cmp_ge0006_cy<11>)
  980. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<12> (Mcompar_v_re_cmp_ge0006_cy<12>)
  981. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<13> (Mcompar_v_re_cmp_ge0006_cy<13>)
  982. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0006_cy<14> (Mcompar_v_re_cmp_ge0006_cy<14>)
  983. LUT5:I4->O 284 0.086 0.559 Mcompar_v_re_cmp_ge0006_cy<16>1 (v_re_cmp_ge0006)
  984. LUT3:I2->O 2 0.086 0.666 v_re_mux0012<0>1 (v_re_mux0012<0>)
  985. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0005_lut<0> (Mcompar_v_re_cmp_ge0005_lut<0>)
  986. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0005_cy<0> (Mcompar_v_re_cmp_ge0005_cy<0>)
  987. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<1> (Mcompar_v_re_cmp_ge0005_cy<1>)
  988. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<2> (Mcompar_v_re_cmp_ge0005_cy<2>)
  989. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<3> (Mcompar_v_re_cmp_ge0005_cy<3>)
  990. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<4> (Mcompar_v_re_cmp_ge0005_cy<4>)
  991. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<5> (Mcompar_v_re_cmp_ge0005_cy<5>)
  992. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<6> (Mcompar_v_re_cmp_ge0005_cy<6>)
  993. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<7> (Mcompar_v_re_cmp_ge0005_cy<7>)
  994. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<8> (Mcompar_v_re_cmp_ge0005_cy<8>)
  995. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<9> (Mcompar_v_re_cmp_ge0005_cy<9>)
  996. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<10> (Mcompar_v_re_cmp_ge0005_cy<10>)
  997. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<11> (Mcompar_v_re_cmp_ge0005_cy<11>)
  998. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<12> (Mcompar_v_re_cmp_ge0005_cy<12>)
  999. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<13> (Mcompar_v_re_cmp_ge0005_cy<13>)
  1000. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0005_cy<14> (Mcompar_v_re_cmp_ge0005_cy<14>)
  1001. LUT5:I4->O 188 0.086 0.544 Mcompar_v_re_cmp_ge0005_cy<16>1 (v_re_cmp_ge0005)
  1002. LUT5:I4->O 6 0.086 0.685 v_re_mux0013<0>1 (v_re_mux0013<0>)
  1003. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0004_lut<0> (Mcompar_v_re_cmp_ge0004_lut<0>)
  1004. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0004_cy<0> (Mcompar_v_re_cmp_ge0004_cy<0>)
  1005. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<1> (Mcompar_v_re_cmp_ge0004_cy<1>)
  1006. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<2> (Mcompar_v_re_cmp_ge0004_cy<2>)
  1007. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<3> (Mcompar_v_re_cmp_ge0004_cy<3>)
  1008. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<4> (Mcompar_v_re_cmp_ge0004_cy<4>)
  1009. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<5> (Mcompar_v_re_cmp_ge0004_cy<5>)
  1010. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<6> (Mcompar_v_re_cmp_ge0004_cy<6>)
  1011. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<7> (Mcompar_v_re_cmp_ge0004_cy<7>)
  1012. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<8> (Mcompar_v_re_cmp_ge0004_cy<8>)
  1013. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<9> (Mcompar_v_re_cmp_ge0004_cy<9>)
  1014. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<10> (Mcompar_v_re_cmp_ge0004_cy<10>)
  1015. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<11> (Mcompar_v_re_cmp_ge0004_cy<11>)
  1016. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<12> (Mcompar_v_re_cmp_ge0004_cy<12>)
  1017. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<13> (Mcompar_v_re_cmp_ge0004_cy<13>)
  1018. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0004_cy<14> (Mcompar_v_re_cmp_ge0004_cy<14>)
  1019. LUT5:I4->O 287 0.086 0.560 Mcompar_v_re_cmp_ge0004_cy<16>1 (v_re_cmp_ge0004)
  1020. LUT3:I2->O 2 0.086 0.666 v_re_mux0014<0>1 (v_re_mux0014<0>)
  1021. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0003_lut<0> (Mcompar_v_re_cmp_ge0003_lut<0>)
  1022. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0003_cy<0> (Mcompar_v_re_cmp_ge0003_cy<0>)
  1023. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<1> (Mcompar_v_re_cmp_ge0003_cy<1>)
  1024. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<2> (Mcompar_v_re_cmp_ge0003_cy<2>)
  1025. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<3> (Mcompar_v_re_cmp_ge0003_cy<3>)
  1026. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<4> (Mcompar_v_re_cmp_ge0003_cy<4>)
  1027. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<5> (Mcompar_v_re_cmp_ge0003_cy<5>)
  1028. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<6> (Mcompar_v_re_cmp_ge0003_cy<6>)
  1029. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<7> (Mcompar_v_re_cmp_ge0003_cy<7>)
  1030. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<8> (Mcompar_v_re_cmp_ge0003_cy<8>)
  1031. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<9> (Mcompar_v_re_cmp_ge0003_cy<9>)
  1032. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<10> (Mcompar_v_re_cmp_ge0003_cy<10>)
  1033. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<11> (Mcompar_v_re_cmp_ge0003_cy<11>)
  1034. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<12> (Mcompar_v_re_cmp_ge0003_cy<12>)
  1035. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<13> (Mcompar_v_re_cmp_ge0003_cy<13>)
  1036. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<14> (Mcompar_v_re_cmp_ge0003_cy<14>)
  1037. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<15> (Mcompar_v_re_cmp_ge0003_cy<15>)
  1038. MUXCY:CI->O 178 0.222 0.543 Mcompar_v_re_cmp_ge0003_cy<16> (v_re_cmp_ge0003)
  1039. LUT5:I4->O 6 0.086 0.685 v_re_mux0015<0>1 (v_re_mux0015<0>)
  1040. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0002_lut<0> (Mcompar_v_re_cmp_ge0002_lut<0>)
  1041. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0002_cy<0> (Mcompar_v_re_cmp_ge0002_cy<0>)
  1042. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<1> (Mcompar_v_re_cmp_ge0002_cy<1>)
  1043. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<2> (Mcompar_v_re_cmp_ge0002_cy<2>)
  1044. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<3> (Mcompar_v_re_cmp_ge0002_cy<3>)
  1045. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<4> (Mcompar_v_re_cmp_ge0002_cy<4>)
  1046. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<5> (Mcompar_v_re_cmp_ge0002_cy<5>)
  1047. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<6> (Mcompar_v_re_cmp_ge0002_cy<6>)
  1048. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<7> (Mcompar_v_re_cmp_ge0002_cy<7>)
  1049. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<8> (Mcompar_v_re_cmp_ge0002_cy<8>)
  1050. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<9> (Mcompar_v_re_cmp_ge0002_cy<9>)
  1051. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<10> (Mcompar_v_re_cmp_ge0002_cy<10>)
  1052. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<11> (Mcompar_v_re_cmp_ge0002_cy<11>)
  1053. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<12> (Mcompar_v_re_cmp_ge0002_cy<12>)
  1054. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<13> (Mcompar_v_re_cmp_ge0002_cy<13>)
  1055. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0002_cy<14> (Mcompar_v_re_cmp_ge0002_cy<14>)
  1056. LUT5:I4->O 236 0.086 0.552 Mcompar_v_re_cmp_ge0002_cy<16>1 (v_re_cmp_ge0002)
  1057. LUT3:I2->O 3 0.086 0.671 v_re_mux0016<0>1 (v_re_mux0016<0>)
  1058. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0001_lut<0> (Mcompar_v_re_cmp_ge0001_lut<0>)
  1059. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0001_cy<0> (Mcompar_v_re_cmp_ge0001_cy<0>)
  1060. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<1> (Mcompar_v_re_cmp_ge0001_cy<1>)
  1061. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<2> (Mcompar_v_re_cmp_ge0001_cy<2>)
  1062. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<3> (Mcompar_v_re_cmp_ge0001_cy<3>)
  1063. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<4> (Mcompar_v_re_cmp_ge0001_cy<4>)
  1064. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<5> (Mcompar_v_re_cmp_ge0001_cy<5>)
  1065. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<6> (Mcompar_v_re_cmp_ge0001_cy<6>)
  1066. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<7> (Mcompar_v_re_cmp_ge0001_cy<7>)
  1067. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<8> (Mcompar_v_re_cmp_ge0001_cy<8>)
  1068. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<9> (Mcompar_v_re_cmp_ge0001_cy<9>)
  1069. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<10> (Mcompar_v_re_cmp_ge0001_cy<10>)
  1070. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<11> (Mcompar_v_re_cmp_ge0001_cy<11>)
  1071. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<12> (Mcompar_v_re_cmp_ge0001_cy<12>)
  1072. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<13> (Mcompar_v_re_cmp_ge0001_cy<13>)
  1073. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0001_cy<14> (Mcompar_v_re_cmp_ge0001_cy<14>)
  1074. LUT5:I4->O 164 0.086 0.541 Mcompar_v_re_cmp_ge0001_cy<16>1 (v_re_cmp_ge0001)
  1075. LUT5:I4->O 2 0.086 0.666 v_re_mux0017<0>1 (v_re_mux0017<0>)
  1076. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0000_lut<0> (Mcompar_v_re_cmp_ge0000_lut<0>)
  1077. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0000_cy<0> (Mcompar_v_re_cmp_ge0000_cy<0>)
  1078. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<1> (Mcompar_v_re_cmp_ge0000_cy<1>)
  1079. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<2> (Mcompar_v_re_cmp_ge0000_cy<2>)
  1080. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<3> (Mcompar_v_re_cmp_ge0000_cy<3>)
  1081. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<4> (Mcompar_v_re_cmp_ge0000_cy<4>)
  1082. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<5> (Mcompar_v_re_cmp_ge0000_cy<5>)
  1083. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<6> (Mcompar_v_re_cmp_ge0000_cy<6>)
  1084. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<7> (Mcompar_v_re_cmp_ge0000_cy<7>)
  1085. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<8> (Mcompar_v_re_cmp_ge0000_cy<8>)
  1086. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<9> (Mcompar_v_re_cmp_ge0000_cy<9>)
  1087. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<10> (Mcompar_v_re_cmp_ge0000_cy<10>)
  1088. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<11> (Mcompar_v_re_cmp_ge0000_cy<11>)
  1089. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<12> (Mcompar_v_re_cmp_ge0000_cy<12>)
  1090. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<13> (Mcompar_v_re_cmp_ge0000_cy<13>)
  1091. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0000_cy<14> (Mcompar_v_re_cmp_ge0000_cy<14>)
  1092. LUT5:I4->O 64 0.086 0.525 Mcompar_v_re_cmp_ge0000_cy<16>1 (v_re_cmp_ge0000)
  1093. LUT5:I4->O 1 0.086 0.000 v_re_mux0018<31>1 (v_re_mux0018<31>)
  1094. FD:D -0.022 re_31
  1095. ----------------------------------------
  1096. Total 37.593ns (16.772ns logic, 20.821ns route)
  1097. (44.6% logic, 55.4% route)
  1098.  
  1099. =========================================================================
  1100. Timing constraint: Default period analysis for Clock 'divisor<0>'
  1101. Clock period: 3.737ns (frequency: 267.560MHz)
  1102. Total number of paths / destination ports: 900 / 62
  1103. -------------------------------------------------------------------------
  1104. Delay: 3.737ns (Levels of Logic = 4)
  1105. Source: shift_val_1 (LATCH)
  1106. Destination: init_reg.re_reg_13 (LATCH)
  1107. Source Clock: divisor<0> falling
  1108. Destination Clock: divisor<0> falling
  1109.  
  1110. Data Path: shift_val_1 to init_reg.re_reg_13
  1111. Gate Net
  1112. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1113. ---------------------------------------- ------------
  1114. LDCP:G->Q 150 0.610 1.027 shift_val_1 (shift_val_1)
  1115. LUT6:I0->O 3 0.086 0.421 Sh10341 (Sh1034)
  1116. LUT6:I5->O 3 0.086 0.421 Sh12931 (Sh1293)
  1117. LUT5:I4->O 4 0.086 0.914 Sh10061 (Sh1006)
  1118. LUT6:I0->O 3 0.086 0.000 init_reg_re_reg_mux0031<13>1 (init_reg_re_reg_mux0031<13>)
  1119. LDCP:D -0.066 init_reg.re_reg_13
  1120. ----------------------------------------
  1121. Total 3.737ns (0.954ns logic, 2.783ns route)
  1122. (25.5% logic, 74.5% route)
  1123.  
  1124. =========================================================================
  1125. Timing constraint: Default OFFSET IN BEFORE for Clock 'mclk1'
  1126. Total number of paths / destination ports: 6969441739846737913835010654208 / 71
  1127. -------------------------------------------------------------------------
  1128. Offset: 35.949ns (Levels of Logic = 201)
  1129. Source: divisor<0> (PAD)
  1130. Destination: re_0 (FF)
  1131. Destination Clock: mclk1 rising
  1132.  
  1133. Data Path: divisor<0> to re_0
  1134. Gate Net
  1135. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1136. ---------------------------------------- ------------
  1137. IBUF:I->O 37 0.694 1.010 divisor_0_IBUF (divisor_0_IBUF1)
  1138. LUT6:I0->O 1 0.086 0.000 Madd_v_re_addsub0017_lut<0> (Madd_v_re_addsub0017_lut<0>)
  1139. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0017_cy<0> (Madd_v_re_addsub0017_cy<0>)
  1140. XORCY:CI->O 3 0.300 0.421 Madd_v_re_addsub0017_xor<1> (v_re_addsub0017<1>)
  1141. LUT4:I3->O 1 0.086 0.000 Madd_v_re_addsub0016_lut<1> (Madd_v_re_addsub0016_lut<1>)
  1142. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0016_cy<1> (Madd_v_re_addsub0016_cy<1>)
  1143. XORCY:CI->O 2 0.300 0.491 Madd_v_re_addsub0016_xor<2> (v_re_addsub0016<2>)
  1144. LUT6:I4->O 1 0.086 0.000 Madd_v_re_addsub0015_lut<2> (Madd_v_re_addsub0015_lut<2>)
  1145. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0015_cy<2> (Madd_v_re_addsub0015_cy<2>)
  1146. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<3> (Madd_v_re_addsub0015_cy<3>)
  1147. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<4> (Madd_v_re_addsub0015_cy<4>)
  1148. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<5> (Madd_v_re_addsub0015_cy<5>)
  1149. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<6> (Madd_v_re_addsub0015_cy<6>)
  1150. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<7> (Madd_v_re_addsub0015_cy<7>)
  1151. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<8> (Madd_v_re_addsub0015_cy<8>)
  1152. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<9> (Madd_v_re_addsub0015_cy<9>)
  1153. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<10> (Madd_v_re_addsub0015_cy<10>)
  1154. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<11> (Madd_v_re_addsub0015_cy<11>)
  1155. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<12> (Madd_v_re_addsub0015_cy<12>)
  1156. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<13> (Madd_v_re_addsub0015_cy<13>)
  1157. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<14> (Madd_v_re_addsub0015_cy<14>)
  1158. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<15> (Madd_v_re_addsub0015_cy<15>)
  1159. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<16> (Madd_v_re_addsub0015_cy<16>)
  1160. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<17> (Madd_v_re_addsub0015_cy<17>)
  1161. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<18> (Madd_v_re_addsub0015_cy<18>)
  1162. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<19> (Madd_v_re_addsub0015_cy<19>)
  1163. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<20> (Madd_v_re_addsub0015_cy<20>)
  1164. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<21> (Madd_v_re_addsub0015_cy<21>)
  1165. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<22> (Madd_v_re_addsub0015_cy<22>)
  1166. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<23> (Madd_v_re_addsub0015_cy<23>)
  1167. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<24> (Madd_v_re_addsub0015_cy<24>)
  1168. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<25> (Madd_v_re_addsub0015_cy<25>)
  1169. MUXCY:CI->O 1 0.023 0.000 Madd_v_re_addsub0015_cy<26> (Madd_v_re_addsub0015_cy<26>)
  1170. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0015_xor<27> (v_re_addsub0015<27>)
  1171. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0014_lut<27> (Madd_v_re_addsub0014_lut<27>)
  1172. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0014_cy<27> (Madd_v_re_addsub0014_cy<27>)
  1173. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0014_xor<28> (v_re_addsub0014<28>)
  1174. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0013_lut<28> (Madd_v_re_addsub0013_lut<28>)
  1175. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0013_cy<28> (Madd_v_re_addsub0013_cy<28>)
  1176. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0013_xor<29> (v_re_addsub0013<29>)
  1177. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0011_lut<29> (Madd_v_re_addsub0011_lut<29>)
  1178. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0011_cy<29> (Madd_v_re_addsub0011_cy<29>)
  1179. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0011_xor<30> (v_re_addsub0011<30>)
  1180. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0009_lut<30> (Madd_v_re_addsub0009_lut<30>)
  1181. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0009_cy<30> (Madd_v_re_addsub0009_cy<30>)
  1182. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0009_xor<31> (v_re_addsub0009<31>)
  1183. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0007_lut<31> (Madd_v_re_addsub0007_lut<31>)
  1184. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0007_cy<31> (Madd_v_re_addsub0007_cy<31>)
  1185. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0007_xor<32> (v_re_addsub0007<32>)
  1186. LUT6:I5->O 1 0.086 0.000 Madd_v_re_addsub0005_lut<32> (Madd_v_re_addsub0005_lut<32>)
  1187. MUXCY:S->O 1 0.305 0.000 Madd_v_re_addsub0005_cy<32> (Madd_v_re_addsub0005_cy<32>)
  1188. XORCY:CI->O 2 0.300 0.416 Madd_v_re_addsub0005_xor<33> (v_re_addsub0005<33>)
  1189. LUT6:I5->O 6 0.086 0.685 v_re_mux0009<33>1 (v_re_mux0009<33>)
  1190. LUT4:I0->O 1 0.086 0.819 Mcompar_v_re_cmp_ge0008_lut<16> (Mcompar_v_re_cmp_ge0008_lut<16>)
  1191. LUT5:I0->O 279 0.086 0.559 Mcompar_v_re_cmp_ge0008_cy<16>1 (v_re_cmp_ge0008)
  1192. LUT3:I2->O 2 0.086 0.666 v_re_mux0010<0>1 (v_re_mux0010<0>)
  1193. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0007_lut<0> (Mcompar_v_re_cmp_ge0007_lut<0>)
  1194. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0007_cy<0> (Mcompar_v_re_cmp_ge0007_cy<0>)
  1195. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<1> (Mcompar_v_re_cmp_ge0007_cy<1>)
  1196. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<2> (Mcompar_v_re_cmp_ge0007_cy<2>)
  1197. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<3> (Mcompar_v_re_cmp_ge0007_cy<3>)
  1198. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<4> (Mcompar_v_re_cmp_ge0007_cy<4>)
  1199. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<5> (Mcompar_v_re_cmp_ge0007_cy<5>)
  1200. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<6> (Mcompar_v_re_cmp_ge0007_cy<6>)
  1201. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<7> (Mcompar_v_re_cmp_ge0007_cy<7>)
  1202. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<8> (Mcompar_v_re_cmp_ge0007_cy<8>)
  1203. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<9> (Mcompar_v_re_cmp_ge0007_cy<9>)
  1204. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<10> (Mcompar_v_re_cmp_ge0007_cy<10>)
  1205. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<11> (Mcompar_v_re_cmp_ge0007_cy<11>)
  1206. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<12> (Mcompar_v_re_cmp_ge0007_cy<12>)
  1207. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0007_cy<13> (Mcompar_v_re_cmp_ge0007_cy<13>)
  1208. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0007_cy<14> (Mcompar_v_re_cmp_ge0007_cy<14>)
  1209. LUT5:I4->O 255 0.086 0.555 Mcompar_v_re_cmp_ge0007_cy<16>1 (v_re_cmp_ge0007)
  1210. LUT5:I4->O 6 0.086 0.685 v_re_mux0011<0>1 (v_re_mux0011<0>)
  1211. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0006_lut<0> (Mcompar_v_re_cmp_ge0006_lut<0>)
  1212. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0006_cy<0> (Mcompar_v_re_cmp_ge0006_cy<0>)
  1213. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<1> (Mcompar_v_re_cmp_ge0006_cy<1>)
  1214. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<2> (Mcompar_v_re_cmp_ge0006_cy<2>)
  1215. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<3> (Mcompar_v_re_cmp_ge0006_cy<3>)
  1216. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<4> (Mcompar_v_re_cmp_ge0006_cy<4>)
  1217. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<5> (Mcompar_v_re_cmp_ge0006_cy<5>)
  1218. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<6> (Mcompar_v_re_cmp_ge0006_cy<6>)
  1219. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<7> (Mcompar_v_re_cmp_ge0006_cy<7>)
  1220. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<8> (Mcompar_v_re_cmp_ge0006_cy<8>)
  1221. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<9> (Mcompar_v_re_cmp_ge0006_cy<9>)
  1222. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<10> (Mcompar_v_re_cmp_ge0006_cy<10>)
  1223. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<11> (Mcompar_v_re_cmp_ge0006_cy<11>)
  1224. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<12> (Mcompar_v_re_cmp_ge0006_cy<12>)
  1225. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0006_cy<13> (Mcompar_v_re_cmp_ge0006_cy<13>)
  1226. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0006_cy<14> (Mcompar_v_re_cmp_ge0006_cy<14>)
  1227. LUT5:I4->O 284 0.086 0.559 Mcompar_v_re_cmp_ge0006_cy<16>1 (v_re_cmp_ge0006)
  1228. LUT3:I2->O 2 0.086 0.666 v_re_mux0012<0>1 (v_re_mux0012<0>)
  1229. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0005_lut<0> (Mcompar_v_re_cmp_ge0005_lut<0>)
  1230. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0005_cy<0> (Mcompar_v_re_cmp_ge0005_cy<0>)
  1231. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<1> (Mcompar_v_re_cmp_ge0005_cy<1>)
  1232. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<2> (Mcompar_v_re_cmp_ge0005_cy<2>)
  1233. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<3> (Mcompar_v_re_cmp_ge0005_cy<3>)
  1234. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<4> (Mcompar_v_re_cmp_ge0005_cy<4>)
  1235. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<5> (Mcompar_v_re_cmp_ge0005_cy<5>)
  1236. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<6> (Mcompar_v_re_cmp_ge0005_cy<6>)
  1237. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<7> (Mcompar_v_re_cmp_ge0005_cy<7>)
  1238. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<8> (Mcompar_v_re_cmp_ge0005_cy<8>)
  1239. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<9> (Mcompar_v_re_cmp_ge0005_cy<9>)
  1240. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<10> (Mcompar_v_re_cmp_ge0005_cy<10>)
  1241. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<11> (Mcompar_v_re_cmp_ge0005_cy<11>)
  1242. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<12> (Mcompar_v_re_cmp_ge0005_cy<12>)
  1243. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0005_cy<13> (Mcompar_v_re_cmp_ge0005_cy<13>)
  1244. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0005_cy<14> (Mcompar_v_re_cmp_ge0005_cy<14>)
  1245. LUT5:I4->O 188 0.086 0.544 Mcompar_v_re_cmp_ge0005_cy<16>1 (v_re_cmp_ge0005)
  1246. LUT5:I4->O 6 0.086 0.685 v_re_mux0013<0>1 (v_re_mux0013<0>)
  1247. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0004_lut<0> (Mcompar_v_re_cmp_ge0004_lut<0>)
  1248. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0004_cy<0> (Mcompar_v_re_cmp_ge0004_cy<0>)
  1249. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<1> (Mcompar_v_re_cmp_ge0004_cy<1>)
  1250. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<2> (Mcompar_v_re_cmp_ge0004_cy<2>)
  1251. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<3> (Mcompar_v_re_cmp_ge0004_cy<3>)
  1252. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<4> (Mcompar_v_re_cmp_ge0004_cy<4>)
  1253. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<5> (Mcompar_v_re_cmp_ge0004_cy<5>)
  1254. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<6> (Mcompar_v_re_cmp_ge0004_cy<6>)
  1255. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<7> (Mcompar_v_re_cmp_ge0004_cy<7>)
  1256. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<8> (Mcompar_v_re_cmp_ge0004_cy<8>)
  1257. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<9> (Mcompar_v_re_cmp_ge0004_cy<9>)
  1258. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<10> (Mcompar_v_re_cmp_ge0004_cy<10>)
  1259. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<11> (Mcompar_v_re_cmp_ge0004_cy<11>)
  1260. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<12> (Mcompar_v_re_cmp_ge0004_cy<12>)
  1261. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0004_cy<13> (Mcompar_v_re_cmp_ge0004_cy<13>)
  1262. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0004_cy<14> (Mcompar_v_re_cmp_ge0004_cy<14>)
  1263. LUT5:I4->O 287 0.086 0.560 Mcompar_v_re_cmp_ge0004_cy<16>1 (v_re_cmp_ge0004)
  1264. LUT3:I2->O 2 0.086 0.666 v_re_mux0014<0>1 (v_re_mux0014<0>)
  1265. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0003_lut<0> (Mcompar_v_re_cmp_ge0003_lut<0>)
  1266. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0003_cy<0> (Mcompar_v_re_cmp_ge0003_cy<0>)
  1267. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<1> (Mcompar_v_re_cmp_ge0003_cy<1>)
  1268. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<2> (Mcompar_v_re_cmp_ge0003_cy<2>)
  1269. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<3> (Mcompar_v_re_cmp_ge0003_cy<3>)
  1270. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<4> (Mcompar_v_re_cmp_ge0003_cy<4>)
  1271. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<5> (Mcompar_v_re_cmp_ge0003_cy<5>)
  1272. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<6> (Mcompar_v_re_cmp_ge0003_cy<6>)
  1273. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<7> (Mcompar_v_re_cmp_ge0003_cy<7>)
  1274. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<8> (Mcompar_v_re_cmp_ge0003_cy<8>)
  1275. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<9> (Mcompar_v_re_cmp_ge0003_cy<9>)
  1276. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<10> (Mcompar_v_re_cmp_ge0003_cy<10>)
  1277. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<11> (Mcompar_v_re_cmp_ge0003_cy<11>)
  1278. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<12> (Mcompar_v_re_cmp_ge0003_cy<12>)
  1279. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<13> (Mcompar_v_re_cmp_ge0003_cy<13>)
  1280. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<14> (Mcompar_v_re_cmp_ge0003_cy<14>)
  1281. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0003_cy<15> (Mcompar_v_re_cmp_ge0003_cy<15>)
  1282. MUXCY:CI->O 178 0.222 0.543 Mcompar_v_re_cmp_ge0003_cy<16> (v_re_cmp_ge0003)
  1283. LUT5:I4->O 6 0.086 0.685 v_re_mux0015<0>1 (v_re_mux0015<0>)
  1284. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0002_lut<0> (Mcompar_v_re_cmp_ge0002_lut<0>)
  1285. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0002_cy<0> (Mcompar_v_re_cmp_ge0002_cy<0>)
  1286. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<1> (Mcompar_v_re_cmp_ge0002_cy<1>)
  1287. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<2> (Mcompar_v_re_cmp_ge0002_cy<2>)
  1288. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<3> (Mcompar_v_re_cmp_ge0002_cy<3>)
  1289. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<4> (Mcompar_v_re_cmp_ge0002_cy<4>)
  1290. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<5> (Mcompar_v_re_cmp_ge0002_cy<5>)
  1291. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<6> (Mcompar_v_re_cmp_ge0002_cy<6>)
  1292. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<7> (Mcompar_v_re_cmp_ge0002_cy<7>)
  1293. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<8> (Mcompar_v_re_cmp_ge0002_cy<8>)
  1294. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<9> (Mcompar_v_re_cmp_ge0002_cy<9>)
  1295. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<10> (Mcompar_v_re_cmp_ge0002_cy<10>)
  1296. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<11> (Mcompar_v_re_cmp_ge0002_cy<11>)
  1297. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<12> (Mcompar_v_re_cmp_ge0002_cy<12>)
  1298. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0002_cy<13> (Mcompar_v_re_cmp_ge0002_cy<13>)
  1299. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0002_cy<14> (Mcompar_v_re_cmp_ge0002_cy<14>)
  1300. LUT5:I4->O 236 0.086 0.552 Mcompar_v_re_cmp_ge0002_cy<16>1 (v_re_cmp_ge0002)
  1301. LUT3:I2->O 3 0.086 0.671 v_re_mux0016<0>1 (v_re_mux0016<0>)
  1302. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0001_lut<0> (Mcompar_v_re_cmp_ge0001_lut<0>)
  1303. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0001_cy<0> (Mcompar_v_re_cmp_ge0001_cy<0>)
  1304. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<1> (Mcompar_v_re_cmp_ge0001_cy<1>)
  1305. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<2> (Mcompar_v_re_cmp_ge0001_cy<2>)
  1306. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<3> (Mcompar_v_re_cmp_ge0001_cy<3>)
  1307. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<4> (Mcompar_v_re_cmp_ge0001_cy<4>)
  1308. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<5> (Mcompar_v_re_cmp_ge0001_cy<5>)
  1309. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<6> (Mcompar_v_re_cmp_ge0001_cy<6>)
  1310. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<7> (Mcompar_v_re_cmp_ge0001_cy<7>)
  1311. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<8> (Mcompar_v_re_cmp_ge0001_cy<8>)
  1312. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<9> (Mcompar_v_re_cmp_ge0001_cy<9>)
  1313. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<10> (Mcompar_v_re_cmp_ge0001_cy<10>)
  1314. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<11> (Mcompar_v_re_cmp_ge0001_cy<11>)
  1315. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<12> (Mcompar_v_re_cmp_ge0001_cy<12>)
  1316. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0001_cy<13> (Mcompar_v_re_cmp_ge0001_cy<13>)
  1317. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0001_cy<14> (Mcompar_v_re_cmp_ge0001_cy<14>)
  1318. LUT5:I4->O 164 0.086 0.541 Mcompar_v_re_cmp_ge0001_cy<16>1 (v_re_cmp_ge0001)
  1319. LUT5:I4->O 2 0.086 0.666 v_re_mux0017<0>1 (v_re_mux0017<0>)
  1320. LUT4:I0->O 1 0.086 0.000 Mcompar_v_re_cmp_ge0000_lut<0> (Mcompar_v_re_cmp_ge0000_lut<0>)
  1321. MUXCY:S->O 1 0.305 0.000 Mcompar_v_re_cmp_ge0000_cy<0> (Mcompar_v_re_cmp_ge0000_cy<0>)
  1322. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<1> (Mcompar_v_re_cmp_ge0000_cy<1>)
  1323. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<2> (Mcompar_v_re_cmp_ge0000_cy<2>)
  1324. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<3> (Mcompar_v_re_cmp_ge0000_cy<3>)
  1325. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<4> (Mcompar_v_re_cmp_ge0000_cy<4>)
  1326. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<5> (Mcompar_v_re_cmp_ge0000_cy<5>)
  1327. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<6> (Mcompar_v_re_cmp_ge0000_cy<6>)
  1328. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<7> (Mcompar_v_re_cmp_ge0000_cy<7>)
  1329. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<8> (Mcompar_v_re_cmp_ge0000_cy<8>)
  1330. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<9> (Mcompar_v_re_cmp_ge0000_cy<9>)
  1331. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<10> (Mcompar_v_re_cmp_ge0000_cy<10>)
  1332. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<11> (Mcompar_v_re_cmp_ge0000_cy<11>)
  1333. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<12> (Mcompar_v_re_cmp_ge0000_cy<12>)
  1334. MUXCY:CI->O 1 0.023 0.000 Mcompar_v_re_cmp_ge0000_cy<13> (Mcompar_v_re_cmp_ge0000_cy<13>)
  1335. MUXCY:CI->O 1 0.222 0.412 Mcompar_v_re_cmp_ge0000_cy<14> (Mcompar_v_re_cmp_ge0000_cy<14>)
  1336. LUT5:I4->O 64 0.086 0.525 Mcompar_v_re_cmp_ge0000_cy<16>1 (v_re_cmp_ge0000)
  1337. LUT5:I4->O 1 0.086 0.000 v_re_mux0018<31>1 (v_re_mux0018<31>)
  1338. FD:D -0.022 re_31
  1339. ----------------------------------------
  1340. Total 35.949ns (16.407ns logic, 19.542ns route)
  1341. (45.6% logic, 54.4% route)
  1342.  
  1343. =========================================================================
  1344. Timing constraint: Default OFFSET IN BEFORE for Clock 'divisor<0>'
  1345. Total number of paths / destination ports: 5315 / 99
  1346. -------------------------------------------------------------------------
  1347. Offset: 6.483ns (Levels of Logic = 8)
  1348. Source: divisor<26> (PAD)
  1349. Destination: init_reg.quo_reg_0 (LATCH)
  1350. Destination Clock: divisor<0> falling
  1351.  
  1352. Data Path: divisor<26> to init_reg.quo_reg_0
  1353. Gate Net
  1354. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1355. ---------------------------------------- ------------
  1356. IBUF:I->O 51 0.694 1.012 divisor_26_IBUF (divisor_26_IBUF)
  1357. LUT6:I0->O 15 0.086 0.665 init_reg_re_reg_mux0031<25>11 (N125)
  1358. LUT5:I2->O 16 0.086 0.888 init_reg_re_reg_mux0031<19>11 (N83)
  1359. LUT6:I1->O 1 0.086 0.412 init_reg_re_reg_or0001_SW0 (N977)
  1360. LUT6:I5->O 227 0.086 0.801 init_reg_re_reg_or0001 (init_reg_re_reg_or0001)
  1361. LUT4:I0->O 4 0.086 0.914 init_reg_quo_reg_mux0031<0>51 (N656)
  1362. LUT6:I0->O 3 0.086 0.496 init_reg_quo_reg_mux0031<1>311 (init_reg_quo_reg_mux0031<1>311)
  1363. LUT6:I4->O 1 0.086 0.000 init_reg_quo_reg_mux0031<1>318 (init_reg_quo_reg_mux0031<1>)
  1364. LDCP:D -0.066 init_reg.quo_reg_1
  1365. ----------------------------------------
  1366. Total 6.483ns (1.296ns logic, 5.187ns route)
  1367. (20.0% logic, 80.0% route)
  1368.  
  1369. =========================================================================
  1370. Timing constraint: Default OFFSET OUT AFTER for Clock 'mclk1'
  1371. Total number of paths / destination ports: 64 / 64
  1372. -------------------------------------------------------------------------
  1373. Offset: 2.826ns (Levels of Logic = 1)
  1374. Source: quo_31 (FF)
  1375. Destination: quo<31> (PAD)
  1376. Source Clock: mclk1 rising
  1377.  
  1378. Data Path: quo_31 to quo<31>
  1379. Gate Net
  1380. Cell:in->out fanout Delay Delay Logical Name (Net Name)
  1381. ---------------------------------------- ------------
  1382. FD:C->Q 1 0.396 0.286 quo_31 (quo_31)
  1383. OBUF:I->O 2.144 quo_31_OBUF (quo<31>)
  1384. ----------------------------------------
  1385. Total 2.826ns (2.540ns logic, 0.286ns route)
  1386. (89.9% logic, 10.1% route)
  1387.  
  1388. =========================================================================
  1389.  
  1390.  
  1391. Total REAL time to Xst completion: 5742.00 secs
  1392. Total CPU time to Xst completion: 5706.66 secs
  1393.  
  1394. -->
  1395.  
  1396.  
  1397. Total memory usage is 761768 kilobytes
  1398.  
  1399. Number of errors : 0 ( 0 filtered)
  1400. Number of warnings : 88 ( 0 filtered)
  1401. Number of infos : 2 ( 0 filtered)
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