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Mikestriken

Registry_File

Apr 7th, 2023 (edited)
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VHDL 2.06 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.NUMERIC_STD.ALL;
  4.  
  5. entity registry_file is
  6.     port (
  7.         register_address_1     : in std_logic_vector(4 downto 0);
  8.         register_address_2     : in std_logic_vector(4 downto 0);
  9.         register_write_address : in std_logic_vector(4 downto 0);
  10.         register_write_data    : in std_logic_vector(31 downto 0);
  11.         RegWrite               : in std_logic;
  12.        
  13.         register_output_1  : out std_logic_vector(31 downto 0);
  14.         register_output_2  : out std_logic_vector(31 downto 0)
  15.        
  16.         --debug_write_output : out std_logic_vector(31 downto 0)
  17.     );
  18. end entity registry_file;
  19.  
  20. architecture dataflow of registry_file is
  21.     -- Registry Array
  22.     type register_array is array (0 to 31) of std_logic_vector(31 downto 0);
  23.     signal registers: register_array := (others => (others => '0'));
  24.    
  25.     -- Address to Integer Conversion, REMOVED DUE TO OUT OF BOUNDS SIMULAITON BUG
  26.     --signal Read_1_Address, Read_2_Address, Write_Address : integer := 0;
  27. begin
  28.     -- Debug Outputs
  29.     --debug_write_output <= registers(to_integer(unsigned(register_write_address)));
  30.  
  31.     -- Address to Integer Conversion, REMOVED DUE TO OUT OF BOUNDS SIMULAITON BUG
  32.     --Read_1_Address <= to_integer(unsigned(register_address_1));
  33.     --Read_2_Address <= to_integer(unsigned(register_address_2));
  34.     --Write_Address <= to_integer(unsigned(register_write_address));
  35.  
  36.     -- Read Outputs
  37.     --register_output_1 <= registers(Read_1_Address);
  38.     --register_output_2 <= registers(Read_2_Address);
  39.     register_output_1 <= registers(to_integer(unsigned(register_address_1)));
  40.     register_output_2 <= registers(to_integer(unsigned(register_address_2)));
  41.        
  42.     -- Register Write Logic
  43.     registers(to_integer(unsigned(register_write_address))) <= register_write_data when (RegWrite = '1') and (to_integer(unsigned(register_write_address)) <= 30) and (to_integer(unsigned(register_write_address)) >= 0)
  44.                                                                else registers(to_integer(unsigned(register_write_address)));
  45.    
  46. end dataflow;
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