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- **** Spice Netlist for Cell 'readwhos' *****
- ************** Module readwhos **************
- xi0 b bb wl n2 n0 6T
- ****voltage source grounding*****
- v0 n2 gnd dc='0' ac='0'
- ****power supply to 6T*****
- vdd n0 n2 dc='5' ac='0'
- **pullup**
- m0 bb read n1 n1 PMOS4 l='400n' w='2000n' m='1'
- m1 b read n1 n1 PMOS4 l='400n' w='2000n' m='1'
- **power supply for pullup**
- vp n1 n2 dc='5' ac='0'
- **routing cap bit line**
- c0 gnd b 1280f
- **routing cap bitb line**
- c1 gnd bb 1280f
- **routing cap wordline**
- c2 gnd wl 2560f
- **jutction cap for bit**
- m2 b gnd gnd gnd NMOS4 l='400n' w='650n' m='127'
- **jutction cap for bitb**
- m3 bb gnd gnd gnd NMOS4 l='400n' w='650n' m='127'
- **bit line conditioning**
- m6 b write gnd gnd NMOS4 l='400n' w='1000n' m='1'
- **bitb line conditioning**
- m5 bb writeb gnd gnd NMOS4 l='400n' w='1000n' m='1'
- **wordline oxide cap**
- m4 gnd wl gnd gnd NMOS4 l='400n' w='650n' m='256'
- m8 gnd wl vdd vdd NMOS4 l='400n' w='650n' m='256'
- **wordline pulse voltage**
- vwl wl n2 dc=5 ac=0
- * pulse 0 5v 10ns 200ps 200ps 20ns 30ns
- **bit line conditioning pulse voltage**
- vwrite write gnd dc=0 ac=0
- * pulse 0 5v 40ns 200ps 200ps 20ns 120ns
- **bitb line conditioning pulse voltage**
- vwriteb writeb gnd dc=0 ac=0
- * pulse 0 5v 100ns 200ps 200ps 20ns 60ns
- **pullup conditioning pulse voltage**
- vread read n2 gnd dc=0 ac=0
- * pulse 0v 5v 10ns 200ps 200ps 20ns 30ns
- **vcvs as sense amplifier**
- e0 opread gnd b bb 1.0
- ************** Module 6T **************
- .include '../myLab/6T/6T0p9.sp'
- **************Model File***************
- **************Model File***************
- .include '../myLab/scn4m_subm/models/ff/nmos.sp'
- .include '../myLab/scn4m_subm/models/ff/pmos.sp'
- *****Condition set and variable declaration*****
- .temp -40
- .param vsupply=5
- .global gnd
- .nodeset V(xi0.n0)=5
- .dc vwl 0 5 0.1
- .control
- run
- plot b,bb
- plot wl
- plot xi0.n0,xi0.n1
- plot read
- plot write,writeb
- .endc
- .end
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