CPE212-[Lab8.1] q2

module ALU4Bit(y,o,a,b,ci,c);
    input [3:0]a;
    input [3:0]b;
    input [1:0]c;
    input ci;
    output [3:0]y;
    output o;
    wire [3:0]z;
    wire zor;
    reg x;

    ALU1Bit alu0(y[0],z[0],a[0],b[0],ci,c);
    ALU1Bit alu1(y[1],z[1],a[1],b[1],z[0],c);
    ALU1Bit alu2(y[2],z[2],a[2],b[2],z[1],c);
    ALU1Bit alu3(y[3],z[3],a[3],b[3],z[2],c);

    or or1(zor,z);
    Mux4to1 mux1(o,zor,x,x,z[3],c);

endmodule

module ALU1Bit(y,z,a,b,ci,c);
    input a,b,ci;
    input [1:0]c;
    output y,z;
    wire s,co;          //y0,0
    wire anda;          //y0,1
    wire nota;          //y1,0

    wire xorab;         //z1,1

    reg x;

    FullAdder fa1(s,co,a,b,ci);     //y0,0
    and and1(anda,a,b);         //y0,1
    not not1(nota,a);           //y1,0

    xor xor1(xorab,a,b);        //z1,1

    Mux4to1 mux1(y,s,anda,nota,1'b0,c);
    Mux4to1 mux2(z,co,x,x,xorab,c);

endmodule

module FullAdder(s,co,a,b,ci);
    input a,b,ci;
    output s,co;
    wire xorab,andaci,andbci;

    xor xor1(xorab,a,b);
    xor xor2(s,xorab,ci);

    and and1(andaci,xorab,ci);
    and and2(andbci,b,a);

    or or1(co,andaci,andbci);
endmodule

module Mux4to1(o,i1,i2,i3,i4,c);
    input i1,i2,i3,i4;
    input [1:0]c;
    output o;

    wire andi1,andi2,andi3,andi4;

    input [1:0]nc;

    not not1(nc[0],c[0]);
    not not2(nc[1],c[1]);

    and and1(andi1,i1,nc[1],nc[0]);
    and and2(andi2,i2,nc[1],c[0]);
    and and3(andi3,i3,c[1],nc[0]);
    and and4(andi4,i4,c[1],c[0]);

    or or1(o,andi1,andi2,andi3,andi4);
endmodule

module stimulus;
    reg ci;
    reg [3:0]a;
    reg [3:0]b;
    reg [1:0]c;
    wire [3:0]y;
    wire o;

    ALU4Bit alu4bit(y,o,a,b,ci,c);

    initial
        begin
            a = 1'b0;
            b = 1'b0;
            ci = 1'b0;
            c = 1'b0;
        end

    always #1 ci = ~ci;
    always #2 a[0] = ~a[0];
    always #4 a[1] = ~a[1];
    always #8 a[2] = ~a[2];
    always #16 a[3] = ~a[3];
    always #32 b[0] = ~b[0];
    always #64 b[1] = ~b[1];
    always #128 b[2] = ~b[2];
    always #256 b[3] = ~b[3];
    always #512 c[0] = ~c[0];
    always #1024 c[1] = ~c[1];

    initial #2047 $finish;

    initial
        $monitor($time,"\tc = %b\ta = %b\tb = %b\tci = %d\ty = %b\tz = %d",c,a,b,ci,y,o);

endmodule