Lab10 - Ej04 - FF 4 bits y su Testbench

module FF_4bits (input clk, en, reset, input [3:0] D, output reg [3:0] Q);

    always @ (posedge clk or posedge reset)
        if (reset)
            Q <= 4'b0;
        else if (en)
            Q <= D;

endmodule

module tb();

    reg clk, en, reset;
    reg [3:0] D;
    wire [3:0] Q;

    FF_4bits DUT(clk, en, reset, D, Q);

    initial begin
        $dumpfile("timing.vcd");
        $dumpvars(0, tb);
    end

    initial
        #100 $finish;

    always
        #5 clk = ~clk;

    initial begin
        clk = 0; en = 0; reset = 0; D = 4'b0001;
        #22
        reset = 1;
        #2
        reset = 0;
        #16
        en = 1;
        #10
        D = 4'b1100;
        #20
        D = 4'b1010;
    end

endmodule