module demux14(
    input logic i,
    input logic s0,
    input logic s1,
    output logic y0,
    output logic y1,
    output logic y2,
    output logic y3
    );
    assign y0=i&(~s0)&(~s1);
    assign y1=i&(~s0)&(s1);
    assign y2=i&(s0)&(~s1);
    assign y3=i&(s0)&(s1);
endmodule