vga.sv

`include "../Headers/vga.svh"
`include "../Headers/RZ-EazyFPGA_A2.2.svh"

module vga (

    input logic clk50MHz,   // Input clock
    input logic resetn,     // Global reset - active negative

    output logic hsync,
    output logic vsync,

    output logic red,
    output logic green,
    output logic blue,

    output logic `LEDS_UNPACKED_ARRAY_PINS_RNG led,

    output logic clk50MHz4check,
    output logic clk_pll4check

);

    assign clk50MHz4check = clk50MHz;

    logic `LEDS_PACKED_ARRAY_CNT_RNG led_cnt;
    always_ff @(posedge clk_pll4check)
        led_cnt <= !resetn ? '0 : led_cnt + 1'b1;

    assign led = led_cnt[`LEDS_PACKED_ARRAY_CNT_WDT-1:
                           `LEDS_PACKED_ARRAY_CNT_WDT-`LEDS_UNPACKED_ARRAY_PINS_WDT];

    logic clk25_175MHz,
          clk108MHz,
          clk;

    // Video Enables
    logic video_en,
          horizontal_en,
          vertical_en;

    // Color Signals
    logic red_signal,
          green_signal,
          blue_signal;

    // Sync Signals
    logic hsync_signal,
          vsync_signal;

    //Sync Counters
    logic `CNT_RNG h_cnt,
                   v_cnt;


    `ifdef VGA640X480

        vga_640x480_pll vga_640x480_pll_inst (

            .inclk0 ( clk50MHz      ),
            .c0     ( clk25_175MHz  )

        );

        assign clk = clk25_175MHz;
        assign hsync = ~hsync_signal;
        assign vsync = ~vsync_signal;

    `elsif VGA1280X1024

        vga_1280x1024_pll   vga_1280x1024_pll_inst (

            .inclk0 ( clk50MHz      ),
            .c0     ( clk108MHz     )

        );

        assign clk = clk108MHz;
        assign hsync = hsync_signal;
        assign vsync = vsync_signal;

    `else // defaulf - for test purposes

        assign clk = clk50MHz;
        assign hsync = 1'b1;
        assign vsync = 1'b0;

    `endif

    lcell lcell_inst (
        .in  ( clk           ),
        .out ( clk_pll4check )
   );

    assign video_en = horizontal_en & vertical_en;

    always_ff @(posedge clk) begin

        // -----------------  Horizontal Sync ---------------

        // Horizontal Counter
        h_cnt <= !resetn || h_cnt == `WHOLE_LINE_PXLS - 1 ? '0 : h_cnt + 1'b1;

        // Generate Horizontal Data

        `ifdef RGB

            // Rows Of Red
            if (v_cnt >= 0 && v_cnt < `FIRST_HORIZ_BORDER_PXLS) begin
                red_signal   <= 1'b1;
                green_signal <= 1'b0;
                blue_signal  <= 1'b0;
            end;

            // Rows Of Green
            if (v_cnt >= `FIRST_HORIZ_BORDER_PXLS && v_cnt < `SECOND_HORIZ_BORDER_PXLS) begin
                red_signal   <= 1'b0;
                green_signal <= 1'b1;
                blue_signal  <= 1'b0;
            end;

            // Rows Of Blue
            if (v_cnt >= `SECOND_HORIZ_BORDER_PXLS && v_cnt <= `VISIBLE_FRAME_PXLS) begin
                red_signal   <= 1'b0;
                green_signal <= 1'b0;
                blue_signal  <= 1'b1;
            end;

        `else

            red_signal   <= 1'b1;
            green_signal <= 1'b1;
            blue_signal  <= 1'b1;

        `endif

        // Generate Horizontal Sync
        hsync_signal <= h_cnt >= `HORIZ_SYNC_PRE_PXLS && h_cnt <= `HORIZ_SYNC_POST_PXLS;

        // -----------------  Vertical Sync ---------------

        // Reset Vertical Counter

        v_cnt <= !resetn ||
                 v_cnt == `VERT_FRAME_PXLS - 1'b1 &&
                 h_cnt == `WHOLE_LINE_PXLS - 1'b1 ? '0 :
                 h_cnt == `WHOLE_LINE_PXLS - 1'b1 ?
                 v_cnt + 1'b1 :
                 v_cnt;

        // Generate Vertical Sync
        vsync_signal <= v_cnt > `VERT_SYNC_PRE_PXLS && v_cnt < `VERT_SYNC_POST_PXLS;

        // Generate Horizontal Enable
        horizontal_en <= h_cnt < `VISIBLE_LINE_PXLS;

        // Generate Vertical Enable
        vertical_en <= v_cnt < `VISIBLE_FRAME_PXLS;

        // Assign Physical Signals To VGA
        red   <= red_signal   & video_en;
        green <= green_signal & video_en;
        blue  <= blue_signal  & video_en;

    end // always_ff @(posedge clk25_175MHz) begin

endmodule : vga