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TheRouletteBoi

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TheRouletteBoi
Jun 28th, 2018
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  1. <?xml version="1.0" encoding="utf-8" standalone="yes"?>
  2. <InstructionHelp>
  3.     <Instruction>
  4.         <Details
  5.            Name="Add"
  6.            Description="The sum (rA) + (rB) is placed into rD."
  7.            OtherRegs="* Condition Register (CR0 field)&#10;   Affected: LT, GT, EQ, SO                 (if Rc = '1')&#10;      Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see next bullet item).&#10; * XER&#10;   Affected: SO, OV                         (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  8.            Pseudocode="         rD = (rA) + (rB)"/>
  9.         <Mnemonic
  10.            Form="add rD,rA,rB"
  11.            Notes="Add."/>
  12.         <Mnemonic
  13.            Form="add. rD,rA,rB"
  14.            Notes="Add record."/>
  15.         <Mnemonic
  16.            Form="addo rD,rA,rB"
  17.            Notes="Add overflow."/>
  18.         <Mnemonic
  19.            Form="addo. rD,rA,rB"
  20.            Notes="Add overflow and record."/>
  21.     </Instruction>
  22.     <Instruction>
  23.         <Details
  24.            Name="Add Carrying"
  25.            Description="The sum (rA) + (rB) is placed into rD."
  26.            OtherRegs="* Condition Register (CR0 field)&#10;    Affected: LT, GT, EQ, SO               (if Rc = '1')&#10;      Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).&#10;  * XER&#10;    Affected: CA&#10;    Affected: SO, OV                          (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  27.            Pseudocode="         rD = (rA) + (rB)"/>
  28.         <Mnemonic
  29.            Form="addc rD,rA,rB"
  30.            Notes="Add carrying."/>
  31.         <Mnemonic
  32.            Form="addc. rD,rA,rB"
  33.            Notes="Add carrying and record."/>
  34.         <Mnemonic
  35.            Form="addco rD,rA,rB"
  36.            Notes="Add carrying and overflow."/>
  37.         <Mnemonic
  38.            Form="addco. rD,rA,rB"
  39.            Notes="Add carrying, overflow and record."/>
  40.     </Instruction>
  41.     <Instruction>
  42.         <Details
  43.            Name="Add Extended"
  44.            Description="The sum (rA) + (rB) + XER[CA] is placed into rD."
  45.            OtherRegs="* Condition Register (CR0 field)&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')&#10;      Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).&#10; * XER&#10;   Affected: CA&#10;   Affected: SO, OV                        (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  46.            Pseudocode="         rD = (rA) + (rB) + XER[CA]"/>
  47.         <Mnemonic
  48.            Form="adde rD,rA,rB"
  49.            Notes="Add extended."/>
  50.         <Mnemonic
  51.            Form="adde. rD,rA,rB"
  52.            Notes="Add extended and record."/>
  53.         <Mnemonic
  54.            Form="addeo rD,rA,rB"
  55.            Notes="Add extended and overflow."/>
  56.         <Mnemonic
  57.            Form="addeo. rD,rA,rB"
  58.            Notes="Add extended, overflow and record."/>
  59.     </Instruction>
  60.     <Instruction>
  61.         <Details
  62.            Name="Add Immediate"
  63.            Description="The sum (rA|0) + sign extended SIMM is placed into rD.&#10;&#10;Note: addi uses the value '0', not the contents of GPR0, if rA = '0'."
  64.            OtherRegs=""
  65.            Pseudocode="         if rA = 0 then &#10;           rD = EXTS(SIMM)&#10;         else &#10;           rD = rA + EXTS(SIMM)"/>
  66.         <Mnemonic
  67.            Form="addi rD,rA,SIMM"
  68.            Notes="Add sign-extended imm16."/>
  69.         <Mnemonic
  70.            Form="li rD,value"
  71.            Notes="Load immediate. Equivalent to: addi rD,0,value."/>
  72.         <Mnemonic
  73.            Form="la rD,disp(rA)"
  74.            Notes="Load address. Equivalent to: addi rD,rA,disp."/>
  75.         <Mnemonic
  76.            Form="subi rD,rA,value"
  77.            Notes="Subtract immediate. Equivalent to: addi rD,rA,-value."/>
  78.     </Instruction>
  79.     <Instruction>
  80.         <Details
  81.            Name="Add Immediate Carrying"
  82.            Description="The sum (rA) + SIMM is placed into rD."
  83.            OtherRegs="XER&#10;   Affected: CA&#10;      Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  84.            Pseudocode="         rD = (rA) + EXTS(SIMM)"/>
  85.         <Mnemonic
  86.            Form="addic rD,rA,SIMM"
  87.            Notes="Add sign-extended imm16 and carrying."/>
  88.         <Mnemonic
  89.            Form="subic rD,rA,value"
  90.            Notes="Subtract immediate, carring. Equivalent to: addic rD,rA,-value."/>
  91.     </Instruction>
  92.     <Instruction>
  93.         <Details
  94.            Name="Add Immediate Carrying and Record"
  95.            Description="The sum (rA) + SIMM is placed into rD."
  96.            OtherRegs="* Condition Register (CR0 field)&#10;    Affected: LT, GT, EQ, SO&#10;      Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).&#10;  * XER&#10;    Affected: CA&#10;      Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  97.            Pseudocode="         rD = (rA) + EXTS(SIMM)"/>
  98.         <Mnemonic
  99.            Form="addic. rD,rA,SIMM"
  100.            Notes="Add sign-extended imm16, carrying and record."/>
  101.         <Mnemonic
  102.            Form="subic. rD,rA,value"
  103.            Notes="Subtract immediate, carring and record. Equivalent to: addic. rD,rA,-value."/>
  104.     </Instruction>
  105.     <Instruction>
  106.         <Details
  107.            Name="Add Immediate Shifted"
  108.            Description="The sum (rA|0) + (SIMM || 0x0000) is placed into rD.&#10;&#10;Note: addis uses the value '0', not the contents of GPR0, if rA = '0'."
  109.            OtherRegs=""
  110.            Pseudocode="        if rA = 0 then &#10;          rD = EXTS(SIMM || (16)0)&#10;        else  &#10;          rD = (rA) + EXTS(SIMM || (16)0)"/>
  111.         <Mnemonic
  112.            Form="addis rD,rA,SIMM"
  113.            Notes="Add sign-extended imm16 shifted left by 16 bits."/>
  114.         <Mnemonic
  115.            Form="lis rD,value"
  116.            Notes="Load immediate shifted. Equivalent to: addis rD,0,value."/>
  117.         <Mnemonic
  118.            Form="subis rD,rA,value"
  119.            Notes="Subtract immediate shifted. Equivalent to: addis rD,rA,-value."/>
  120.     </Instruction>
  121.     <Instruction>
  122.         <Details
  123.            Name="Add to Minus One Extended"
  124.            Description="The sum (rA) + XER[CA] + 0xFFFF_FFFF_FFFF_FFFF is placed into rD."
  125.            OtherRegs="* Condition Register (CR0 field)&#10;    Affected: LT, GT, EQ, SO               (if Rc = '1')&#10;      Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).&#10;  * XER&#10;    Affected: CA&#10;    Affected: SO, OV                       (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  126.            Pseudocode="         rD = (rA) + XER[CA] - 1"/>
  127.         <Mnemonic
  128.            Form="addme rD,rA"
  129.            Notes="Add to minus one extended."/>
  130.         <Mnemonic
  131.            Form="addme. rD,rA"
  132.            Notes="Add to minus one extended and record."/>
  133.         <Mnemonic
  134.            Form="addmeo rD,rA"
  135.            Notes="Add to minus one extended and overflow."/>
  136.         <Mnemonic
  137.            Form="addmeo. rD,rA"
  138.            Notes="Add to minus one extended, overflow and record."/>
  139.     </Instruction>
  140.     <Instruction>
  141.         <Details
  142.            Name="Add to Zero Extended"
  143.            Description="The sum (rA) + XER[CA] is placed into rD."
  144.            OtherRegs="* Condition Register (CR0 field)&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')&#10;      Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).&#10; * XER&#10;   Affected: CA&#10;   Affected: SO, OV                        (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  145.            Pseudocode="         rD = (rA) + XER[CA]"/>
  146.         <Mnemonic
  147.            Form="addze rD,rA"
  148.            Notes="Add to zero extended."/>
  149.         <Mnemonic
  150.            Form="addze. rD,rA"
  151.            Notes="Add to zero extended and record."/>
  152.         <Mnemonic
  153.            Form="addzeo rD,rA"
  154.            Notes="Add to zero extended and overflow."/>
  155.         <Mnemonic
  156.            Form="addzeo. rD,rA"
  157.            Notes="Add to zero extended, overflow and record."/>
  158.     </Instruction>
  159.     <Instruction>
  160.         <Details
  161.            Name="AND"
  162.            Description="The contents of rS are ANDed with the contents of rB and the result is placed into rA."
  163.            OtherRegs="* Condition Register (CR0 field)&#10;    Affected: LT, GT, EQ, SO             (if Rc = '1')"
  164.            Pseudocode="         rA = (rS) &amp; (rB)"/>
  165.         <Mnemonic
  166.            Form="and rA,rS,rB"
  167.            Notes="AND."/>
  168.         <Mnemonic
  169.            Form="and. rA,rS,rB"
  170.            Notes="AND and record."/>
  171.     </Instruction>
  172.     <Instruction>
  173.         <Details
  174.            Name="AND with Complement"
  175.            Description="The contents of rS are ANDed with the one's complement of the contents of rB and the result is placed into rA."
  176.            OtherRegs="* Condition Register (CR0 field)&#10;   Affected: LT, GT, EQ, SO             (if Rc = '1')"
  177.            Pseudocode="        rA = (rS) + ! (rB)"/>
  178.         <Mnemonic
  179.            Form="andc rA,rS,rB"
  180.            Notes="AND with Complement."/>
  181.         <Mnemonic
  182.            Form="andc. rA,rS,rB"
  183.            Notes="AND with Complement and record."/>
  184.     </Instruction>
  185.     <Instruction>
  186.         <Details
  187.            Name="AND Immediate"
  188.            Description="The contents of rS are ANDed with 0x0000_0000_0000 || UIMM and the result is placed into rA."
  189.            OtherRegs="* Condition Register (CR0 field)&#10;    Affected: LT, GT, EQ, SO"
  190.            Pseudocode="         rA = (rS) &amp; ((48)0 || UIMM)"/>
  191.         <Mnemonic
  192.            Form="andi. rA,rS,UIMM"
  193.            Notes="AND imm16 and record."/>
  194.     </Instruction>
  195.     <Instruction>
  196.         <Details
  197.            Name="AND Immediate Shifted"
  198.            Description="The contents of rS are ANDed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA."
  199.            OtherRegs="* Condition Register (CR0 field)&#10;   Affected: LT, GT, EQ, SO"
  200.            Pseudocode="         rA = (rS) + ((32)0 || UIMM || (16)0)"/>
  201.         <Mnemonic
  202.            Form="andis. rA,rS,UIMM"
  203.            Notes="AND imm16 shifted left by 16 bits."/>
  204.     </Instruction>
  205.     <Instruction>
  206.         <Details
  207.            Name="Branch"
  208.            Description="target specifies the branch target address.&#10;&#10;If AA = '0', then the branch target address is the sum of LI || '00' sign-extended and the address of this instruction, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations.&#10;&#10;If AA = '1', then the branch target address is the value LI || '00' sign-extended, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations.&#10;&#10;If LK = '1', then the effective address of the instruction following the branch instruction is placed into the link register."
  209.            OtherRegs="Affected: Link Register (LR) (if LK = '1')"
  210.            Pseudocode="         if AA then &#10;           NIA =iea EXTS(LI || '00')&#10;         else &#10;           NIA =iea CIA + EXTS(LI || '00')&#10;         if LK then &#10;           LR =iea CIA + 4"/>
  211.         <Mnemonic
  212.            Form="b target"
  213.            Notes="Branch."/>
  214.         <Mnemonic
  215.            Form="ba target"
  216.            Notes="Branch to absolute address."/>
  217.         <Mnemonic
  218.            Form="bl target"
  219.            Notes="Branch and update link register."/>
  220.         <Mnemonic
  221.            Form="bla target"
  222.            Notes="Branch to absolute address and update link register."/>
  223.     </Instruction>
  224.     <Instruction>
  225.         <Details
  226.            Name="Branch Conditional"
  227.            Description="The BI field specifies the bit in the condition register (CR) to be used as the condition of the branch.  target specifies the branch target address.&#10;&#10;The BO field is encoded as described below. &#10;BO: Description&#10;0000z: Decrement the CTR, then branch if the decremented CTR[M-63] != '0' and CR[BI] = '0' (condition is false).&#10;0001z: Decrement the CTR, then branch if the decremented CTR[M-63] = '0' and CR[BI] = '0' (condition is false).&#10;001at: Branch if CR[BI] = 0 (false).&#10;0100z: Decrement the CTR, then branch if the decremented CTR[M-63] !='0' and CR[BI] = '1' (condition is true).&#10;0101z: Decrement the CTR, then branch if the decremented CTR[M-63] = '0' and CR[BI] = '1' (condition is true).&#10;011at: Branch if CR[BI] = '1' (condition is true).&#10;1a00t: Decrement the CTR, then branch if the decremented CTR[M-63] != '0'.&#10;1a01t: Decrement the CTR, then branch if the decremented CTR[M-63] = '0'.&#10;1z1zz: Branch always.&#10;&#10;The at field is encoded as described below.&#10;at: Hint&#10;00: No hint is given&#10;01: Reserved&#10;10: Branch is very likely not to be taken&#10;11: Branch is very likely to be taken&#10;&#10;If AA = '0', then the branch target address is the sum of BD || '00' sign-extended and the address of this instruction, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations.&#10;&#10;If AA = '1', the branch target address is the value BD || '00' sign-extended, with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations.&#10;&#10;If LK = '1', the effective address of the instruction following the branch instruction is placed into the link register."
  228.            OtherRegs="Count Register (CTR)            (if BO[2] = '0')&#10; * Link Register (LR)              (if LK = '1')"
  229.            Pseudocode="        if (64-bit implementation) &amp; (64-bit mode) then &#10;          m = 0&#10;        else &#10;          m = 32&#10;        if ! BO[2] then &#10;          CTR = CTR - 1&#10;        ctr_ok = BO[2] | ((CTR[m-63] != 0) + BO[3])&#10;        cond_ok = BO[0] | (CR[BI] = BO[1])&#10;        if ctr_ok &amp; cond_ok then&#10;          if AA then &#10;            NIA =iea EXTS(BD || '00')&#10;          else &#10;            NIA =iea CIA + EXTS(BD || '00')&#10;          if LK then &#10;            LR =iea CIA + 4"/>
  230.         <Mnemonic
  231.            Form="bc BO,BI,target"
  232.            Notes="Branch conditional."/>
  233.         <Mnemonic
  234.            Form="bca BO,BI,target"
  235.            Notes="Branch conditional to absolute address."/>
  236.         <Mnemonic
  237.            Form="bcl BO,BI,target"
  238.            Notes="Branch conditional and update link register."/>
  239.         <Mnemonic
  240.            Form="bcla BO,BI,target"
  241.            Notes="Branch conditional to absolute address and update link register."/>
  242.         <Mnemonic
  243.            Form="blt target"
  244.            Notes="Branch if less than. Equivalent to: bc 12,0,target."/>
  245.         <Mnemonic
  246.            Form="ble"
  247.            Notes="Branch if less than or equal."/>
  248.         <Mnemonic
  249.            Form="beq"
  250.            Notes="Branch if equal."/>
  251.         <Mnemonic
  252.            Form="bge"
  253.            Notes="Branch if greater than or equal."/>
  254.         <Mnemonic
  255.            Form="bgt"
  256.            Notes="Branch if greater than."/>
  257.         <Mnemonic
  258.            Form="bnl"
  259.            Notes="Branch if not less than."/>
  260.         <Mnemonic
  261.            Form="bne cr2,target"
  262.            Notes="Branch if not equal. Equivalent to: bc 4,10,target."/>
  263.         <Mnemonic
  264.            Form="bng"
  265.            Notes="Branch if not greater than."/>
  266.         <Mnemonic
  267.            Form="bso"
  268.            Notes="Branch if summary overflow."/>
  269.         <Mnemonic
  270.            Form="blta"
  271.            Notes="Branch to absolute address if less than."/>
  272.         <Mnemonic
  273.            Form="blea"
  274.            Notes="Branch to absolute address if less than or equal."/>
  275.         <Mnemonic
  276.            Form="beqa"
  277.            Notes="Branch to absolute address if equal."/>
  278.         <Mnemonic
  279.            Form="bgea"
  280.            Notes="Branch to absolute address if greater than or equal."/>
  281.         <Mnemonic
  282.            Form="bgta"
  283.            Notes="Branch to absolute address if greater than."/>
  284.         <Mnemonic
  285.            Form="bnla"
  286.            Notes="Branch to absolute address if not less than."/>
  287.         <Mnemonic
  288.            Form="bnea"
  289.            Notes="Branch to absolute address if not equal."/>
  290.         <Mnemonic
  291.            Form="bnga"
  292.            Notes="Branch to absolute address if not greater than."/>
  293.         <Mnemonic
  294.            Form="bsoa"
  295.            Notes="Branch to absolute address if summary overflow."/>
  296.         <Mnemonic
  297.            Form="bltl"
  298.            Notes="Branch if less than, and update link register."/>
  299.         <Mnemonic
  300.            Form="blel"
  301.            Notes="Branch if less than or equal, and update link register."/>
  302.         <Mnemonic
  303.            Form="beql"
  304.            Notes="Branch if equal, and update link register."/>
  305.         <Mnemonic
  306.            Form="bgel"
  307.            Notes="Branch if greater than or equal, and update link register."/>
  308.         <Mnemonic
  309.            Form="bgtl"
  310.            Notes="Branch if greater than, and update link register."/>
  311.         <Mnemonic
  312.            Form="bnll"
  313.            Notes="Branch if not less than, and update link register."/>
  314.         <Mnemonic
  315.            Form="bnel"
  316.            Notes="Branch if not equal, and update link register."/>
  317.         <Mnemonic
  318.            Form="bngl"
  319.            Notes="Branch if not greater than, and update link register."/>
  320.         <Mnemonic
  321.            Form="bsol"
  322.            Notes="Branch if summary overflow, and update link register."/>
  323.         <Mnemonic
  324.            Form="bltal"
  325.            Notes="Branch to absolute address if less than, and update link register."/>
  326.         <Mnemonic
  327.            Form="bleal"
  328.            Notes="Branch to absolute address if less than or equal, and update link register."/>
  329.         <Mnemonic
  330.            Form="beqal"
  331.            Notes="Branch to absolute address if equal, and update link register."/>
  332.         <Mnemonic
  333.            Form="bgeal"
  334.            Notes="Branch to absolute address if greater than or equal, and update link register."/>
  335.         <Mnemonic
  336.            Form="bgtal"
  337.            Notes="Branch to absolute address if greater than, and update link register."/>
  338.         <Mnemonic
  339.            Form="bnlal"
  340.            Notes="Branch to absolute address if not less than, and update link register."/>
  341.         <Mnemonic
  342.            Form="bneal"
  343.            Notes="Branch to absolute address if not equal, and update link register."/>
  344.         <Mnemonic
  345.            Form="bngal"
  346.            Notes="Branch to absolute address if not greater than, and update link register."/>
  347.         <Mnemonic
  348.            Form="bsoal"
  349.            Notes="Branch to absolute address if summary overflow, and update link register."/>
  350.         <Mnemonic
  351.            Form="bt"
  352.            Notes="Branch if condition true."/>
  353.         <Mnemonic
  354.            Form="bf"
  355.            Notes="Branch if condition false."/>
  356.         <Mnemonic
  357.            Form="bdnz"
  358.            Notes="Decrement CTR, branch if CTR non-zero."/>
  359.         <Mnemonic
  360.            Form="bdnzt"
  361.            Notes="Decrement CTR, branch if CTR non-zero AND condition true."/>
  362.         <Mnemonic
  363.            Form="bdnzf"
  364.            Notes="Decrement CTR, branch if CTR non-zero AND condition false."/>
  365.         <Mnemonic
  366.            Form="bdz"
  367.            Notes="Decrement CTR, branch if CTR zero."/>
  368.         <Mnemonic
  369.            Form="bdzt"
  370.            Notes="Decrement CTR, branch if CTR zero AND condition true."/>
  371.         <Mnemonic
  372.            Form="bdzf"
  373.            Notes="Decrement CTR, branch if CTR zero AND condition false."/>
  374.         <Mnemonic
  375.            Form="bta"
  376.            Notes="Branch to absolute address if condition true."/>
  377.         <Mnemonic
  378.            Form="bfa"
  379.            Notes="Branch to absolute address if condition false."/>
  380.         <Mnemonic
  381.            Form="bdnza"
  382.            Notes="Decrement CTR, branch to absolute address if CTR non-zero."/>
  383.         <Mnemonic
  384.            Form="bdnzta"
  385.            Notes="Decrement CTR, branch to absolute address if CTR non-zero AND condition true."/>
  386.         <Mnemonic
  387.            Form="bdnzfa"
  388.            Notes="Decrement CTR, branch to absolute address if CTR non-zero AND condition false."/>
  389.         <Mnemonic
  390.            Form="bdza"
  391.            Notes="Decrement CTR, branch to absolute address if CTR zero."/>
  392.         <Mnemonic
  393.            Form="bdzta"
  394.            Notes="Decrement CTR, branch to absolute address if CTR zero AND condition true."/>
  395.         <Mnemonic
  396.            Form="bdzfa"
  397.            Notes="Decrement CTR, branch to absolute address if CTR zero AND condition false."/>
  398.         <Mnemonic
  399.            Form="btl"
  400.            Notes="Branch if condition true, and update link register."/>
  401.         <Mnemonic
  402.            Form="bfl"
  403.            Notes="Branch if condition false, and update link register."/>
  404.         <Mnemonic
  405.            Form="bdnzl"
  406.            Notes="Decrement CTR, branch if CTR non-zero, and update link register."/>
  407.         <Mnemonic
  408.            Form="bdnztl"
  409.            Notes="Decrement CTR, branch if CTR non-zero AND condition true, and update link register."/>
  410.         <Mnemonic
  411.            Form="bdnzfl"
  412.            Notes="Decrement CTR, branch if CTR non-zero AND condition false, and update link register."/>
  413.         <Mnemonic
  414.            Form="bdzl"
  415.            Notes="Decrement CTR, branch if CTR zero, and update link register."/>
  416.         <Mnemonic
  417.            Form="bdztl"
  418.            Notes="Decrement CTR, branch if CTR zero AND condition true, and update link register."/>
  419.         <Mnemonic
  420.            Form="bdzfl"
  421.            Notes="Decrement CTR, branch if CTR zero AND condition false, and update link register."/>
  422.         <Mnemonic
  423.            Form="btla"
  424.            Notes="Branch to absolute address if condition true, and update link register."/>
  425.         <Mnemonic
  426.            Form="bfla"
  427.            Notes="Branch to absolute address if condition false, and update link register."/>
  428.         <Mnemonic
  429.            Form="bdnzla"
  430.            Notes="Decrement CTR, branch to absolute address if CTR non-zero, and update link register."/>
  431.         <Mnemonic
  432.            Form="bdnztla"
  433.            Notes="Decrement CTR, branch to absolute address if CTR non-zero AND condition true, and update link register."/>
  434.         <Mnemonic
  435.            Form="bdnzfla"
  436.            Notes="Decrement CTR, branch to absolute address if CTR non-zero AND condition false, and update link register."/>
  437.         <Mnemonic
  438.            Form="bdzla"
  439.            Notes="Decrement CTR, branch to absolute address if CTR zero, and update link register."/>
  440.         <Mnemonic
  441.            Form="bdztla"
  442.            Notes="Decrement CTR, branch to absolute address if CTR zero AND condition true, and update link register."/>
  443.         <Mnemonic
  444.            Form="bdzfla"
  445.            Notes="Decrement CTR, branch to absolute address if CTR zero AND condition false, and update link register."/>
  446.     </Instruction>
  447.     <Instruction>
  448.         <Details
  449.            Name="Branch Conditional to Count Register"
  450.            Description="The BI field specifies the bit in the condition register to be used as the condition of the branch. The branch target address is CTR[0-61] || '00', with the high-order 32 bits of the branch target address cleared in 32-bit mode of 64-bit implementations. &#10;&#10;The BO field is encoded as described below. &#10;BO: Description&#10;0000z: Decrement the CTR, then branch if the decremented CTR[M-63] != '0' and CR[BI] = '0' (condition is false).&#10;0001z: Decrement the CTR, then branch if the decremented CTR[M-63] = '0' and CR[BI] = '0' (condition is false).&#10;001at: Branch if CR[BI] = 0 (false).&#10;0100z: Decrement the CTR, then branch if the decremented CTR[M-63] !='0' and CR[BI] = '1' (condition is true).&#10;0101z: Decrement the CTR, then branch if the decremented CTR[M-63] = '0' and CR[BI] = '1' (condition is true).&#10;011at: Branch if CR[BI] = '1' (condition is true).&#10;1a00t: Decrement the CTR, then branch if the decremented CTR[M-63] != '0'.&#10;1a01t: Decrement the CTR, then branch if the decremented CTR[M-63] = '0'.&#10;1z1zz: Branch always.&#10;&#10;The at field is encoded as described below.&#10;at: Hint&#10;00: No hint is given&#10;01: Reserved&#10;10: Branch is very likely not to be taken&#10;11: Branch is very likely to be taken&#10;&#10;The BH field is used as described below.&#10;BH: Hint&#10;00: bclr[l] - The instruction is a subroutine return. &#10;00: bcctr[l] - The instruction is not a subroutine return; the target address is likely to be the same as the target address used the preceding time the branch was taken.&#10;01: bclr[l] - The instruction is not a subroutine return; the target address is likely to be the same as the target address used the preceding time the branch was taken.&#10;01: bcctr[l] - Reserved.&#10;10: Reserved.&#10;11: bclr[l] and bcctr[l] - The target address is not predictable.&#10;&#10;If LK = '1' the effective address of the instruction following the branch instruction is placed into the link register.&#10;&#10;If the 'decrement and test CTR' option is specified (BO[2] = '0'), the instruction form is invalid."
  451.            OtherRegs="Link Register (LR)             (if LK = '1')"
  452.            Pseudocode="         cond_ok = BO[0] | (CR[BI] = BO[1])&#10;         if cond_ok then&#10;           NIA =iea CTR[0-61] || '00'&#10;           if LK then &#10;             LR =iea CIA + 4"/>
  453.         <Mnemonic
  454.            Form="bcctr BO,BI,BH"
  455.            Notes="Branch conditional to count register."/>
  456.         <Mnemonic
  457.            Form="bcctrl BO,BI,BH"
  458.            Notes="Branch conditional to count register and update link register."/>
  459.         <Mnemonic
  460.            Form="bltctr"
  461.            Notes="Branch to count register if less than. Equivalent to: bcctr 12,0,0."/>
  462.         <Mnemonic
  463.            Form="blectr"
  464.            Notes="Branch to count register if less than or equal."/>
  465.         <Mnemonic
  466.            Form="beqctr"
  467.            Notes="Branch to count register if equal."/>
  468.         <Mnemonic
  469.            Form="bgectr"
  470.            Notes="Branch to count register if greater than or equal."/>
  471.         <Mnemonic
  472.            Form="bgtctr"
  473.            Notes="Branch to count register if greater than."/>
  474.         <Mnemonic
  475.            Form="bnlctr"
  476.            Notes="Branch to count register if not less than."/>
  477.         <Mnemonic
  478.            Form="bnectr cr2"
  479.            Notes="Branch to count register if not equal. Equivalent to: bcctr 4,10,0."/>
  480.         <Mnemonic
  481.            Form="bngctr"
  482.            Notes="Branch to count register if not greater than."/>
  483.         <Mnemonic
  484.            Form="bsoctr"
  485.            Notes="Branch to count register if summary overflow."/>
  486.         <Mnemonic
  487.            Form="bltctrl"
  488.            Notes="Branch to count register if less than, and update link register."/>
  489.         <Mnemonic
  490.            Form="blectrl"
  491.            Notes="Branch to count register if less than or equal, and update link register."/>
  492.         <Mnemonic
  493.            Form="beqctrl"
  494.            Notes="Branch to count register if equal, and update link register."/>
  495.         <Mnemonic
  496.            Form="bgectrl"
  497.            Notes="Branch to count register if greater than or equal, and update link register."/>
  498.         <Mnemonic
  499.            Form="bgtctrl"
  500.            Notes="Branch to count register if greater than, and update link register."/>
  501.         <Mnemonic
  502.            Form="bnlctrl"
  503.            Notes="Branch to count register if not less than, and update link register."/>
  504.         <Mnemonic
  505.            Form="bnectrl"
  506.            Notes="Branch to count register if not equal, and update link register."/>
  507.         <Mnemonic
  508.            Form="bngctrl"
  509.            Notes="Branch to count register if not greater than, and update link register."/>
  510.         <Mnemonic
  511.            Form="bsoctrl"
  512.            Notes="Branch to count register if summary overflow, and update link register."/>
  513.         <Mnemonic
  514.            Form="bctr"
  515.            Notes="Branch unconditionally to count register."/>
  516.         <Mnemonic
  517.            Form="btctr"
  518.            Notes="Branch to count register if condition true."/>
  519.         <Mnemonic
  520.            Form="bfctr"
  521.            Notes="Branch to count register if condition false."/>
  522.     </Instruction>
  523.     <Instruction>
  524.         <Details
  525.            Name="Branch Conditional to Link Register"
  526.            Description="The BI field specifies the bit in the condition register to be used as the condition of the branch. The BO field is encoded as described below. The branch target address is LR[0-61] || '00', with the high-order 32 bits of the branch target address cleared in 32-bit mode of a 64-bit implementations. &#10;&#10;The BO field is encoded as described below. &#10;BO: Description&#10;0000z: Decrement the CTR, then branch if the decremented CTR[M-63] != '0' and CR[BI] = '0' (condition is false).&#10;0001z: Decrement the CTR, then branch if the decremented CTR[M-63] = '0' and CR[BI] = '0' (condition is false).&#10;001at: Branch if CR[BI] = 0 (false).&#10;0100z: Decrement the CTR, then branch if the decremented CTR[M-63] !='0' and CR[BI] = '1' (condition is true).&#10;0101z: Decrement the CTR, then branch if the decremented CTR[M-63] = '0' and CR[BI] = '1' (condition is true).&#10;011at: Branch if CR[BI] = '1' (condition is true).&#10;1a00t: Decrement the CTR, then branch if the decremented CTR[M-63] != '0'.&#10;1a01t: Decrement the CTR, then branch if the decremented CTR[M-63] = '0'.&#10;1z1zz: Branch always.&#10;&#10;The at field is encoded as described below.&#10;at: Hint&#10;00: No hint is given&#10;01: Reserved&#10;10: Branch is very likely not to be taken&#10;11: Branch is very likely to be taken&#10;&#10;The BH field is used as described below.&#10;BH: Hint&#10;00: bclr[l] - The instruction is a subroutine return. &#10;00: bcctr[l] - The instruction is not a subroutine return; the target address is likely to be the same as the target address used the preceding time the branch was taken.&#10;01: bclr[l] - The instruction is not a subroutine return; the target address is likely to be the same as the target address used the preceding time the branch was taken.&#10;01: bcctr[l] - Reserved.&#10;10: Reserved.&#10;11: bclr[l] and bcctr[l] - The target address is not predictable.&#10;&#10;If LK = '1', then the effective address of the instruction following the branch instruction is placed into the link register."
  527.            OtherRegs="Count Register (CTR)           (if BO[2] = '0')&#10; * Link Register (LR)             (if LK = '1')"
  528.            Pseudocode="         if (64-bit implementation) &amp; (64-bit mode) then &#10;           m = 0&#10;         else &#10;           m = 32&#10;         if ! BO[2] then &#10;           CTR = CTR - 1&#10;         ctr_ok = BO[2] | ((CTR[m-63] != 0) + BO[3])&#10;         cond_ok = BO[0] | (CR[BI] = BO[1])&#10;         if ctr_ok &amp; cond_ok then&#10;           NIA =iea LR[0-61] || '00'&#10;           if LK then &#10;             LR =iea CIA + 4"/>
  529.         <Mnemonic
  530.            Form="bclr BO,BI,BH"
  531.            Notes="Branch conditional to link register."/>
  532.         <Mnemonic
  533.            Form="bclrl BO,BI,BH"
  534.            Notes="Branch conditional to link register and update link register."/>
  535.         <Mnemonic
  536.            Form="bltlr"
  537.            Notes="Equivalent to: bclr 12,0,0."/>
  538.         <Mnemonic
  539.            Form="bnelr cr2"
  540.            Notes="Equivalent to: bclr 4,10,0."/>
  541.         <Mnemonic
  542.            Form="bltlr"
  543.            Notes="Branch to link register if less than."/>
  544.         <Mnemonic
  545.            Form="blelr"
  546.            Notes="Branch to link register if less than or equal."/>
  547.         <Mnemonic
  548.            Form="beqlr"
  549.            Notes="Branch to link register if equal."/>
  550.         <Mnemonic
  551.            Form="bgelr"
  552.            Notes="Branch to link register if greater than or equal."/>
  553.         <Mnemonic
  554.            Form="bgtlr"
  555.            Notes="Branch to link register if greater than."/>
  556.         <Mnemonic
  557.            Form="bnllr"
  558.            Notes="Branch to link register if not less than."/>
  559.         <Mnemonic
  560.            Form="bnelr"
  561.            Notes="Branch to link register if not equal."/>
  562.         <Mnemonic
  563.            Form="bnglr"
  564.            Notes="Branch to link register if not greater than."/>
  565.         <Mnemonic
  566.            Form="bsolr"
  567.            Notes="Branch to link register if summary overflow."/>
  568.         <Mnemonic
  569.            Form="bltlrl"
  570.            Notes="Branch to link register if less than, and update link register."/>
  571.         <Mnemonic
  572.            Form="blelrl"
  573.            Notes="Branch to link register if less than or equal, and update link register."/>
  574.         <Mnemonic
  575.            Form="beqlrl"
  576.            Notes="Branch to link register if equal, and update link register."/>
  577.         <Mnemonic
  578.            Form="bgelrl"
  579.            Notes="Branch to link register if greater than or equal, and update link register."/>
  580.         <Mnemonic
  581.            Form="bgtlrl"
  582.            Notes="Branch to link register if greater than, and update link register."/>
  583.         <Mnemonic
  584.            Form="bnllrl"
  585.            Notes="Branch to link register if not less than, and update link register."/>
  586.         <Mnemonic
  587.            Form="bnelrl"
  588.            Notes="Branch to link register if not equal, and update link register."/>
  589.         <Mnemonic
  590.            Form="bnglrl"
  591.            Notes="Branch to link register if not greater than, and update link register."/>
  592.         <Mnemonic
  593.            Form="bsolrl"
  594.            Notes="Branch to link register if summary overflow, and update link register."/>
  595.         <Mnemonic
  596.            Form="blr"
  597.            Notes="Branch unconditionally to link register."/>
  598.         <Mnemonic
  599.            Form="btlr"
  600.            Notes="Branch to link register if condition true."/>
  601.         <Mnemonic
  602.            Form="bflr"
  603.            Notes="Branch to link register if condition false."/>
  604.         <Mnemonic
  605.            Form="bdnzlr"
  606.            Notes="Decrement CTR, branch to link register if CTR non-zero."/>
  607.         <Mnemonic
  608.            Form="bdnztlr"
  609.            Notes="Decrement CTR, branch to link register if CTR non-zero AND condition true."/>
  610.         <Mnemonic
  611.            Form="bdnzflr"
  612.            Notes="Decrement CTR, branch to link register if CTR non-zero AND condition false."/>
  613.         <Mnemonic
  614.            Form="bdzlr"
  615.            Notes="Decrement CTR, branch to link register if CTR zero."/>
  616.         <Mnemonic
  617.            Form="bdztlr"
  618.            Notes="Decrement CTR, branch to link register if CTR zero AND condition true."/>
  619.         <Mnemonic
  620.            Form="bdzflr"
  621.            Notes="Decrement CTR, branch to link register if CTR zero AND condition false."/>
  622.         <Mnemonic
  623.            Form="blrl"
  624.            Notes="Branch unconditionally to link register, and update link register."/>
  625.         <Mnemonic
  626.            Form="btlrl"
  627.            Notes="Branch to link register if condition true, and update link register."/>
  628.         <Mnemonic
  629.            Form="bflrl"
  630.            Notes="Branch to link register if condition false, and update link register."/>
  631.         <Mnemonic
  632.            Form="bdnzlrl"
  633.            Notes="Decrement CTR, branch to link register if CTR non-zero, and update link register."/>
  634.         <Mnemonic
  635.            Form="bdnztlrl"
  636.            Notes="Decrement CTR, branch to link register if CTR non-zero AND condition true, and update link register."/>
  637.         <Mnemonic
  638.            Form="bdnzflrl"
  639.            Notes="Decrement CTR, branch to link register if CTR non-zero AND condition false, and update link register."/>
  640.         <Mnemonic
  641.            Form="bdzlrl"
  642.            Notes="Decrement CTR, branch to link register if CTR zero, and update link register."/>
  643.         <Mnemonic
  644.            Form="bdztlrl"
  645.            Notes="Decrement CTR, branch to link register if CTR zero AND condition true, and update link register."/>
  646.         <Mnemonic
  647.            Form="bdzflrl"
  648.            Notes="Decrement CTR, branch to link register if CTR zero AND condition false, and update link register."/>
  649.     </Instruction>
  650.     <Instruction>
  651.         <Details
  652.            Name="Compare"
  653.            Description="The contents of rA (or the low-order 32 bits of rA if L = '0') are compared with the contents of rB (or the low-order 32 bits of rB if L = '0'), treating the operands as signed integers. The result of the comparison is placed into CR field crfD."
  654.            OtherRegs="* Condition Register (CR field specified by operand crfD)&#10;    Affected: LT, GT, EQ, SO"
  655.            Pseudocode="         if L = '0' then &#10;           a = EXTS(rA[32-63])&#10;           b = EXTS(rB[32-63])&#10;         else&#10;           a = (rA)&#10;           b = (rB)&#10;         if a &lt; b then &#10;           c = '100'&#10;         else if a &gt; b then &#10;           c = '010'&#10;         else&#10;           c = '001'&#10;         CR[(4 * crfD) - (4 * crfD + 3)] = c || XER[SO]"/>
  656.         <Mnemonic
  657.            Form="cmp crfD,L,rA,rB"
  658.            Notes="Compare."/>
  659.         <Mnemonic
  660.            Form="cmpd rA,rB"
  661.            Notes="Compare doubleword. Equivalent to: cmp 0,1,rA,rB."/>
  662.         <Mnemonic
  663.            Form="cmpw cr3,rA,rB"
  664.            Notes="Compare word. Equivalent to: cmp 3,0,rA,rB."/>
  665.     </Instruction>
  666.     <Instruction>
  667.         <Details
  668.            Name="Compare Immediate"
  669.            Description="The contents of rA (or the low-order 32 bits of rA sign-extended to 64 bits if L = '0') are compared with the sign-extended value of the SIMM field, treating the operands as signed integers. The result of the comparison is placed into CR field crfD."
  670.            OtherRegs="* Condition Register (CR field specified by operand crfD)&#10;   Affected: LT, GT, EQ, SO"
  671.            Pseudocode="        if L = '0' then &#10;          a = EXTS(rA[32-63])&#10;        else&#10;          a = (rA)&#10;        if a &lt; EXTS(SIMM) then &#10;          c = '100'&#10;        else if a &gt; EXTS(SIMM) then &#10;          c = '010'&#10;        else &#10;          c = '001'&#10;        CR[(4 * crfD) - (4 * crfD + 3)] = c || XER[SO]"/>
  672.         <Mnemonic
  673.            Form="cmpi crfD,L,rA,SIMM"
  674.            Notes="Compare with sign-extended imm16."/>
  675.         <Mnemonic
  676.            Form="cmpdi rA,value"
  677.            Notes="Compare doubleword immediate. Equivalent to: cmpi 0,1,rA,value."/>
  678.         <Mnemonic
  679.            Form="cmpwi cr3,rA,value"
  680.            Notes="Compare word immediate. Equivalent to: cmpi 3,0,rA,value."/>
  681.     </Instruction>
  682.     <Instruction>
  683.         <Details
  684.            Name="Compare Logical"
  685.            Description="The contents of rA (or the low-order 32 bits of rA if L = '0') are compared with the contents of rB (or the low-order 32 bits of rB if L = '0'), treating the operands as unsigned integers. The result of the comparison is placed into CR field crfD."
  686.            OtherRegs="* Condition Register (CR field specified by operand crfD)&#10;    Affected: LT, GT, EQ, SO"
  687.            Pseudocode="         if L = 0 then &#10;            a = (32)0 || rA[32-63]&#10;            b = (32)0 || rB[32-63]&#10;         else &#10;            a = (rA)&#10;            b = (rB)&#10;         if a &lt;U b then &#10;            c = '100'&#10;         else if a &gt;U b then &#10;            c = '010'&#10;         else&#10;            c = '001'&#10;         CR[(4 * crfD) - (4 * crfD + 3)] = c || XER[SO]"/>
  688.         <Mnemonic
  689.            Form="cmpl crfD,L,rA,rB"
  690.            Notes="Compare logical."/>
  691.         <Mnemonic
  692.            Form="cmpld rA,rB"
  693.            Notes="Compare logical doubleword. Equivalent to: cmpl 0,1,rA,rB."/>
  694.         <Mnemonic
  695.            Form="cmplw cr3,rA,rB"
  696.            Notes="Compare logical word. Equivalent to: cmpl 3,0,rA,rB."/>
  697.     </Instruction>
  698.     <Instruction>
  699.         <Details
  700.            Name="Compare Logical Immediate"
  701.            Description="The contents of rA (or the low-order 32 bits of rA zero-extended to 64-bits if L = '0') are compared with 0x0000_0000_0000 || UIMM, treating the operands as unsigned integers. The result of the comparison is placed into CR field crfD."
  702.            OtherRegs="* Condition Register (CR field specified by operand crfD)&#10;   Affected: LT, GT, EQ, SO"
  703.            Pseudocode="        if L = 0 then &#10;          a = (32)0 || rA[32-63]&#10;        else &#10;          a = (rA)&#10;        if a &lt;U ((48)0 || UIMM) then &#10;          c = '100'&#10;        else if a &gt;U ((48)0 || UIMM) then &#10;          c = '010'&#10;        else &#10;          c = '00'1&#10;        CR[(4 * crfD) - (4 * crfD + 3)] = c || XER[SO]"/>
  704.         <Mnemonic
  705.            Form="cmpli crfD,L,rA,UIMM"
  706.            Notes="Compare logical with imm16."/>
  707.         <Mnemonic
  708.            Form="cmpldi rA,value"
  709.            Notes="Compare logical doubleword immediate. Equivalent to: cmpli 0,1,rA,value."/>
  710.         <Mnemonic
  711.            Form="cmplwi cr3,rA,value"
  712.            Notes="Compare logical word immediate. Equivalent to: cmpli 3,0,rA,value."/>
  713.     </Instruction>
  714.     <Instruction>
  715.         <Details
  716.            Name="Count Leading Zeros Doubleword"
  717.            Description="A count of the number of consecutive zero bits starting at bit [0] of register rS is placed into rA. This number ranges from 0 to 64, inclusive."
  718.            OtherRegs="* Condition Register (CR0 field)&#10;    Affected: LT, GT, EQ, SO                (Rc = '1')&#10;     Note: If Rc = '1', then LT is cleared in the CR0 field."
  719.            Pseudocode="          n =0&#10;          do while n &lt; 64&#10;            if rS[n] = 1 then &#10;              leave&#10;            n = n + 1&#10;          rA = n"/>
  720.         <Mnemonic
  721.            Form="cntlzd rA,rS"
  722.            Notes="Count leading zeros doubleword."/>
  723.         <Mnemonic
  724.            Form="cntlzd. rA,rS"
  725.            Notes="Count leading zeros doubleword and record."/>
  726.     </Instruction>
  727.     <Instruction>
  728.         <Details
  729.            Name="Count Leading Zeros Word"
  730.            Description="A count of the number of consecutive zero bits starting at bit [32] of rS is placed into rA. This number ranges from 0 to 32, inclusive."
  731.            OtherRegs="* Condition Register (CR0 field)&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')&#10;    Note: If Rc = '1', then LT is cleared in the CR0 field."
  732.            Pseudocode="        n = 32&#10;        do while n &lt; 64&#10;          if rS[n] = 1 then &#10;            leave&#10;          n = n+1&#10;        rA = n - 32"/>
  733.         <Mnemonic
  734.            Form="cntlzw rA,rS"
  735.            Notes="Count leading zeros word."/>
  736.         <Mnemonic
  737.            Form="cntlzw. rA,rS"
  738.            Notes="Count leading zeros word and record."/>
  739.     </Instruction>
  740.     <Instruction>
  741.         <Details
  742.            Name="Condition Register AND"
  743.            Description="The bit in the condition register specified by crbA is ANDed with the bit in the condition register specified by crbB. The result is placed into the condition register bit specified by crbD."
  744.            OtherRegs="* Condition Register&#10;    Affected: Bit specified by operand crbD"
  745.            Pseudocode="         CR[crbD] = CR[crbA] &amp; CR[crbB]"/>
  746.         <Mnemonic
  747.            Form="crand crbD,crbA,crbB"
  748.            Notes="AND condition register bits."/>
  749.     </Instruction>
  750.     <Instruction>
  751.         <Details
  752.            Name="Condition Register AND with Complement"
  753.            Description="The bit in the condition register specified by crbA is ANDed with the complement of the bit in the condition register specified by crbB and the result is placed into the condition register bit specified by crbD."
  754.            OtherRegs="* Condition Register&#10;   Affected: Bit specified by operand crbD"
  755.            Pseudocode="        CR[crbD] = CR[crbA] &amp; ! CR[crbB]"/>
  756.         <Mnemonic
  757.            Form="crandc crbD,crbA,crbB"
  758.            Notes="AND with complement the condition register bits."/>
  759.     </Instruction>
  760.     <Instruction>
  761.         <Details
  762.            Name="Condition Register Equivalent"
  763.            Description="The bit in the condition register specified by crbA is XORed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD."
  764.            OtherRegs="* Condition Register&#10;    Affected: Bit specified by operand crbD"
  765.            Pseudocode="         CR[crbD] = CR[crbA] = CR[crbB]"/>
  766.         <Mnemonic
  767.            Form="creqv crbD,crbA,crbB"
  768.            Notes="XOR and complement the condition register bits."/>
  769.         <Mnemonic
  770.            Form="crset crbD"
  771.            Notes="Condition register set. Equivalent to: creqv crbD,crbD,crbD."/>
  772.     </Instruction>
  773.     <Instruction>
  774.         <Details
  775.            Name="Condition Register NAND"
  776.            Description="The bit in the condition register specified by crbA is ANDed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD."
  777.            OtherRegs="* Condition Register&#10;   Affected: Bit specified by operand crbD"
  778.            Pseudocode="        CR[crbD] = ! (CR[crbA] &amp; CR[crbB])"/>
  779.         <Mnemonic
  780.            Form="crnand crbD,crbA,crbB"
  781.            Notes="AND and complement the condition register bits."/>
  782.     </Instruction>
  783.     <Instruction>
  784.         <Details
  785.            Name="Condition Register NOR"
  786.            Description="The bit in the condition register specified by crbA is ORed with the bit in the condition register specified by crbB and the complemented result is placed into the condition register bit specified by crbD."
  787.            OtherRegs="* Condition Register&#10;    Affected: Bit specified by operand crbD"
  788.            Pseudocode="         CR[crbD] = ! (CR[crbA] | CR[crbB])"/>
  789.         <Mnemonic
  790.            Form="crnor crbD,crbA,crbB"
  791.            Notes="OR and complement the condition register bits."/>
  792.         <Mnemonic
  793.            Form="crnot crbD,crbA"
  794.            Notes="Condition register not. Equivalent to: crnor crbD,crbA,crbA."/>
  795.     </Instruction>
  796.     <Instruction>
  797.         <Details
  798.            Name="Condition Register OR"
  799.            Description="The bit in the condition register specified by crbA is ORed with the bit in the condition register specified by crbB. The result is placed into the condition register bit specified by crbD."
  800.            OtherRegs="* Condition Register&#10;   Affected: Bit specified by operand crbD"
  801.            Pseudocode="        CR[crbD] = CR[crbA] | CR[crbB]"/>
  802.         <Mnemonic
  803.            Form="cror crbD,crbA,crbB"
  804.            Notes="OR the condition register bits."/>
  805.         <Mnemonic
  806.            Form="crmove crbD,crbA"
  807.            Notes="Condition register move. Equivalent to: cror crbD,crbA,crbA."/>
  808.     </Instruction>
  809.     <Instruction>
  810.         <Details
  811.            Name="Condition Register OR with Complement"
  812.            Description="The bit in the condition register specified by crbA is ORed with the complement of the condition register bit specified by crbB and the result is placed into the condition register bit specified by crbD."
  813.            OtherRegs="* Condition Register&#10;    Affected: Bit specified by operand crbD"
  814.            Pseudocode="         CR[crbD] = CR[crbA] | ! CR[crbB]"/>
  815.         <Mnemonic
  816.            Form="crorc crbD,crbA,crbB"
  817.            Notes="OR with complement the condition register bits."/>
  818.     </Instruction>
  819.     <Instruction>
  820.         <Details
  821.            Name="Condition Register XOR"
  822.            Description="The bit in the condition register specified by crbA is XORed with the bit in the condition register specified by crbB and the result is placed into the condition register specified by crbD."
  823.            OtherRegs="* Condition Register&#10;   Affected: Bit specified by crbD"
  824.            Pseudocode="        CR[crbD] = CR[crbA] + CR[crbB]"/>
  825.         <Mnemonic
  826.            Form="crxor crbD,crbA,crbB"
  827.            Notes="XOR the condition register bits."/>
  828.         <Mnemonic
  829.            Form="crclr crbD"
  830.            Notes="Condition register clear. Equivalent to: crxor crbD,crbD,crbD."/>
  831.     </Instruction>
  832.     <Instruction>
  833.         <Details
  834.            Name="Data Cache Block Flush"
  835.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The action taken depends on the memory mode associated with the block containing the byte addressed and the state of that block. If the system is a multiprocessor implementation, then the block is marked coherency-required, the processor will, if necessary, send an address-only broadcast to other processors. The broadcast of the dcbf instruction causes another processor to copy the block to memory, if it has dirty data, and then invalidate the block from the cache. The list below describes the action taken for the two states of the memory coherency attribute (M-bit).&#10; * Coherency required (requires the use of address broadcast)&#10;   - Unmodified block-Invalidates copies of the block in the data caches of all processors.&#10;   - Modified block-Copies the block to memory and invalidates it. (In whatever processor it resides, there should be only one modified block).&#10;   - Absent block-If modified copies of the block are in the data caches of other processors, it causes them to be copied to memory and invalidated in those data caches. If unmodified copies are in the data caches of other processors, it causes those copies to be invalidated in those data caches.&#10; * Coherency not required (no address broadcast required)&#10;   - Unmodified block-Invalidates the block in the processor's data cache.&#10;   - Modified block-Copies the block to memory. Invalidates the block in the processor's data cache.&#10;   - Absent block-No action is taken.&#10;&#10;The function of this instruction is independent of the write-through, write-back and caching-inhibited/allowed modes of the block containing the byte addressed by the effective address.&#10;&#10;This instruction is treated as a load from the addressed byte with respect to address translation and memory protection. It is also treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur."
  836.            OtherRegs=""
  837.            Pseudocode=""/>
  838.         <Mnemonic
  839.            Form="dcbf rA,rB"
  840.            Notes="The data block at the effective address is flushed to memory and invalidated in the processor's data cache."/>
  841.     </Instruction>
  842.     <Instruction>
  843.         <Details
  844.            Name="Data Cache Block Store"
  845.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The dcbst instruction executes as follows:&#10; * Coherency required (requires the use of address broadcast)&#10;   - Unmodified block-No action in this processor. Signals other processors to copy to memory any modified cache block.&#10;   - Modified block-The cache block is written to memory. (Only one processor should have a copy of a modified block)&#10;   - Absent block -No action in this processor. If a modified copy of the block is in the data cache of another processor, the cache line is written to memory.&#10; * Coherency not required (no address broadcast required)&#10;   - Unmodified block-No action is taken.&#10;   - Modified block- The cache block is written to memory.&#10;   - Absent block-No action is taken.&#10;&#10;Note: For modified cache blocks written to memory the architecture does not stipulate whether or not to clear the modified state of the cache block. It is left up to the processor designer to determine the final state of the cache block. Either modified or valid is logically correct.&#10;&#10;The function of this instruction is independent of the write-through and caching-inhibited/allowed modes of the block containing the byte addressed by EA.&#10;&#10;The processor treats this instruction as a load from the addressed byte with respect to address translation and memory protection, except that the system data storage error handler is not invoked, and the reference and change recording does not need to be done."
  846.            OtherRegs=""
  847.            Pseudocode=""/>
  848.         <Mnemonic
  849.            Form="dcbst rA,rB"
  850.            Notes="The data block at the effective address is written to memory."/>
  851.     </Instruction>
  852.     <Instruction>
  853.         <Details
  854.            Name="Data Cache Block Touch"
  855.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;This instruction is a hint that performance will possibly be improved if the block containing the byte addressed by EA and the TH field is fetched into the data cache, because the program will probably soon load from the addressed byte. If the block is caching-inhibited, the hint is ignored and the instruction is treated as a no-op. Executing dcbt does not cause the system alignment error handler to be invoked.&#10;&#10;The encodings of the TH field are as follows:&#10;TH: Description&#10;00: The memory location is the block containing the byte addressed by the effective address.&#10;01: The memory locations are the block containing the byte addressed by the effective address and sequentially following blocks.  (i.e., the blocks containing the bytes addressed by EA + n * block_size, where n = 0, 1, 2, ...).&#10;10: Reserved. The TH field should not be set to '10', because the value may be assigned a meaning in some future version of the architecture.&#10;11  The memory locations are the block containing the byte addressed by the effective address and sequentially preceding blocks. (i.e., the blocks containing the bytes addressed by EA - n * block_size, where n = 0, 1, 2, ...).&#10;&#10;The actions (if any) taken by the processor in response to the hint are not considered to be 'caused by' or'associated with' the dcbt instruction (for example, dcbt is considered not to cause any data accesses). No means are provided by which software can synchronize these actions with the execution of the instruction stream. For example, these actions are not ordered by memory barriers.&#10;&#10;This instruction is treated as a load from the addressed byte with respect to address translation, memory protection, and reference and change recording except that referenced and changed bit recording may not occur. Additionally, no exception occurs in the case of a translation fault or protection violation.&#10;&#10;The program uses the dcbt instruction to request a cache block fetch before it is actually needed by the program. The program can later execute load instructions to put data into registers. However, the processor is not obliged to load the addressed block into the data cache.&#10;&#10;Note: This instruction is defined architecturally to perform the same functions as the dcbtst instruction. Both are defined in order to allow implementations to differentiate the bus actions when fetching into the cache for the case of a load and for a store.&#10;&#10;In response to the hint provided by dcbt, the processor may prefetch the specified block into the data cache, or take other actions that reduce the latency of subsequent load or store instructions that refer to the block.&#10;&#10;Note: Earlier implementations that do not support the optional version of dcbt ignore the TH field (i.e., treat it as if it were set to '00'), and do not necessarily ignore the hint provided by dcbt if the specified block is in storage that is Guarded and not Caching Inhibited. Therefore a dcbt instruction with TH[1] = '1' should not specify an EA in such memory if the program is to be run on such implementations.&#10;&#10;Earlier implementations do not necessarily ignore the hint provided by dcbt if the specified block is in memory that is Guarded and not Caching Inhibited. Therefore a dcbt instruction should not specify an EA in such memory if the program is to be run on such implementations."
  856.            OtherRegs=""
  857.            Pseudocode=""/>
  858.         <Mnemonic
  859.            Form="dcbt rA,rB,TH"
  860.            Notes="Hint for the data block at the effective address to be loaded into the processor's cache because the program will soon load from the address."/>
  861.     </Instruction>
  862.     <Instruction>
  863.         <Details
  864.            Name="Data Cache Block Touch for Store"
  865.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;This instruction is a hint that performance will possibly be improved if the block containing the byte addressed by EA is fetched into the data cache, because the program will probably soon store from the addressed byte. If the block is caching-inhibited or guarded, the hint is ignored and the instruction is treated as a no-op. Executing dcbtst does not cause the system alignment error handler to be invoked.&#10;&#10;This instruction is treated as a load from the addressed byte with respect to address translation, memory protection, and reference and change recording except that referenced and changed bit recording may not occur. Additionally, no exception occurs in the case of a translation fault or protection violation.&#10;&#10;The program uses dcbtst to request a cache block fetch to potentially improve performance for a subsequent store to that EA, as that store would then be to a cached location. However, the processor is not obliged to load the addressed block into the data cache.&#10;&#10;Note: This instruction is defined architecturally to perform the same functions as the dcbt instruction. Both are defined in order to allow implementations to differentiate the bus actions when fetching into the cache for the case of a load and for a store.&#10;&#10;Note: In response to the hint provided by dcbtst, the processor may prefetch the specified block into the data cache, or take other actions that reduce the latency of subsequent load or store instructions that refer to the block.&#10;&#10;Earlier implementations do not necessarily ignore the hint provided by dcbtst if the specified block is in memory that is Guarded and not Caching Inhibited. Therefore a dcbtst instruction should not specify an EA in such memory if the program is to be run on such implementations."
  866.            OtherRegs=""
  867.            Pseudocode=""/>
  868.         <Mnemonic
  869.            Form="dcbtst rA,rB"
  870.            Notes="Hint for the data block at the effective address to be loaded into the processor's cache because the program will soon store to the address."/>
  871.     </Instruction>
  872.     <Instruction>
  873.         <Details
  874.            Name="Data Cache Block Clear to Zero"
  875.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;All bytes in the block containing the byte addressed by the effective address are set to zero.&#10;&#10;This instruction is treated as a store to the addressed byte with respect to address translation, memory protection, referenced and changed recording. It is also treated as a store with respect to the ordering enforced by eieio and the ordering enforced by the combination of caching-inhibited and guarded attributes for a page (or block).&#10;&#10;The dcbz instruction executes as follows:&#10; * dcbz does not cause the block to exist in the data cache if the block is in memory that is caching inhibited.&#10; * For memory that is neither write-through required nor caching inhibited, dcbz provides an efficient means of setting blocks of memory to zero. It can be used to initialize large areas of such memory, in a manner that is likely to consume less memory bandwidth than an equivalent sequence of store instructions.&#10; * If the page containing the byte addressed by EA is in caching-inhibited or write-through mode, either all bytes of main memory that correspond to the addressed cache block are cleared or the alignment exception handler is invoked. The exception handler can then clear all bytes in main memory that correspond to the addressed cache block.&#10; * For memory that is either write-through required or caching inhibited, dcbz is likely to take significantly longer to execute than an equivalent sequence of store instructions."
  876.            OtherRegs=""
  877.            Pseudocode="        if A = 0 then &#10;          b = 0&#10;        else &#10;          b = (RA)&#10;        EA = b + (RB)&#10;        n = block size (bytes)&#10;        m = log2(n)&#10;        ea = EA[(0-63)-m || (m)0)&#10;        MEM(ea, n) = (n)0x00"/>
  878.         <Mnemonic
  879.            Form="dcbz rA,rB"
  880.            Notes="The data block at the effective address is set to zero."/>
  881.     </Instruction>
  882.     <Instruction>
  883.         <Details
  884.            Name="Divide Doubleword"
  885.            Description="The 64-bit dividend is the contents of rA. The 64-bit divisor is the contents of rB. The 64-bit quotient is placed into rD. The remainder is not supplied as a result.&#10;&#10;Both the operands and the quotient are interpreted as signed integers. The quotient is the unique signed integer that satisfies the equation-dividend = (quotient * divisor) + r-where 0 &lt;= r &lt; |divisor| if the dividend is non-negative, and -|divisor| &lt; r &lt;= 0 if the dividend is negative.&#10;&#10;If an attempt is made to perform the divisions-0x8000_0000_0000_0000 / -1 or &lt;anything&gt; / 0-the contents of rD are undefined, as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = '1'). In this case, if OE = '1' then OV is set."
  886.            OtherRegs="* Condition Register (CR0 field):&#10;    Affected: LT, GT, EQ, SO              (if Rc = '1')&#10;  * XER:&#10;    Affected: SO, OV                      (if OE = '1')&#10;    Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 64-bit&#10;    result."
  887.            Pseudocode="         dividend[0-63] = (rA)&#10;         divisor[0-63] = (rB)&#10;         rD = dividend / divisor"/>
  888.         <Mnemonic
  889.            Form="divd rD,rA,rB"
  890.            Notes="Divide doubleword."/>
  891.         <Mnemonic
  892.            Form="divd. rD,rA,rB"
  893.            Notes="Divide doubleword and record."/>
  894.         <Mnemonic
  895.            Form="divdo rD,rA,rB"
  896.            Notes="Divide doubleword and overflow."/>
  897.         <Mnemonic
  898.            Form="divdo. rD,rA,rB"
  899.            Notes="Divide doubleword overflow and record."/>
  900.     </Instruction>
  901.     <Instruction>
  902.         <Details
  903.            Name="Divide Doubleword Unsigned"
  904.            Description="The 64-bit dividend is the contents of rA. The 64-bit divisor is the contents of rB. The 64-bit quotient of the dividend and divisor is placed into rD. The remainder is not supplied as a result.&#10;&#10;Both the operands and the quotient are interpreted as unsigned integers, except that if Rc is set to 1, then the first three bits of CR0 field are set by signed comparison of the result to zero. The quotient is the unique unsigned integer that satisfies the equation-dividend = (quotient * divisor) + r-where 0 &lt;= r &lt; divisor.&#10;&#10;If an attempt is made to perform the division-&lt;anything&gt; / 0-the contents of rD are undefined as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = '1'). In this case, if OE = '1' then OV is set."
  905.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                  (if Rc = '1')&#10; * XER:&#10;   Affected: SO, OV                        (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 64-bit&#10;      result."
  906.            Pseudocode="         dividend[0-63] = (rA)&#10;         divisor[0-63] = (rB)&#10;         rD = dividend / divisor"/>
  907.         <Mnemonic
  908.            Form="divdu rD,rA,rB"
  909.            Notes="Divide doubleword unsigned."/>
  910.         <Mnemonic
  911.            Form="divdu. rD,rA,rB"
  912.            Notes="Divide doubleword unsigned and record."/>
  913.         <Mnemonic
  914.            Form="divduo rD,rA,rB"
  915.            Notes="Divide doubleword unsigned and overflow."/>
  916.         <Mnemonic
  917.            Form="divduo. rD,rA,rB"
  918.            Notes="Divide doubleword unsigned overflow and record."/>
  919.     </Instruction>
  920.     <Instruction>
  921.         <Details
  922.            Name="Divide Word"
  923.            Description="The 64-bit dividend is the sign-extended value of the contents of the low-order 32 bits of rA. The 64-bit divisor is the sign-extended value of the contents of the low-order 32 bits of rB. The 64-bit quotient is formed. The low-order 32 bits of the 64-bit quotient are placed into the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are undefined. The remainder is not supplied as a result.&#10;&#10;Both the operands and the quotient are interpreted as signed integers. The quotient is the unique signed integer that satisfies the equation-dividend = (quotient * divisor) + r where 0 &lt;= r &lt; |divisor| (if the dividend is non-negative), and -|divisor| &lt; r &lt;= 0 (if the dividend is negative).&#10;&#10;If an attempt is made to perform either of the divisions- 0x8000_0000 / -1 or &lt;anything&gt; / 0, then the contents of rD are undefined, as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = 1). In this case, if OE = '1' then OV is set."
  924.            OtherRegs="* Condition Register (CR0 field):&#10;    Affected: LT, GT, EQ, SO               (if Rc = '1')&#10;    LT, GT, EQ undefined                   (if Rc = '1' and 64-bit mode)&#10;  * XER:&#10;    Affected: SO, OV                      (if OE = '1')&#10;    Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the low-&#10;    order 32-bit result."
  925.            Pseudocode="         dividend[0-63] = EXTS(rA[32-63])&#10;         divisor[0-63] = EXTS(rB[32-63])&#10;         rD[32-63] = dividend / divisor&#10;         rD[0-31] = undefined"/>
  926.         <Mnemonic
  927.            Form="divw rD,rA,rB"
  928.            Notes="Divide word."/>
  929.         <Mnemonic
  930.            Form="divw. rD,rA,rB"
  931.            Notes="Divide word and record."/>
  932.         <Mnemonic
  933.            Form="divwo rD,rA,rB"
  934.            Notes="Divide word and overflow."/>
  935.         <Mnemonic
  936.            Form="divwo. rD,rA,rB"
  937.            Notes="Divide word overflow and record."/>
  938.     </Instruction>
  939.     <Instruction>
  940.         <Details
  941.            Name="Divide Word Unsigned"
  942.            Description="The 64-bit dividend is the zero-extended value of the contents of the low-order 32 bits of rA. The 64-bit divisor is the zero-extended value the contents of the low-order 32 bits of rB. A 64-bit quotient is formed. The low-order 32 bits of the 64-bit quotient are placed into the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are undefined. The remainder is not supplied as a result.&#10;&#10;Both operands and the quotient are interpreted as unsigned integers, except that if Rc = '1' the first three bits of CR0 field are set by signed comparison of the result to zero. The quotient is the unique unsigned integer that satisfies the equation-dividend = (quotient * divisor) + r (where 0 &lt;= r &lt; divisor). If an attempt is made to perform the division-&lt;anything&gt; / 0-then the contents of rD are undefined as are the contents of the LT, GT, and EQ bits of the CR0 field (if Rc = '1'). In this case, if OE = '1' then OV is set."
  943.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')&#10;   LT, GT, EQ undefined                    (if Rc = '1' and 64-bit mode)&#10; * XER:&#10;   Affected: SO, OV                        (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the low-&#10;      order 32-bit result."
  944.            Pseudocode="         dividend[0-63] = (32)0 || rA[32-63]&#10;         divisor[0-63] = (32)0 || rB[32-63]&#10;         rD[32-63] = dividend / divisor&#10;         rD[0-31] = undefined"/>
  945.         <Mnemonic
  946.            Form="divwu rD,rA,rB"
  947.            Notes="Divide word unsigned."/>
  948.         <Mnemonic
  949.            Form="divwu. rD,rA,rB"
  950.            Notes="Divide word unsigned and record."/>
  951.         <Mnemonic
  952.            Form="divwuo rD,rA,rB"
  953.            Notes="Divide word unsigned and overflow."/>
  954.         <Mnemonic
  955.            Form="divwuo. rD,rA,rB"
  956.            Notes="Divide word unsigned overflow and record."/>
  957.     </Instruction>
  958.     <Instruction>
  959.         <Details
  960.            Name="External Control In Word Indexed"
  961.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The eciwx instruction and the EAR register can be very efficient when mapping special devices such as graphics devices that use addresses as pointers.&#10;&#10;A load word request for the physical address (referred to as real address in the architecture specification) corresponding to EA is sent to the device identified by EAR[RID], bypassing the cache. The word returned by the device is placed in the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are cleared.&#10;&#10;EAR[E] must be '1'. If it is not, a DSI exception is generated.&#10;&#10;EA must be a multiple of four. If it is not, one of the following occurs:&#10; * A system alignment exception is generated.&#10; * A DSI exception is generated (possible only if EAR[E] = '0').&#10; * The results are boundedly undefined.&#10;&#10;If this instruction is executed when MSR[DR] = '0' (real addressing mode), the results are boundedly undefined. This instruction is treated as a load from the addressed byte with respect to address translation, memory protection, referenced and changed bit recording, and the ordering performed by eieio. This instruction is optional in the PowerPC Architecture."
  962.            OtherRegs=""
  963.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else &#10;           b= (rA)&#10;         EA = b + (rB)&#10;         paddr = address translation of EA&#10;         send load word request for paddr to device identified by EAR[RID]&#10;         rD = (32)0 || word from device"/>
  964.         <Mnemonic
  965.            Form="eciwx rD,rA,rB"
  966.            Notes="External control in word. Effective address is register indexed."/>
  967.     </Instruction>
  968.     <Instruction>
  969.         <Details
  970.            Name="External Control Out Word Indexed"
  971.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The ecowx instruction and the EAR register can be very efficient when mapping special devices such as graphics devices that use addresses as pointers.&#10;&#10;A store word request for the physical address corresponding to EA and the contents of the low-order 32 bits of rS are sent to the device identified by EAR[RID], bypassing the cache.&#10;&#10;EAR[E] must be '1', if it is not, a DSI exception is generated. EA must be a multiple of four. If it is not, one of the following occurs:&#10; * A system alignment exception is generated.&#10; * A DSI exception is generated (possible only if EAR[E] = '0').&#10; * The results are boundedly undefined.&#10;&#10;If this instruction is executed when MSR[DR] = '0' (real addressing mode), the results are boundedly undefined. This instruction is treated as a store from the addressed byte with respect to address translation, memory protection, and referenced and changed bit recording, and the ordering performed by eieio.&#10;&#10;Note: Software synchronization is required in order to ensure that the data access is performed in program order with respect to data accesses caused by other store or ecowx instructions, even though the addressed byte is assumed to be caching-inhibited and guarded. This instruction is optional in the PowerPC Architecture."
  972.            OtherRegs=""
  973.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else &#10;           b = (rA)&#10;         EA = b + (rB)&#10;         paddr = address translation of EA&#10;         send store word request for paddr to device identified by EAR[RID]&#10;         send rS[32-63] to device"/>
  974.         <Mnemonic
  975.            Form="ecowx rS,rA,rB"
  976.            Notes="External control out word. Effective address is register indexed."/>
  977.     </Instruction>
  978.     <Instruction>
  979.         <Details
  980.            Name="Enforce In-Order Execution of I/O"
  981.            Description="The eieio instruction provides an ordering function for the effects of load and store instructions executed by a processor. These loads and stores are divided into two sets, which are ordered separately. The memory accesses caused by a dcbz or an ecowx instruction are ordered like a store, and the memory access caused by an eciwx instruction is ordered as a load. The two sets follow:&#10;&#10; 1. Loads and stores to memory that is both caching-inhibited and guarded, and stores to memory that is write-through required.&#10;    - The eieio instruction controls the order in which the accesses are performed in main memory. It ensures that all applicable memory accesses caused by instructions preceding the eieio instruction have completed with respect to main memory before any applicable memory accesses caused by instructions following the eieio instruction access main memory. It acts like a barrier that flows through the memory queues and to main memory, preventing the reordering of memory accesses across the barrier. No ordering is performed for dcbz if the instruction causes the system alignment error handler to be invoked.&#10;    - All accesses in this set are ordered as a single set-that is, there is not one order for loads and stores to caching-inhibited and guarded memory and another order for stores to write-through required memory.&#10;    - The ordering done by the memory barrier for accesses in this set is not cumulative.&#10;&#10; 2. Stores to memory that have all of the following attributes-caching-allowed, write-through not required, and memory-coherency required.&#10;    - The eieio instruction controls the order in which the accesses are performed with respect to coherent memory. It ensures that all applicable stores caused by instructions preceding the eieio instruction have completed with respect to coherent memory before any applicable stores caused by instructions following the eieio instruction complete with respect to coherent memory.&#10;&#10;The eieio instruction may complete before memory accesses caused by instructions preceding the eieio instruction have been performed with respect to main memory or coherent memory as appropriate.&#10;&#10;The eieio instruction is intended for use in managing shared data structures, in accessing memory-mapped I/O, and in preventing load/store combining operations in main memory. For the first use, the shared data structure and the lock that protects it must be altered only by stores that are in the same set (1 or 2; see previous discussion). For the second use, eieio can be thought of as placing a barrier into the stream of memory accesses issued by a processor, such that any given memory access appears to be on the same side of the barrier to both the processor and the I/O device.&#10;&#10;Because the processor performs store operations in order to memory that is designated as both caching-inhibited and guarded, the eieio instruction is needed for such memory only when loads must be ordered with respect to stores or with respect to other loads.&#10;&#10;Note: The eieio instruction does not connect hardware considerations to it such as multiprocessor implementations that send an eieio address-only broadcast (useful in some designs). For example, if a design has an external buffer that re-orders loads and stores for better bus efficiency, the eieio broadcast signals to that buffer that previous loads/stores (marked caching-inhibited, guarded, or write-through required) must complete before any following loads/stores (marked caching-inhibited, guarded, or write-through required)."
  982.            OtherRegs=""
  983.            Pseudocode=""/>
  984.         <Mnemonic
  985.            Form="eieio"
  986.            Notes="Provides an ordering function for load and store instructions. The effects are non-cumulative."/>
  987.     </Instruction>
  988.     <Instruction>
  989.         <Details
  990.            Name="Equivalent"
  991.            Description="The contents of rS are XORed with the contents of rB and the complemented result is placed into rA."
  992.            OtherRegs="* Condition Register (CR0 field):&#10;    Affected: LT, GT, EQ, SO             (if Rc = '1')"
  993.            Pseudocode="         rA = (rS) = (rB)"/>
  994.         <Mnemonic
  995.            Form="eqv rA,rS,rB"
  996.            Notes="Equivalent is logically the same as XOR and complement."/>
  997.         <Mnemonic
  998.            Form="eqv. rA,rS,rB"
  999.            Notes="Equivalent and record. Equivalent is logically the same as XOR and complement."/>
  1000.     </Instruction>
  1001.     <Instruction>
  1002.         <Details
  1003.            Name="Extend Sign Byte"
  1004.            Description="The contents of the low-order eight bits of rS [56-63] are placed into the low-order eight bits of rA . Bit [56] of rS is placed into bits rA."
  1005.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                  (if Rc = '1')"
  1006.            Pseudocode="         S = rS[56]&#10;         rA[56-63] = rS[56-63]&#10;         rA[0-55] = (56)S"/>
  1007.         <Mnemonic
  1008.            Form="extsb rA,rS"
  1009.            Notes="Sign-extend byte."/>
  1010.         <Mnemonic
  1011.            Form="extsb. rA,rS"
  1012.            Notes="Sign-extend byte and record."/>
  1013.     </Instruction>
  1014.     <Instruction>
  1015.         <Details
  1016.            Name="Extend Sign Halfword"
  1017.            Description="The contents of the low-order 16 bits of rS are placed into the low-order 16 bits of rA. Bit [48] of rS is placed into the remaining bits of rA."
  1018.            OtherRegs="* Condition Register (CR0 field):&#10;    Affected: LT, GT, EQ, SO                  (if Rc = '1')"
  1019.            Pseudocode="         S = rS[48]&#10;         rA[48-63] = rS[48-63]&#10;         rA[0-47] = (48)S"/>
  1020.         <Mnemonic
  1021.            Form="extsh rA,rS"
  1022.            Notes="Sign-extend halfword."/>
  1023.         <Mnemonic
  1024.            Form="extsh. rA,rS"
  1025.            Notes="Sign-extend halfward and record."/>
  1026.     </Instruction>
  1027.     <Instruction>
  1028.         <Details
  1029.            Name="Extend Sign Word"
  1030.            Description="The contents of the low-order 32 bits of rS are placed into the low-order 32 bits of rA. Bit [32] of rS is placed into the high-order 32 bits of rA."
  1031.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO               (if Rc = '1')"
  1032.            Pseudocode="         S = rS[32]&#10;         rA[32-63] = rS[32-63]&#10;         rA[0-31] = (32)S"/>
  1033.         <Mnemonic
  1034.            Form="extsw rA,rS"
  1035.            Notes="Sign-extend word."/>
  1036.         <Mnemonic
  1037.            Form="extsw. rA,rS"
  1038.            Notes="Sign-extend word and record."/>
  1039.     </Instruction>
  1040.     <Instruction>
  1041.         <Details
  1042.            Name="Floating Absolute Value"
  1043.            Description="The contents of frB with bit [0] cleared are placed into frD.&#10;&#10;Note: The fabs instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may be altered by fabs. This instruction does not alter the FPSCR."
  1044.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                (if Rc = '1')"
  1045.            Pseudocode=""/>
  1046.         <Mnemonic
  1047.            Form="fabs frD,frB"
  1048.            Notes="Floating point absolute value."/>
  1049.         <Mnemonic
  1050.            Form="fabs. frD,frB"
  1051.            Notes="Floating point absolute value and record."/>
  1052.     </Instruction>
  1053.     <Instruction>
  1054.         <Details
  1055.            Name="Floating Add"
  1056.            Description="The floating-point operand in frA is added to the floating-point operand in frB.&#10;&#10;If the most- significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;Floating-point addition is based on exponent comparison and addition of the two significands. The exponents of the two operands are compared, and the significand accompanying the smaller exponent is shifted right, with its exponent increased by one for each bit shifted, until the two exponents are equal. The two significands are then added or subtracted as appropriate, depending on the signs of the operands. All 53 bits in the significand, as well as all three guard bits (G, R, and X) enter into the computation.&#10;&#10;If a carry occurs, the sum's significand is shifted right one bit position and the exponent is increased by one. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1057.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, XX,VXSNAN, VXISI"
  1058.            Pseudocode=""/>
  1059.         <Mnemonic
  1060.            Form="fadd frD,frA,frB"
  1061.            Notes="Floating point add ."/>
  1062.         <Mnemonic
  1063.            Form="fadd. frD,frA,frB"
  1064.            Notes="Floating point add and record."/>
  1065.     </Instruction>
  1066.     <Instruction>
  1067.         <Details
  1068.            Name="Floating Add Single"
  1069.            Description="The floating-point operand in frA is added to the floating-point operand in frB. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to the single-precision undercontrol of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;Floating-point addition is based on exponent comparison and addition of the two significands. The exponents of the two operands are compared, and the significand accompanying the smaller exponent is shifted right, with its exponent increased by one for each bit shifted, until the two exponents are equal. The two significands are then added or subtracted as appropriate, depending on the signs of the operands. All 53 bits in the significand, as well as all three guard bits (G, R, and X) enter into the computation.&#10;&#10;If a carry occurs, the sum's significand is shifted right one bit position and the exponent is increased by one. FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1070.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, OX, UX, XX,VXSNAN, VXISI"
  1071.            Pseudocode=""/>
  1072.         <Mnemonic
  1073.            Form="fadds frD,frA,frB"
  1074.            Notes="Single precision floating point add."/>
  1075.         <Mnemonic
  1076.            Form="fadds. frD,frA,frB"
  1077.            Notes="Single precision floating point add and record."/>
  1078.     </Instruction>
  1079.     <Instruction>
  1080.         <Details
  1081.            Name="Floating Convert from Integer Doubleword"
  1082.            Description="The 64-bit signed fixed-point operand in register frB is converted to an infinitely precise floating-point integer. The result of the conversion is rounded to double-precision using the rounding mode specified by FPSCR[RN] and placed into register frD.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact."
  1083.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, VX, FEX, OX                 (if Rc = '1')&#10; * Floating-point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, XX"
  1084.            Pseudocode=""/>
  1085.         <Mnemonic
  1086.            Form="fcfid frD,frB"
  1087.            Notes="Floating point from integer doubleword."/>
  1088.         <Mnemonic
  1089.            Form="fcfid. frD,frB"
  1090.            Notes="Floating point from integer doubleword and record."/>
  1091.     </Instruction>
  1092.     <Instruction>
  1093.         <Details
  1094.            Name="Floating Compare Ordered"
  1095.            Description="The floating-point operand in frA is compared to the floating-point operand in frB. The result of the compare is placed into CR field crfD and the FPCC.&#10;&#10;If one of the operands is a NaN, either quiet or signaling, then CR field crfD and the FPCC are set to reflect unordered. If one of the operands is a signaling NaN, then VXSNAN is set, and if invalid operation is disabled (VE = '0') then VXVC is set. Otherwise, if one of the operands is a QNaN, then VXVC is set."
  1096.            OtherRegs="* Condition Register (CR field specified by operand crfD):&#10;    Affected: LT, GT, EQ, UN&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPCC, FX, VXSNAN, VXVC"
  1097.            Pseudocode="         if (frA) is a NaN or (frB) is a NaN then &#10;           c = '0001'&#10;         else if (frA)&lt; (frB) then&#10;           c = '1000'&#10;         else if (frA)&gt; (frB) then&#10;           c = '0100'&#10;         else&#10;                     c = '0010'&#10;         FPCC = c&#10;         CR[(4 * crfD) - (4 * crfD + 3)] = c&#10;         if (frA) is an SNaN or (frB) is an SNaN then&#10;           VXSNAN = 1&#10;           if VE = 0 then &#10;             VXVC = 1&#10;         else if (frA) is a QNaN or (frB) is a QNaN then &#10;           VXVC = 1"/>
  1098.         <Mnemonic
  1099.            Form="fcmpo crfD,frA,frB"
  1100.            Notes="Floating point compare ordered. This instruction sets the VXVC bit in the FPSCR."/>
  1101.     </Instruction>
  1102.     <Instruction>
  1103.         <Details
  1104.            Name="Floating Compare Unordered"
  1105.            Description="The floating-point operand in register frA is compared to the floating-point operand in register frB. The result of the compare is placed into CR field crfD and the FPCC.&#10;&#10;If one of the operands is a NaN, either quiet or signaling, then CR field crfD and the FPCC are set to reflect unordered. If one of the operands is a signaling NaN, then VXSNAN is set."
  1106.            OtherRegs="* Condition Register (CR field specified by operand crfD):&#10;   Affected: LT, GT, EQ, UN&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPCC, FX, VXSNAN"
  1107.            Pseudocode="        if (frA) is a NaN or (frB) is a NaN then &#10;          c = '0001'&#10;        else if (frA) &lt; (frB) then&#10;          c = '1000'&#10;        else if (frA) &gt; (frB) then&#10;          c = '0100'          &#10;        else&#10;          c = '0010'&#10;        FPCC = c&#10;        CR[(4 * crfD) - (4 * crfD + 3)] = c&#10;        if (frA) is an SNaN or (frB) is an SNaN then&#10;          VXSNAN = 1"/>
  1108.         <Mnemonic
  1109.            Form="fcmpu crfD,frA,frB"
  1110.            Notes="Floating point compare unordered."/>
  1111.     </Instruction>
  1112.     <Instruction>
  1113.         <Details
  1114.            Name="Floating Convert to Integer Doubleword"
  1115.            Description="The floating-point operand in frB is converted to a 64-bit signed fixed-point integer, using the rounding mode specified by FPSCR[RN], and placed into frD.&#10;&#10;If the operand in frB is greater than 2^63 - 1, then frD is set to 0x7FFF_FFFF_FFFF_FFFF. If the operand in frB is less than -2^63, then frD is set to 0x8000_0000_0000_0000.&#10;&#10;Except for enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact."
  1116.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX               (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI"
  1117.            Pseudocode=""/>
  1118.         <Mnemonic
  1119.            Form="fctid frD,frB"
  1120.            Notes="Floating point convert to integer doubleword."/>
  1121.         <Mnemonic
  1122.            Form="fctid. frD,frB"
  1123.            Notes="Floating point convert to integer doubleword and record."/>
  1124.     </Instruction>
  1125.     <Instruction>
  1126.         <Details
  1127.            Name="Floating Convert to Integer Doubleword with Round toward Zero"
  1128.            Description="The floating-point operand in frB is converted to a 64-bit signed fixed-point integer, using the rounding mode round toward zero, and placed into frD.&#10;&#10;If the operand in frB is greater than 2^63 - 1, then frD is set to 0x7FFF_FFFF_FFFF_FFFF. If the operand in frB is less than -2^63, then frD is set to 0x8000_0000_0000_0000.&#10;&#10;Except for enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact."
  1129.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI"
  1130.            Pseudocode=""/>
  1131.         <Mnemonic
  1132.            Form="fctidz frD,frB"
  1133.            Notes="Floating point convert to integer doubleword with round toward zero."/>
  1134.         <Mnemonic
  1135.            Form="fctidz. frD,frB"
  1136.            Notes="Floating point convert to integer doubleword with round toward zero and record."/>
  1137.     </Instruction>
  1138.     <Instruction>
  1139.         <Details
  1140.            Name="Floating Convert to Integer Word"
  1141.            Description="The floating-point operand in register frB is converted to a 32-bit signed integer, using the rounding mode specified by FPSCR[RN], and placed in bits [32-63] of frD. Bits [0-31] of frD are undefined.&#10;&#10;If the operand in frB are greater than 2^31 - 1, bits [32-63] of frD are set to 0x7FFF_FFFF.&#10;&#10;If the operand in frB are less than -2^31, bits [32-63] of frD are set to 0x8000_0000.&#10;&#10;Except for trap-enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact.&#10;&#10;(Programmers note: A stfiwz instruction should be used to store the 32-bit resultant integer because bits [0-31] of frD are undefined.)"
  1142.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX               (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI"
  1143.            Pseudocode=""/>
  1144.         <Mnemonic
  1145.            Form="fctiw frD,frB"
  1146.            Notes="Floating point convert to integer word."/>
  1147.         <Mnemonic
  1148.            Form="fctiw. frD,frB"
  1149.            Notes="Floating point convert to integer word and record."/>
  1150.     </Instruction>
  1151.     <Instruction>
  1152.         <Details
  1153.            Name="Floating Convert to Integer Word with Round toward Zero"
  1154.            Description="The floating-point operand in register frB is converted to a 32-bit signed integer, using the rounding mode round toward zero, and placed in bits [32-63] of frD. Bits [0-31] of frD are undefined.&#10;&#10;If the operand in frB is greater than 2^31 - 1, bits [32-63] of frD are set to 0x7FFF_FFFF. If the operand in frB is less than -2^31, bits [32-63] of frD are set to 0x 8000_0000.&#10;&#10;Except for trap-enabled invalid operation exceptions, FPSCR[FPRF] is undefined. FPSCR[FR] is set if the result is incremented when rounded. FPSCR[FI] is set if the result is inexact.&#10;&#10;(Programmers note: A stfiwz instruction should be used to store the 32-bit resultant integer because bits [0-31] of frD are undefined.)"
  1155.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF (undefined), FR, FI, FX, XX, VXSNAN, VXCVI"
  1156.            Pseudocode=""/>
  1157.         <Mnemonic
  1158.            Form="fctiwz frD,frB"
  1159.            Notes="Floating point convert to integer word with round toward zero."/>
  1160.         <Mnemonic
  1161.            Form="fctiwz. frD,frB"
  1162.            Notes="Floating point convert to integer word with round toward zero and record."/>
  1163.     </Instruction>
  1164.     <Instruction>
  1165.         <Details
  1166.            Name="Floating Divide"
  1167.            Description="The floating-point operand in register frA is divided by the floating-point operand in register frB. The remainder is not supplied as a result.&#10;&#10;If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;Floating-point division is based on exponent subtraction and division of the significands.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1' and zero divide exceptions when FPSCR[ZE] = '1'."
  1168.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, OX, UX, ZX, XX, VXSNAN, VXIDI, VXZDZ"
  1169.            Pseudocode=""/>
  1170.         <Mnemonic
  1171.            Form="fdiv frD,frA,frB"
  1172.            Notes="Floating point divide."/>
  1173.         <Mnemonic
  1174.            Form="fdiv. frD,frA,frB"
  1175.            Notes="Floating point divide and record."/>
  1176.     </Instruction>
  1177.     <Instruction>
  1178.         <Details
  1179.            Name="Floating Divide Single"
  1180.            Description="The floating-point operand in register frA is divided by the floating-point operand in register frB. The remainder is not supplied as a result.&#10;&#10;If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;Floating-point division is based on exponent subtraction and division of the significands.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1' and zero divide exceptions when FPSCR[ZE] = '1'."
  1181.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, ZX, XX, VXSNAN, VXIDI, VXZDZ"
  1182.            Pseudocode=""/>
  1183.         <Mnemonic
  1184.            Form="fdivs frD,frA,frB"
  1185.            Notes="Single precision floating point divide."/>
  1186.         <Mnemonic
  1187.            Form="fdivs. frD,frA,frB"
  1188.            Notes="Single precision floating point divide and record."/>
  1189.     </Instruction>
  1190.     <Instruction>
  1191.         <Details
  1192.            Name="Floating Multiply-Add"
  1193.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is added to this intermediate result.&#10;&#10;If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1194.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ"
  1195.            Pseudocode="         frD = (frA * frC) + frB"/>
  1196.         <Mnemonic
  1197.            Form="fmadd frD,frA,frC,frB"
  1198.            Notes="Floating point multiply-add."/>
  1199.         <Mnemonic
  1200.            Form="fmadd. frD,frA,frC,frB"
  1201.            Notes="Floating point multiply-add and record."/>
  1202.     </Instruction>
  1203.     <Instruction>
  1204.         <Details
  1205.            Name="Floating Multiply-Add Single"
  1206.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is added to this intermediate result.&#10;&#10;If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1207.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ"
  1208.            Pseudocode="         frD = (frA * frC) + frB"/>
  1209.         <Mnemonic
  1210.            Form="fmadds frD,frA,frC,frB"
  1211.            Notes="Single precision floating point multiply-add."/>
  1212.         <Mnemonic
  1213.            Form="fmadds. frD,frA,frC,frB"
  1214.            Notes="Single precision floating point multiply-add and record."/>
  1215.     </Instruction>
  1216.     <Instruction>
  1217.         <Details
  1218.            Name="Floating Move Register"
  1219.            Description="The contents of register frB are placed into frD."
  1220.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX               (if Rc = '1')"
  1221.            Pseudocode="         frD = (frB)"/>
  1222.         <Mnemonic
  1223.            Form="fmr frD,frB"
  1224.            Notes="Floating point move register."/>
  1225.         <Mnemonic
  1226.            Form="fmr. frD,frB"
  1227.            Notes="Floating point move register and record."/>
  1228.     </Instruction>
  1229.     <Instruction>
  1230.         <Details
  1231.            Name="Floating Multiply-Subtract"
  1232.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is subtracted from this intermediate result.&#10;&#10;If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1233.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                   (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ"
  1234.            Pseudocode="        frD = [frA * frC] - frB"/>
  1235.         <Mnemonic
  1236.            Form="fmsub frD,frA,frC,frB"
  1237.            Notes="Floating point multiply-subtract."/>
  1238.         <Mnemonic
  1239.            Form="fmsub. frD,frA,frC,frB"
  1240.            Notes="Floating point multiply-subtract and record."/>
  1241.     </Instruction>
  1242.     <Instruction>
  1243.         <Details
  1244.            Name="Floating Multiply-Subtract Single"
  1245.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is subtracted from this intermediate result.&#10;&#10;If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1246.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ"
  1247.            Pseudocode="         frD = [frA * frC] - frB"/>
  1248.         <Mnemonic
  1249.            Form="fmsubs frD,frA,frC,frB"
  1250.            Notes="Single precision floating point multiply-subtract."/>
  1251.         <Mnemonic
  1252.            Form="fmsubs. frD,frA,frC,frB"
  1253.            Notes="Single precision floating point multiply-subtract and record."/>
  1254.     </Instruction>
  1255.     <Instruction>
  1256.         <Details
  1257.            Name="Floating Multiply"
  1258.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC.&#10;&#10;If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;Floating-point multiplication is based on exponent addition and multiplication of the significands.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1259.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                   (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXIMZ"
  1260.            Pseudocode="         frD = (frA) * (frC)"/>
  1261.         <Mnemonic
  1262.            Form="fmul frD,frA,frC"
  1263.            Notes="Floating point multiply."/>
  1264.         <Mnemonic
  1265.            Form="fmul. frD,frA,frC"
  1266.            Notes="Floating point multiply and record."/>
  1267.     </Instruction>
  1268.     <Instruction>
  1269.         <Details
  1270.            Name="Floating Multiply Single"
  1271.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC.&#10;&#10;If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;Floating-point multiplication is based on exponent addition and multiplication of the significands.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1272.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                  (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXIMZ"
  1273.            Pseudocode="         frD = (frA) * (frC)"/>
  1274.         <Mnemonic
  1275.            Form="fmuls frD,frA,frC"
  1276.            Notes="Single precision floating point multiply."/>
  1277.         <Mnemonic
  1278.            Form="fmuls. frD,frA,frC"
  1279.            Notes="Single precision floating point multiply and record."/>
  1280.     </Instruction>
  1281.     <Instruction>
  1282.         <Details
  1283.            Name="Floating Negative Absolute Value"
  1284.            Description="The contents of register frB with bit [0] set are placed into frD.&#10;&#10;Note: The fnabs instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may be altered by fnabs. This instruction does not alter the FPSCR."
  1285.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                 (if Rc = '1')"
  1286.            Pseudocode="         frD = 1 || frB[1-63]"/>
  1287.         <Mnemonic
  1288.            Form="fnabs frD,frB"
  1289.            Notes="Floating point negative absolute value."/>
  1290.         <Mnemonic
  1291.            Form="fnabs. frD,frB"
  1292.            Notes="Floating point negative absolute value and record."/>
  1293.     </Instruction>
  1294.     <Instruction>
  1295.         <Details
  1296.            Name="Floating Negate"
  1297.            Description="The contents of register frB with bit [0] inverted are placed into frD.&#10;&#10;Note: The fneg instruction treats NaNs just like any other kind of value. That is, the sign bit of a NaN may be altered by fneg. This instruction does not alter the FPSCR."
  1298.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                (if Rc = '1')"
  1299.            Pseudocode="         frD = ! frB[0] || frB[1-63]"/>
  1300.         <Mnemonic
  1301.            Form="fneg frD,frB"
  1302.            Notes="Floating point negate."/>
  1303.         <Mnemonic
  1304.            Form="fneg. frD,frB"
  1305.            Notes="Floating point negate and record."/>
  1306.     </Instruction>
  1307.     <Instruction>
  1308.         <Details
  1309.            Name="Floating Negative Multiply-Add"
  1310.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is added to this intermediate result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision undercontrol of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD.&#10;&#10;This instruction produces the same result as would be obtained by using the Floating Multiply-Add (fmaddx) instruction and then negating the result, with the following exceptions:&#10; * QNaNs propagate with no effect on their sign bit.&#10; * QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero.&#10; * SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign bit of the SNaN.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1311.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ"
  1312.            Pseudocode="        frD = - ([frA * frC] + frB)"/>
  1313.         <Mnemonic
  1314.            Form="fnmadd frD,frA,frC,frB"
  1315.            Notes="Floating point negative multiply-add."/>
  1316.         <Mnemonic
  1317.            Form="fnmadd. frD,frA,frC,frB"
  1318.            Notes="Floating point negative multiply-add and record."/>
  1319.     </Instruction>
  1320.     <Instruction>
  1321.         <Details
  1322.            Name="Floating Negative Multiply-Add Single"
  1323.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is added to this intermediate result. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision undercontrol of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD.&#10;&#10;This instruction produces the same result as would be obtained by using the Floating Multiply-Add Single (fmaddsx) instruction and then negating the result, with the following exceptions:&#10; * QNaNs propagate with no effect on their sign bit.&#10; * QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero.&#10; * SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign bit of the SNaN.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1324.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ"
  1325.            Pseudocode="         frD = - ([frA * frC] + frB)"/>
  1326.         <Mnemonic
  1327.            Form="fnmadds frD,frA,frC,frB"
  1328.            Notes="Single precision floating point negative multiply-add."/>
  1329.         <Mnemonic
  1330.            Form="fnmadds. frD,frA,frC,frB"
  1331.            Notes="Single precision floating point negative multiply-add and record."/>
  1332.     </Instruction>
  1333.     <Instruction>
  1334.         <Details
  1335.            Name="Floating Negative Multiply-Subtract"
  1336.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is subtracted from this intermediate result.&#10;&#10;If the most-significant bit of the resultant significand is not one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD.&#10;&#10;This instruction produces the same result obtained by negating the result of a Floating Multiply-Subtract&#10;(fmsubx) instruction with the following exceptions:&#10; * QNaNs propagate with no effect on their sign bit.&#10; * QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero.&#10; * SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign bit of the SNaN.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1337.            OtherRegs="* Condition Register (CR1 field)&#10;   Affected: FX, FEX, VX, OX                  (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ"
  1338.            Pseudocode="        frD = - ([frA * frC] - frB)"/>
  1339.         <Mnemonic
  1340.            Form="fnmsub frD,frA,frC,frB"
  1341.            Notes="Floating point negative multiply-subtract."/>
  1342.         <Mnemonic
  1343.            Form="fnmsub. frD,frA,frC,frB"
  1344.            Notes="Floating point negative multiply-subtract and record."/>
  1345.     </Instruction>
  1346.     <Instruction>
  1347.         <Details
  1348.            Name="Floating Negative Multiply-Subtract Single"
  1349.            Description="The floating-point operand in register frA is multiplied by the floating-point operand in register frC. The floating-point operand in register frB is subtracted from this intermediate result.&#10;&#10;If the most-significant bit of the resultant significand is not one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR, then negated and placed into frD.&#10;&#10;This instruction produces the same result obtained by negating the result of a Floating Multiply-Subtract Single (fmsubsx) instruction with the following exceptions:&#10; * QNaNs propagate with no effect on their sign bit.&#10; * QNaNs that are generated as the result of a disabled invalid operation exception have a sign bit of zero.&#10; * SNaNs that are converted to QNaNs as the result of a disabled invalid operation exception retain the sign bit of the SNaN.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1350.            OtherRegs="* Condition Register (CR1 field)&#10;    Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI, VXIMZ"
  1351.            Pseudocode="         frD = - ([frA * frC] - frB)"/>
  1352.         <Mnemonic
  1353.            Form="fnmsubs frD,frA,frC,frB"
  1354.            Notes="Single precision floating point negative multiply-subtract."/>
  1355.         <Mnemonic
  1356.            Form="fnmsubs. frD,frA,frC,frB"
  1357.            Notes="Single precision floating point negative multiply-subtract and record."/>
  1358.     </Instruction>
  1359.     <Instruction>
  1360.         <Details
  1361.            Name="Floating Reciprocal Estimate Single"
  1362.            Description="A single-precision estimate of the reciprocal of the floating-point operand in register frB is placed into register frD. The estimate placed into register frD is correct to a precision of one part in 256 of the reciprocal of frB. That is,&#10;&#10;ABS( ( estimate / (1/x) ) / (1/x) ) &lt;= 1/256&#10;&#10;where x is the initial value in frB. Note that the value placed into register frD may vary between implementations, and between different executions on the same implementation.&#10;&#10;Operation with various special values of the operand is summarized below:&#10;&#10;Operand                    Result                  Exception&#10;-INF                       -0                      None&#10;-0                         -INF(1)                 ZX&#10;+0                         +INF(1)                 ZX&#10;+INF                       +0                      None&#10;SNaN                       QNaN(2)                 VXSNAN&#10;QNaN                       QNaN                    None&#10;&#10;Notes:&#10;  1. No result if FPSCR[ZE] = '1'&#10;  2. No result if FPSCR[VE] = '1'&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1' and zero divide exceptions when FPSCR[ZE] = '1'.&#10;&#10;Note: The PowerPC Architecture makes no provision for a double-precision version of the fresx instruction. This is because graphics applications are expected to need only the single-precision version, and no other important performance-critical applications are expected to require a double-precision version of the fresx instruction.&#10;&#10;Note: This instruction is optional in the PowerPC Architecture."
  1363.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX            (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR (undefined), FI (undefined), FX, OX, UX, ZX, VXSNAN"
  1364.            Pseudocode="         frD = estimate[1/(frB)]"/>
  1365.         <Mnemonic
  1366.            Form="fres frD,frB"
  1367.            Notes="Single precision floating point reciprocal estimate."/>
  1368.         <Mnemonic
  1369.            Form="fres. frD,frB"
  1370.            Notes="Single precision floating point reciprocal estimate and record."/>
  1371.     </Instruction>
  1372.     <Instruction>
  1373.         <Details
  1374.            Name="Floating Round to Single"
  1375.            Description="If it is already in single-precision range, the floating-point operand in register frB is placed into frD. Otherwise, the floating-point operand in register frB is rounded to single-precision using the rounding mode specified by FPSCR[RN] and placed into frD.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1376.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                  (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN"
  1377.            Pseudocode="        frD = Round_single( frB )"/>
  1378.         <Mnemonic
  1379.            Form="frsp frD,frB"
  1380.            Notes="Floating point round to single precision."/>
  1381.         <Mnemonic
  1382.            Form="frsp. frD,frB"
  1383.            Notes="Floating point round to single precision and record."/>
  1384.     </Instruction>
  1385.     <Instruction>
  1386.         <Details
  1387.            Name="Floating Reciprocal Square Root Estimate"
  1388.            Description="A double-precision estimate of the reciprocal of the square root of the floating-point operand in register frB is placed into register frD. The estimate placed into register frD is correct to a precision of one part in 32 of the reciprocal of the square root of frB. That is,&#10;&#10;ABS( ( estimate / (sqrt(x)) ) / (sqrt(x)) ) &lt;= 1/32&#10;&#10;where x is the initial value in frB. Note that the value placed into register frD may vary between implementations, and between different executions on the same implementation.&#10;&#10;Operation with various special values of the operand is summarized below:&#10;&#10;Operand                    Result                  Exception&#10;-INF                       QNaN(2)                 VXSQRT                                  &#10;&lt;0                      QNaN(2)                 VXSQRT&#10;-0                         -INF(1)                 ZX&#10;+0                         +INF(1)                 ZX  &#10;+INF                       +0                      None                &#10;SNaN                       QNaN(2)                 VXSNAN&#10;QNaN                       QNaN                    None&#10;&#10;Notes:&#10;  1. No result if FPSCR[ZE] = '1'&#10;  2. No result if FPSCR[VE] = '1'&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1' and zero divide exceptions when FPSCR[ZE] = '1'.&#10;&#10;Note: No single-precision version of the frsqrte instruction is provided; however, both frB and frD are representable in single-precision format.&#10;&#10;Note: This instruction is optional in the PowerPC Architecture."
  1389.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX         (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR (undefined), FI (undefined), FX, ZX, VXSNAN, VXSQRT"
  1390.            Pseudocode=""/>
  1391.         <Mnemonic
  1392.            Form="frsqrte frD,frB"
  1393.            Notes="Floating point reciprocal square root estimate."/>
  1394.         <Mnemonic
  1395.            Form="frsqrte. frD,frB"
  1396.            Notes="Floating point reciprocal square root estimate and record."/>
  1397.     </Instruction>
  1398.     <Instruction>
  1399.         <Details
  1400.            Name="Floating Select"
  1401.            Description="The floating-point operand in register frA is compared to the value zero. If the operand is greater than or equal to zero, register frD is set to the contents of register frC. If the operand is less than zero or is a NaN, register frD is set to the contents of register frB. The comparison ignores the sign of zero (that is, regards +0 as equal to -0).&#10;&#10;Care must be taken in using fsel if IEEE compatibility is required, or if the values being tested can be NaNs or infinities.&#10;&#10;Note: This instruction is optional in the PowerPC Architecture."
  1402.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                (if Rc = '1')"
  1403.            Pseudocode="         if (frA) &gt;= 0.0 then &#10;           frD = (frC)&#10;         else &#10;           frD = (frB)"/>
  1404.         <Mnemonic
  1405.            Form="fsel frD,frA,frC,frB"
  1406.            Notes="Floating point select."/>
  1407.         <Mnemonic
  1408.            Form="fsel. frD,frA,frC,frB"
  1409.            Notes="Floating point select and record."/>
  1410.     </Instruction>
  1411.     <Instruction>
  1412.         <Details
  1413.            Name="Floating Square Root"
  1414.            Description="The square root of the floating-point operand in register frB is placed into register frD.&#10;&#10;If the most-significant bit of the resultant significand is not a one the result is normalized. The result is rounded to the target precision under control of the floating-point rounding control field RN of the FPSCR and placed into register frD.&#10;&#10;Operation with various special values of the operand is summarized below.&#10;Operand: Result - Exception&#10;-INF: QNaN(1) - VXSQRT                                  &#10;&lt;0: QNaN(1) - VXSQRT&#10;-0: -0 - None&#10;+INF: +INF - None                &#10;SNaN: QNaN(1) - VXSNAN&#10;QNaN: QNaN - None&#10;&#10;Note:&#10;  1. No result if FPSCR[VE] = '1'&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'.&#10;&#10;Note: This instruction is optional in the PowerPC Architecture."
  1415.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                   (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, XX, VXSNAN, VXSQRT"
  1416.            Pseudocode="         frD = (Square_rootfrB)"/>
  1417.         <Mnemonic
  1418.            Form="fsqrt frD,frB"
  1419.            Notes="Floating point square root."/>
  1420.         <Mnemonic
  1421.            Form="fsqrt. frD,frB"
  1422.            Notes="Floating point square root and record."/>
  1423.     </Instruction>
  1424.     <Instruction>
  1425.         <Details
  1426.            Name="Floating Square Root Single"
  1427.            Description="If the most-significant bit of the resultant significand is not a one the result is normalized. The result is rounded to the target precision under control of the floating-point rounding control field RN of the FPSCR and placed into register frD.&#10;&#10;Operation with various special values of the operand is summarized below.&#10;Operand: Result - Exception&#10;-INF: QNaN(1) - VXSQRT                                  &#10;&lt;0: QNaN(1) - VXSQRT&#10;-0: -0 - None&#10;+INF: +INF - None                &#10;SNaN: QNaN(1) - VXSNAN&#10;QNaN: QNaN - None&#10;&#10;Note:&#10;  1. No result if FPSCR[VE] = '1'&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'.&#10;&#10;Note: This instruction is optional in the PowerPC Architecture."
  1428.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                  (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, XX, VXSNAN, VXSQRT"
  1429.            Pseudocode="          frD = (Square_rootfrB)"/>
  1430.         <Mnemonic
  1431.            Form="fsqrts frD,frB"
  1432.            Notes="Single precision floating point square root."/>
  1433.         <Mnemonic
  1434.            Form="fsqrts. frD,frB"
  1435.            Notes="Single precision floating point squire root and record."/>
  1436.     </Instruction>
  1437.     <Instruction>
  1438.         <Details
  1439.            Name="Floating Subtract"
  1440.            Description="The floating-point operand in register frB is subtracted from the floating-point operand in register frA. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to double-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;The execution of the fsub instruction is identical to that of fadd, except that the contents of frB participate in the operation with its sign bit (bit [0]) inverted.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1441.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI"
  1442.            Pseudocode="        frD = (frA) - (frB)"/>
  1443.         <Mnemonic
  1444.            Form="fsub frD,frA,frB"
  1445.            Notes="Floating point subtract."/>
  1446.         <Mnemonic
  1447.            Form="fsub. frD,frA,frB"
  1448.            Notes="Floating point subtract and record."/>
  1449.     </Instruction>
  1450.     <Instruction>
  1451.         <Details
  1452.            Name="Floating Subtract Single"
  1453.            Description="The floating-point operand in register frB is subtracted from the floating-point operand in register frA. If the most-significant bit of the resultant significand is not a one, the result is normalized. The result is rounded to single-precision under control of the floating-point rounding control field RN of the FPSCR and placed into frD.&#10;&#10;The execution of the fsubs instruction is identical to that of fadds, except that the contents of frB participate in the operation with its sign bit (bit [0]) inverted.&#10;&#10;FPSCR[FPRF] is set to the class and sign of the result, except for invalid operation exceptions when FPSCR[VE] = '1'."
  1454.            OtherRegs="* Condition Register (CR1 field):&#10;    Affected: FX, FEX, VX, OX                (if Rc = '1')&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FPRF, FR, FI, FX, OX, UX, XX, VXSNAN, VXISI"
  1455.            Pseudocode=""/>
  1456.         <Mnemonic
  1457.            Form="fsubs frD,frA,frB"
  1458.            Notes="Single precision floating point subtract."/>
  1459.         <Mnemonic
  1460.            Form="fsubs. frD,frA,frB"
  1461.            Notes="Single precision floating point subtract and record."/>
  1462.     </Instruction>
  1463.     <Instruction>
  1464.         <Details
  1465.            Name="Instruction Cache Block Invalidate"
  1466.            Description="The effective address is the sum (rA|0) + (rB).&#10;&#10;If the block containing the byte addressed by EA is in coherency-required mode, and a block containing the byte addressed by EA is in the instruction cache of any processor, the block is made invalid in all such instruction caches, so that subsequent references cause the block to be refetched.&#10;&#10;If the block containing the byte addressed by EA is in coherency-not-required mode, and a block containing the byte addressed by EA is in the instruction cache of this processor, the block is made invalid in that instruction cache, so that subsequent references cause the block to be refetched.&#10;&#10;The function of this instruction is independent of the write-through, write-back, and caching-inhibited/allowed modes of the block containing the byte addressed by EA.&#10;&#10;This instruction is treated as a load from the addressed byte with respect to address translation and memory protection. It may also be treated as a load for referenced and changed bit recording except that referenced and changed bit recording may not occur. Implementations with a combined data and instruction cache treat the icbi instruction as a no-op, except that they may invalidate the target block in the instruction caches of other processors if the block is in coherency-required mode.&#10;&#10;The icbi instruction invalidates the block at EA (rA|0 + rB). If the processor is a multiprocessor implementation and the block is marked coherency-required, the processor will send an address-only broadcast to other processors causing those processors to invalidate the block from their instruction caches.&#10;&#10;For faster processing, many implementations will not compare the entire EA (rA|0 + rB) with the tag in the instruction cache. Instead, they will use the bits in the EA to locate the set that the block is in, and invalidate all blocks in that set."
  1467.            OtherRegs=""
  1468.            Pseudocode=""/>
  1469.         <Mnemonic
  1470.            Form="icbi rA,rB"
  1471.            Notes="The instruction block at the effective address is invalidated."/>
  1472.     </Instruction>
  1473.     <Instruction>
  1474.         <Details
  1475.            Name="Instruction Synchronize"
  1476.            Description="The isync instruction provides an ordering function for the effects of all instructions executed by a processor. Executing an isync instruction ensures that all instructions preceding the isync instruction have completed before the isync instruction completes, except that memory accesses caused by those instructions need not have been performed with respect to other processors and mechanisms. It also ensures that no subsequent instructions are initiated by the processor until after the isync instruction completes. Finally, it causes the processor to discard any prefetched instructions, with the effect that subsequent instructions will be fetched and executed in the context established by the instructions preceding the isync instruction. The isync instruction has no effect on the other processors or on their caches.&#10;&#10;This instruction is context synchronizing.&#10;&#10;Context synchronization is necessary after certain code sequences that perform complex operations within the processor. These code sequences are usually operating system tasks that involve memory management. For example, if an instruction A changes the memory translation rules in the memory management unit (MMU), the isync instruction should be executed so that the instructions following instruction A will be discarded from the pipeline and refetched according to the new translation rules.&#10;&#10;Note: All exceptions and the rfid instruction are also context synchronizing."
  1477.            OtherRegs=""
  1478.            Pseudocode=""/>
  1479.         <Mnemonic
  1480.            Form="isync"
  1481.            Notes="Provides an ordering function for all instructions executed by a processor."/>
  1482.     </Instruction>
  1483.     <Instruction>
  1484.         <Details
  1485.            Name="Load Byte and Zero"
  1486.            Description="EA is the sum (rA|0) + d. The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared."
  1487.            OtherRegs=""
  1488.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + EXTS(d)&#10;        rD = (56)0 || MEM(EA, 1)"/>
  1489.         <Mnemonic
  1490.            Form="lbz rD,d(rA)"
  1491.            Notes="Load byte and zero. The addressing mode is register indirect with immediate index."/>
  1492.     </Instruction>
  1493.     <Instruction>
  1494.         <Details
  1495.            Name="Load Byte and Zero with Update"
  1496.            Description="EA is the sum (rA) + d. The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', or rA = rD, the instruction form is invalid."
  1497.            OtherRegs=""
  1498.            Pseudocode="         EA = (rA) + EXTS(d)&#10;         rD = (56)0 || MEM(EA, 1)&#10;         rA = EA"/>
  1499.         <Mnemonic
  1500.            Form="lbzu rD,d(rA)"
  1501.            Notes="Load byte and zero with update. The addressing mode is register indirect with immediate index."/>
  1502.     </Instruction>
  1503.     <Instruction>
  1504.         <Details
  1505.            Name="Load Byte and Zero with Update Indexed"
  1506.            Description="EA is the sum (rA) + (rB). The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0' or rA = rD, the instruction form is invalid."
  1507.            OtherRegs=""
  1508.            Pseudocode="        EA = (rA) + (rB)&#10;        rD = (56)0 || MEM(EA, 1)&#10;        rA = EA"/>
  1509.         <Mnemonic
  1510.            Form="lbzux rD,rA,rB"
  1511.            Notes="Load byte and zero with update. The addressing mode is register indirect with index."/>
  1512.     </Instruction>
  1513.     <Instruction>
  1514.         <Details
  1515.            Name="Load Byte and Zero Indexed"
  1516.            Description="EA is the sum (rA|0) + (rB). The byte in memory addressed by EA is loaded into the low-order eight bits of rD. The remaining bits in rD are cleared."
  1517.            OtherRegs=""
  1518.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         rD = (56)0 || MEM(EA, 1)"/>
  1519.         <Mnemonic
  1520.            Form="lbzx rD,rA,rB"
  1521.            Notes="Load byte and zero. The addressing mode is register indirect with index."/>
  1522.     </Instruction>
  1523.     <Instruction>
  1524.         <Details
  1525.            Name="Load Doubleword"
  1526.            Description="EA is the sum (rA|0) + (ds || '00'). The doubleword in memory addressed by EA is loaded into rD."
  1527.            OtherRegs=""
  1528.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + EXTS(ds || '00')&#10;         rD = MEM(EA, 8)"/>
  1529.         <Mnemonic
  1530.            Form="ld rD,ds(rA)"
  1531.            Notes="Load doubleword. The addressing mode is register indirect with immediate index."/>
  1532.     </Instruction>
  1533.     <Instruction>
  1534.         <Details
  1535.            Name="Load Doubleword and Reserve Indexed"
  1536.            Description="EA is the sum (rA|0) + (rB). The doubleword in memory addressed by EA is loaded into rD.&#10;&#10;This instruction creates a reservation for use by a Store Doubleword Conditional Indexed (stdcx.) instruction. An address computed from the EA is associated with the reservation, and replaces any address previously associated with the reservation.&#10;&#10;EA must be a multiple of eight. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined."
  1537.            OtherRegs=""
  1538.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         RESERVE = 1&#10;         RESERVE_ADDR = physical_addr(EA)&#10;         rD = MEM(EA, 8)"/>
  1539.         <Mnemonic
  1540.            Form="ldarx rD,rA,rB"
  1541.            Notes="Load doubleword and creates a reservation. The addressing mode is register indirect with index."/>
  1542.     </Instruction>
  1543.     <Instruction>
  1544.         <Details
  1545.            Name="Load Doubleword with Update"
  1546.            Description="EA is the sum (rA) + (ds || '00'). The doubleword in memory addressed by EA is loaded into rD.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0' or rA = rD, the instruction form is invalid."
  1547.            OtherRegs=""
  1548.            Pseudocode="        EA = (rA) + EXTS(ds || '00')&#10;        rD = MEM(EA, 8)&#10;        rA = EA"/>
  1549.         <Mnemonic
  1550.            Form="ldu rD,ds(rA)"
  1551.            Notes="Load doubleword with update. The addressing mode is register indirect with immediate index."/>
  1552.     </Instruction>
  1553.     <Instruction>
  1554.         <Details
  1555.            Name="Load Doubleword with Update Indexed"
  1556.            Description="EA is the sum (rA) + (rB). The doubleword in memory addressed by EA is loaded into rD.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0' or rA = rD, the instruction form is invalid."
  1557.            OtherRegs=""
  1558.            Pseudocode="         EA = (rA) + (rB)&#10;         rD = MEM(EA, 8)&#10;         rA = EA"/>
  1559.         <Mnemonic
  1560.            Form="ldux rD,rA,rB"
  1561.            Notes="Load doubleword with update. The addressing mode is register indirect with index."/>
  1562.     </Instruction>
  1563.     <Instruction>
  1564.         <Details
  1565.            Name="Load Doubleword Indexed"
  1566.            Description="EA is the sum (rA|0) + (rB). The doubleword in memory addressed by EA is loaded into rD."
  1567.            OtherRegs=""
  1568.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        rD = MEM(EA, 8)"/>
  1569.         <Mnemonic
  1570.            Form="ldx rD,rA,rB"
  1571.            Notes="Load doubleword. The addressing mode is register indirect with index."/>
  1572.     </Instruction>
  1573.     <Instruction>
  1574.         <Details
  1575.            Name="Load Floating-Point Double"
  1576.            Description="EA is the sum (rA|0) + d.&#10;&#10;The doubleword in memory addressed by EA is placed into frD."
  1577.            OtherRegs=""
  1578.            Pseudocode="         if rA = 0 then &#10;           b = 0      &#10;         else&#10;           b = (rA)&#10;         EA = b + EXTS(d)&#10;         frD = MEM(EA, 8)"/>
  1579.         <Mnemonic
  1580.            Form="lfd frD,d(rA)"
  1581.            Notes="Load double precision floating point. The addressing mode is register indirect with immediate index."/>
  1582.     </Instruction>
  1583.     <Instruction>
  1584.         <Details
  1585.            Name="Load Floating-Point Double with Update"
  1586.            Description="EA is the sum (rA) + d.&#10;&#10;The doubleword in memory addressed by EA is placed into frD.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  1587.            OtherRegs=""
  1588.            Pseudocode="        EA = (rA) + EXTS(d)&#10;        frD = MEM(EA, 8)&#10;        rA = EA"/>
  1589.         <Mnemonic
  1590.            Form="lfdu frD,d(rA)"
  1591.            Notes="Load double precision floating point with update. The addressing mode is register indirect with immediate index."/>
  1592.     </Instruction>
  1593.     <Instruction>
  1594.         <Details
  1595.            Name="Load Floating-Point Double with Update Indexed"
  1596.            Description="EA is the sum (rA) + (rB).&#10;&#10;The doubleword in memory addressed by EA is placed into frD.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  1597.            OtherRegs=""
  1598.            Pseudocode="         EA = (rA) + (rB)&#10;         frD = MEM(EA, 8)&#10;         rA = EA"/>
  1599.         <Mnemonic
  1600.            Form="lfdux frD,rA,rB"
  1601.            Notes="Load double precision floating point with update. The addressing mode is register indirect with index."/>
  1602.     </Instruction>
  1603.     <Instruction>
  1604.         <Details
  1605.            Name="Load Floating-Point Double Indexed"
  1606.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The doubleword in memory addressed by EA is placed into frD."
  1607.            OtherRegs=""
  1608.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        frD = MEM(EA, 8)"/>
  1609.         <Mnemonic
  1610.            Form="lfdx frD,rA,rB"
  1611.            Notes="Load double precision floating point. The addressing mode is register indirect with index."/>
  1612.     </Instruction>
  1613.     <Instruction>
  1614.         <Details
  1615.            Name="Load Floating-Point Single"
  1616.            Description="EA is the sum (rA|0) + d.&#10;&#10;The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double-precision and placed into frD."
  1617.            OtherRegs=""
  1618.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + EXTS(d)&#10;         frD = DOUBLE(MEM(EA, 4))"/>
  1619.         <Mnemonic
  1620.            Form="lfs frD,d(rA)"
  1621.            Notes="Load single precision floating point. The addressing mode is register indirect with immediate index."/>
  1622.     </Instruction>
  1623.     <Instruction>
  1624.         <Details
  1625.            Name="Load Floating-Point Single with Update"
  1626.            Description="EA is the sum (rA) + d.&#10;&#10;The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double-precision and placed&#10;into frD.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  1627.            OtherRegs=""
  1628.            Pseudocode="        EA = (rA) + EXTS(d)&#10;        frD = DOUBLE(MEM(EA, 4))&#10;        rA = EA"/>
  1629.         <Mnemonic
  1630.            Form="lfsu frD,d(rA)"
  1631.            Notes="Load single precision floating point with update. The addressing mode is register indirect with immediate index."/>
  1632.     </Instruction>
  1633.     <Instruction>
  1634.         <Details
  1635.            Name="Load Floating-Point Single with Update Indexed"
  1636.            Description="EA is the sum (rA) + (rB).&#10;&#10;The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double-precision and placed into frD.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  1637.            OtherRegs=""
  1638.            Pseudocode="         EA = (rA) + (rB)&#10;         frD = DOUBLE(MEM(EA, 4))&#10;         rA = EA"/>
  1639.         <Mnemonic
  1640.            Form="lfsux frD,rA,rB"
  1641.            Notes="Load single precision floating point with update. The addressing mode is register indirect with index."/>
  1642.     </Instruction>
  1643.     <Instruction>
  1644.         <Details
  1645.            Name="Load Floating-Point Single Indexed"
  1646.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The word in memory addressed by EA is interpreted as a floating-point single-precision operand. This word is converted to floating-point double-precision and placed into frD."
  1647.            OtherRegs=""
  1648.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        frD = DOUBLE(MEM(EA, 4))"/>
  1649.         <Mnemonic
  1650.            Form="lfsx frD,rA,rB"
  1651.            Notes="Load single precision floating point. The addressing mode is register indirect with index."/>
  1652.     </Instruction>
  1653.     <Instruction>
  1654.         <Details
  1655.            Name="Load Halfword Algebraic"
  1656.            Description="EA is the sum (rA|0) + d. The halfword in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded halfword."
  1657.            OtherRegs=""
  1658.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + EXTS(d)&#10;         rD = EXTS(MEM(EA, 2))"/>
  1659.         <Mnemonic
  1660.            Form="lha rD,d(rA)"
  1661.            Notes="Load sign extended halfword. The addressing mode is register indirect with immediate index."/>
  1662.     </Instruction>
  1663.     <Instruction>
  1664.         <Details
  1665.            Name="Load Halfword Algebraic with Update"
  1666.            Description="EA is the sum (rA) + d. The halfword in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded halfword.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0' or rA = rD, the instruction form is invalid."
  1667.            OtherRegs=""
  1668.            Pseudocode="        EA = (rA) + EXTS(d)&#10;        rD = EXTS(MEM(EA, 2))&#10;        rA = EA"/>
  1669.         <Mnemonic
  1670.            Form="lhau rD,d(rA)"
  1671.            Notes="Load sign extended halfword with update. The addressing mode is register indirect with immediate index."/>
  1672.     </Instruction>
  1673.     <Instruction>
  1674.         <Details
  1675.            Name="Load Halfword Algebraic with Update Indexed"
  1676.            Description="EA is the sum (rA) + (rB). The halfword in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded halfword.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0' or rA = rD, the instruction form is invalid."
  1677.            OtherRegs=""
  1678.            Pseudocode="         EA = (rA) + (rB)&#10;         rD = EXTS(MEM(EA, 2))&#10;         rA = EA"/>
  1679.         <Mnemonic
  1680.            Form="lhaux rD,rA,rB"
  1681.            Notes="Load sign extended halfword with update. The addressing mode is register indirect with index."/>
  1682.     </Instruction>
  1683.     <Instruction>
  1684.         <Details
  1685.            Name="Load Halfword Algebraic Indexed"
  1686.            Description="EA is the sum (rA|0) + (rB). The halfword in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are filled with a copy of the most-significant bit of the loaded halfword."
  1687.            OtherRegs=""
  1688.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        rD = EXTS(MEM(EA, 2))"/>
  1689.         <Mnemonic
  1690.            Form="lhax rD,rA,rB"
  1691.            Notes="Load sign extended halfword. The addressing mode is register indirect with index."/>
  1692.     </Instruction>
  1693.     <Instruction>
  1694.         <Details
  1695.            Name="Load Halfword Byte-Reverse Indexed"
  1696.            Description="EA is the sum (rA|0) + (rB). Bits [0-7] of the halfword in memory addressed by EA are loaded into the low-order eight bits of rD. Bits [8-15] of the halfword in memory addressed by EA are loaded into the subsequent low-order eight bits of rD. The remaining bits in rD are cleared.&#10;&#10;The PowerPC Architecture cautions programmers that some implementations of the architecture may run the lhbrx instructions with greater latency than other types of load instructions."
  1697.            OtherRegs=""
  1698.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         rD = (48)0 || MEM(EA + 1, 1) || MEM(EA, 1)"/>
  1699.         <Mnemonic
  1700.            Form="lhbrx rD,rA,rB"
  1701.            Notes="Load byte-reversed halfword. The addressing mode is register indirect with index."/>
  1702.     </Instruction>
  1703.     <Instruction>
  1704.         <Details
  1705.            Name="Load Halfword and Zero"
  1706.            Description="EA is the sum (rA|0) + d. The halfword in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared."
  1707.            OtherRegs=""
  1708.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + EXTS(d)&#10;        rD = (48)0 || MEM(EA, 2)"/>
  1709.         <Mnemonic
  1710.            Form="lhz rD,d(rA)"
  1711.            Notes="Load halfword and zero. The addressing mode is register indirect with immediate index."/>
  1712.     </Instruction>
  1713.     <Instruction>
  1714.         <Details
  1715.            Name="Load Halfword and Zero with Update"
  1716.            Description="EA is the sum (rA) + d. The halfword in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0' or rA = rD, the instruction form is invalid."
  1717.            OtherRegs=""
  1718.            Pseudocode="         EA = rA + EXTS(d)&#10;         rD = (48)0 || MEM(EA, 2)&#10;         rA = EA"/>
  1719.         <Mnemonic
  1720.            Form="lhzu rD,d(rA)"
  1721.            Notes="Load halfword and zero with update. The addressing mode is register indirect with immediate index."/>
  1722.     </Instruction>
  1723.     <Instruction>
  1724.         <Details
  1725.            Name="Load Halfword and Zero with Update Indexed"
  1726.            Description="EA is the sum (rA) + (rB). The halfword in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0' or rA = rD, the instruction form is invalid."
  1727.            OtherRegs=""
  1728.            Pseudocode="        EA = (rA) + (rB)&#10;        rD = (48)0 || MEM(EA, 2)&#10;        rA = EA"/>
  1729.         <Mnemonic
  1730.            Form="lhzux rD,rA,rB"
  1731.            Notes="Load halfword and zero with update. The addressing mode is register indirect with index."/>
  1732.     </Instruction>
  1733.     <Instruction>
  1734.         <Details
  1735.            Name="Load Halfword and Zero Indexed"
  1736.            Description="EA is the sum (rA|0) + (rB). The halfword in memory addressed by EA is loaded into the low-order 16 bits of rD. The remaining bits in rD are cleared."
  1737.            OtherRegs=""
  1738.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         rD = (48)0 || MEM(EA, 2)"/>
  1739.         <Mnemonic
  1740.            Form="lhzx rD,rA,rB"
  1741.            Notes="Load halfword and zero. The addressing mode is register indirect with index."/>
  1742.     </Instruction>
  1743.     <Instruction>
  1744.         <Details
  1745.            Name="Load Multiple Word"
  1746.            Description="EA is the sum (rA|0) + d.&#10;&#10;    n = (32 - rD).&#10;&#10;n consecutive words starting at EA are loaded into the low-order 32 bits of GPRs rD through r31. The high-order 32 bits of these GPRs are cleared.&#10;&#10;EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined.&#10;&#10;If rA is in the range of registers specified to be loaded, including the case in which rA = '0', the instruction form is invalid.&#10;&#10;Note: In some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results."
  1747.            OtherRegs=""
  1748.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + EXTS(d)&#10;        r = rD&#10;        do while r &lt;= 31&#10;           GPR(r) = (32)0 || MEM(EA, 4)&#10;           r=r + 1&#10;           EA = EA + 4"/>
  1749.         <Mnemonic
  1750.            Form="lmw rD,d(rA)"
  1751.            Notes="Load multiple word. The addressing mode is register indirect with immediate index."/>
  1752.     </Instruction>
  1753.     <Instruction>
  1754.         <Details
  1755.            Name="Load String Word Immediate"
  1756.            Description="The effective address is (rA|0).&#10;&#10;Let n = NB if NB != 0, n = 32 if NB = '0'; n is the number of bytes to load.&#10;&#10;Let nr = CEIL(n / 4); nr is the number of registers to be loaded with data.&#10;&#10;n consecutive bytes starting at EA are loaded into GPRs rD through rD + nr - 1. Data is loaded into the low-order four bytes of each GPR; the high-order four bytes are cleared.&#10;&#10;Bytes are loaded left to right in each register. The sequence of registers wraps around to r0 if required. If the low-order four bytes of register rD + nr - 1 are only partially filled, the unfilled low-order byte(s) of that register are cleared.&#10;&#10;If rA is in the range of registers specified to be loaded, including the case in which rA = '0', the instruction form is invalid.&#10;&#10;Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. For additional information about data alignment exceptions. &#10;&#10;Note: In some implementations, this instruction is likely to have greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results."
  1757.            OtherRegs=""
  1758.            Pseudocode="         if rA = 0 then &#10;           EA = 0&#10;         else &#10;           EA = (rA)&#10;         if NB = 0 then &#10;           n = 32&#10;         else&#10;           n = NB&#10;         r = rD - 1&#10;         i = 32&#10;         do while n &gt; 0&#10;           if i = 32 then&#10;             r = r + 1 (mod 32)&#10;             GPR(r) = 0&#10;           GPR(r)[i-(i + 7)] = MEM(EA, 1)&#10;           i= i + 8&#10;           if i = 64 then &#10;             i = 32&#10;           EA = EA + 1&#10;           n = n-1"/>
  1759.         <Mnemonic
  1760.            Form="lswi rD,rA,NB"
  1761.            Notes="Load string word. The number of bytes to load is specified by an immediate. The addressing mode is register indirect."/>
  1762.     </Instruction>
  1763.     <Instruction>
  1764.         <Details
  1765.            Name="Load String Word Indexed"
  1766.            Description="EA is the sum (rA|0) + (rB). Let n = XER[57-63]; n is the number of bytes to load.&#10;&#10;Let nr = CEIL(n / 4); nr is the number of registers to receive data.&#10;&#10;If n &gt; 0, n consecutive bytes starting at EA are loaded into GPRs rD through rD + nr - 1. Data is loaded into the low-order four bytes of each GPR; the high-order four bytes are cleared.&#10;&#10;Bytes are loaded left to right in each register. The sequence of registers wraps around through r0 if required. If the low-order four bytes of rD + nr - 1 are only partially filled, the unfilled low-order byte(s) of that register are cleared. If n = '0', the contents of rD are undefined.&#10;&#10;If rA or rB is in the range of registers specified to be loaded, including the case in which rA = '0', either the system illegal instruction error handler is invoked or the results are boundedly undefined.&#10;&#10;If rD = rA or rD = rB, the instruction form is invalid.&#10;&#10;If rD and rA both specify GPR0, the form is invalid.&#10;&#10;Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. For additional information about data alignment exception. &#10;&#10;Note: In some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results."
  1767.            OtherRegs=""
  1768.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        n = XER[57-63]&#10;        r = rD - 1&#10;        i = 32&#10;        rD = undefined&#10;        do while n &gt; 0&#10;          if i = 32 then&#10;            r = r + 1 (mod 32)&#10;            GPR(r) = 0&#10;          GPR(r)[i-(i + 7)] = MEM(EA, 1)&#10;          i = i + 8&#10;          if i = 64 then &#10;            i = 32&#10;          EA = EA + 1&#10;          n = n-1"/>
  1769.         <Mnemonic
  1770.            Form="lswx rD,rA,rB"
  1771.            Notes="Load string word. The number of bytes to load is specified by XER[57-63]. The addressing mode is register indirect with index."/>
  1772.     </Instruction>
  1773.     <Instruction>
  1774.         <Details
  1775.            Name="Load Word Algebraic"
  1776.            Description="EA is the sum (rA|0) + (ds || '00'). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are filled with a copy of bit [0] of the loaded word."
  1777.            OtherRegs=""
  1778.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + EXTS(ds || '00')&#10;         rD = EXTS(MEM(EA, 4))"/>
  1779.         <Mnemonic
  1780.            Form="lwa rD,ds(rA)"
  1781.            Notes="Load sign-extended word. The addressing mode is register indirect with immediate index."/>
  1782.     </Instruction>
  1783.     <Instruction>
  1784.         <Details
  1785.            Name="Load Word and Reserve Indexed"
  1786.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The contents of the high-order 32 bits of rD are cleared.&#10;&#10;This instruction creates a reservation for use by a store word conditional indexed (stwcx.) instruction. The physical address computed from EA is associated with the reservation, and replaces any address previously associated with the reservation.&#10;&#10;EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions. &#10;&#10;When the RESERVE bit is set, the processor enables hardware snooping for the block of memory addressed by the RESERVE address. If the processor detects that another processor writes to the block of memory it has reserved, it clears the RESERVE bit. The stwcx. instruction will only do a store if the RESERVE bit is set. The stwcx. instruction sets the CR0[EQ] bit if the store was successful and clears it if it failed. The lwarx and stwcx. combination can be used for atomic read-modify-write sequences.&#10;&#10;Note: The atomic sequence is not guaranteed, but its failure can be detected if CR0[EQ] = '0' after the stwcx. instruction."
  1787.            OtherRegs=""
  1788.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        else&#10;        EA = b + (rB)&#10;        RESERVE = 1&#10;        RESERVE_ADDR = physical_addr(EA)&#10;        rD = (32)0 || MEM(EA,4)"/>
  1789.         <Mnemonic
  1790.            Form="lwarx rD,rA,rB"
  1791.            Notes="Load word and creates a reservation. The addressing mode is register indirect with index."/>
  1792.     </Instruction>
  1793.     <Instruction>
  1794.         <Details
  1795.            Name="Load Word Algebraic with Update Indexed"
  1796.            Description="EA is the sum (rA) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are filled with a copy of bit 0 of the loaded word.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0' or rA = rD, the instruction form is invalid."
  1797.            OtherRegs=""
  1798.            Pseudocode="         EA = (rA) + (rB)&#10;         rD = EXTS(MEM(EA, 4))&#10;         rA = EA"/>
  1799.         <Mnemonic
  1800.            Form="lwaux rD,rA,rB"
  1801.            Notes="Load sign-extended word with update. The addressing mode is register indirect with index."/>
  1802.     </Instruction>
  1803.     <Instruction>
  1804.         <Details
  1805.            Name="Load Word Algebraic Indexed"
  1806.            Description="EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are filled with a copy of bit 0 of the loaded word."
  1807.            OtherRegs=""
  1808.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        rD = EXTS(MEM(EA, 4))"/>
  1809.         <Mnemonic
  1810.            Form="lwax rD,rA,rB"
  1811.            Notes="Load sign-extended word. The addressing mode is register indirect with index."/>
  1812.     </Instruction>
  1813.     <Instruction>
  1814.         <Details
  1815.            Name="Load Word Byte-Reverse Indexed"
  1816.            Description="EA is the sum (rA|0) + rB. &#10;&#10;Bits 0-7 of the word in memory addressed by EA are loaded into the low-order 8 bits of rD. &#10;&#10;Bits [8-15] of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of rD. &#10;&#10;Bits [16-23] of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of rD. &#10;&#10;Bits [24-31] of the word in memory addressed by EA are loaded into the subsequent low-order 8 bits of rD. &#10;&#10;The high-order 32 bits of rD are cleared.&#10;&#10;The PowerPC Architecture cautions programmers that some implementations of the architecture may run the lwbrx instructions with greater latency than other types of load instructions."
  1817.            OtherRegs=""
  1818.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         rD = (32)0 || MEM(EA + 3, 1) || MEM(EA + 2, 1) || MEM(EA + 1, 1) || MEM(EA, 1)"/>
  1819.         <Mnemonic
  1820.            Form="lwbrx rD,rA,rB"
  1821.            Notes="Load byte-reversed halfword. The addressing mode is register indirect with index."/>
  1822.     </Instruction>
  1823.     <Instruction>
  1824.         <Details
  1825.            Name="Load Word and Zero"
  1826.            Description="EA is the sum (rA|0) + d. The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared."
  1827.            OtherRegs=""
  1828.            Pseudocode="          if rA = 0 then &#10;            b = 0&#10;          else&#10;            b = (rA)&#10;          EA = b + EXTS(d)&#10;          rD = (32)0 || MEM(EA, 4)"/>
  1829.         <Mnemonic
  1830.            Form="lwz rD,d(rA)"
  1831.            Notes="Load word and zero. The addressing mode is register indirect with immediate index."/>
  1832.     </Instruction>
  1833.     <Instruction>
  1834.         <Details
  1835.            Name="Load Word and Zero with Update"
  1836.            Description="EA is the sum (rA) + d. The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', or rA = rD, the instruction form is invalid."
  1837.            OtherRegs=""
  1838.            Pseudocode="         EA = rA + EXTS(d)&#10;         rD = (32)0 || MEM(EA, 4)&#10;         rA = EA"/>
  1839.         <Mnemonic
  1840.            Form="lwzu rD,d(rA)"
  1841.            Notes="Load word and zero with update. The addressing mode is register indirect with immediate index."/>
  1842.     </Instruction>
  1843.     <Instruction>
  1844.         <Details
  1845.            Name="Load Word and Zero with Update Indexed"
  1846.            Description="EA is the sum (rA) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', or rA = rD, the instruction form is invalid."
  1847.            OtherRegs=""
  1848.            Pseudocode="        EA = (rA) + (rB)&#10;        rD = (32)0 || MEM(EA, 4)&#10;        rA = EA"/>
  1849.         <Mnemonic
  1850.            Form="lwzux rD,rA,rB"
  1851.            Notes="Load word and zero with update. The addressing mode is register indirect with index."/>
  1852.     </Instruction>
  1853.     <Instruction>
  1854.         <Details
  1855.            Name="Load Word and Zero Indexed"
  1856.            Description="EA is the sum (rA|0) + (rB). The word in memory addressed by EA is loaded into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared."
  1857.            OtherRegs=""
  1858.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + rB&#10;         rD = (32)0 || MEM(EA, 4)"/>
  1859.         <Mnemonic
  1860.            Form="lwzx rD,rA,rB"
  1861.            Notes="Load word and zero. The addressing mode is register indirect with index."/>
  1862.     </Instruction>
  1863.     <Instruction>
  1864.         <Details
  1865.            Name="Move Condition Register Field"
  1866.            Description="The contents of condition register field crfS are copied into condition register field crfD. All other condition register fields remain unchanged."
  1867.            OtherRegs="* Condition Register (CR field specified by operand crfD):&#10;   Affected: LT, GT, EQ, SO"
  1868.            Pseudocode="        CR[(4 * crfD) to (4 * crfD + 3)] = CR[(4 * crfS) to (4 * crfS + 3)]"/>
  1869.         <Mnemonic
  1870.            Form="mcrf crfD,crfS"
  1871.            Notes="Move condition register field."/>
  1872.     </Instruction>
  1873.     <Instruction>
  1874.         <Details
  1875.            Name="Move to Condition Register from FPSCR"
  1876.            Description="The contents of FPSCR field crfS are copied to CR field crfD. All exception bits copied (except FEX and VX) are cleared in the FPSCR."
  1877.            OtherRegs="* Condition Register (CR field specified by operand crfD):&#10;    Affected: FX, FEX, VX, OX&#10;  * Floating-Point Status and Control Register:&#10;    Affected: FX, OX                        (if crfS = '0')&#10;    Affected: UX, ZX, XX, VXSNAN            (if crfS = '1')&#10;    Affected: VXISI, VXIDI, VXZDZ, VXIMZ (if crfS = '2')&#10;    Affected: VXVC                          (if crfS = '3')&#10;    Affected: VXSOFT, VXSQRT, VXCVI         (if crfS = '5')"
  1878.            Pseudocode=""/>
  1879.         <Mnemonic
  1880.            Form="mcrfs crfD,crfS"
  1881.            Notes="Move to condition register from FPSCR."/>
  1882.     </Instruction>
  1883.     <Instruction>
  1884.         <Details
  1885.            Name="Move from Condition Register"
  1886.            Description="The contents of the condition register (CR) are placed into the low-order 32 bits of rD. The high-order 32 bits of rD are cleared."
  1887.            OtherRegs=""
  1888.            Pseudocode="        rD = (32)0 || CR"/>
  1889.         <Mnemonic
  1890.            Form="mfcr rD"
  1891.            Notes="Move from condition register."/>
  1892.     </Instruction>
  1893.     <Instruction>
  1894.         <Details
  1895.            Name="Move from One Condition Register Field"
  1896.            Description="If exactly one bit of the CRM field is set to 1, let n be the position of that bit in the field (0 &lt;= n &lt;= 7). The contents of CR field n (CR bits [(4*n) to (4*n+3)]) are placed into bits [(32+4*n) to (32+4*n + 3)] of register rD and the contents of the remaining bits of register rD are undefined. Otherwise, the contents of register rD are undefined.&#10;&#10;Note: This form of the mfocrf instruction is intended to replace the old form of the instruction which will eventually be phased out of the architecture. The new form is backward compatible with most processors that comply with versions of the architecture that precede Version 2.01. On those processors, the new form is treated as the old form. However, on some processors that comply with versions of the architecture that precede Version 2.01 the new form of mfocrf may copy the contents of an SPR, possibly a privileged SPR, into register rD."
  1897.            OtherRegs=""
  1898.            Pseudocode="         rD = undefined&#10;         count = 0&#10;         do i = 0 to 7&#10;           if CRM[i] = 1 then&#10;           n = i&#10;           count = count + 1&#10;         if count = 1 then &#10;           rD[(32 + 4 * n) - (32 + 4 * n + 3)] = CR[( 4 * n) - (4 * n + 3)]"/>
  1899.         <Mnemonic
  1900.            Form="mfocrf rD,CRM"
  1901.            Notes="Move from one condition register field."/>
  1902.     </Instruction>
  1903.     <Instruction>
  1904.         <Details
  1905.            Name="Move from FPSCR"
  1906.            Description="The contents of the floating-point status and control register (FPSCR) are placed into the low-order bits of register frD. The high-order bits of register frD are undefined."
  1907.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                (if Rc = '1')"
  1908.            Pseudocode="        frD[32-63]= FPSCR"/>
  1909.         <Mnemonic
  1910.            Form="mffs frD"
  1911.            Notes="Move from FPSCR."/>
  1912.         <Mnemonic
  1913.            Form="mffs. frD"
  1914.            Notes="Move from FPSCR and record."/>
  1915.     </Instruction>
  1916.     <Instruction>
  1917.         <Details
  1918.            Name="Move from Machine State Register"
  1919.            Description="The contents of the MSR are placed into rD.&#10;&#10;This is a supervisor-level instruction."
  1920.            OtherRegs=""
  1921.            Pseudocode="        rD = MSR"/>
  1922.         <Mnemonic
  1923.            Form="mfmsr rD"
  1924.            Notes="Move from machine state register."/>
  1925.     </Instruction>
  1926.     <Instruction>
  1927.         <Details
  1928.            Name="Move from Special-Purpose Register"
  1929.            Description="In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as shown below. The contents of the designated special-purpose register are placed into rD.&#10;&#10;For special-purpose registers that are 32 bits long, the low-order 32 bits of rD receive the contents of the special-purpose register and the high-order 32 bits of rD are cleared.&#10;&#10;Decimal: spr[5-9] spr[0-4] - Register Name&#10;1: 00000 00001 - XER&#10;8: 00000 01000 - LR&#10;9: 00000 01001 - CTR&#10;&#10;Note: The order of the two 5-bit halves of the SPR number is reversed compared with the actual instruction coding.&#10;&#10;If the SPR field contains any value other than one of the values shown above (and the processor is in user mode), one of the following occurs:&#10; * The system illegal instruction error handler is invoked.&#10; * The system supervisor-level instruction error handler is invoked.&#10; * The results are boundedly undefined."
  1930.            OtherRegs=""
  1931.            Pseudocode="         n = spr[5-9] || spr[0-4]&#10;         if length (SPR(n)) = 64 then&#10;           rD = SPR(n)&#10;         else&#10;           rD = (32)0 || SPR(n)"/>
  1932.         <Mnemonic
  1933.            Form="mfspr rD,SPR"
  1934.            Notes="Move from special-purpose register."/>
  1935.         <Mnemonic
  1936.            Form="mfxer rD"
  1937.            Notes="Equivalent to: mfspr rD,1."/>
  1938.         <Mnemonic
  1939.            Form="mflr rD"
  1940.            Notes="Equivalent to: mfspr rD,8."/>
  1941.         <Mnemonic
  1942.            Form="mfctr rD"
  1943.            Notes="Equivalent to: mfspr rD,9."/>
  1944.     </Instruction>
  1945.     <Instruction>
  1946.         <Details
  1947.            Name="Move from Segment Register"
  1948.            Description="The contents of the low-order 27 bits of the VSID field, and the contents of the KS, KP, N, and L fields, of the SLB entry specified by SR are placed into register rD, as follows:&#10;&#10;SLBE Bit(s): Copied to - SLB Field&#10;62-88: rD[37-63] - VSID[25-51]&#10;89-91: rD[33-35] - KS KP N&#10;92: rD[36] - L (SBE[L] must be '0')&#10;&#10;rD[32] is set to '0'. The contents of rD[0-31] are undefined.&#10;&#10;This is a supervisor-level instruction.&#10;&#10;This instruction must be used only to read an SLB entry that was, or could have been, created by mtsr or mtsrin and has not subsequently been invalidated (i.e., an SLB entry in which ESID&lt; 16, V= '1', VSID&lt; 227, L= '0', and C= '0'). Otherwise the contents of register rD are undefined.&#10;&#10;Note: MSR[SF] must be '0' when this instruction is executed. Otherwise, the results are boundedly undefined."
  1949.            OtherRegs=""
  1950.            Pseudocode=""/>
  1951.         <Mnemonic
  1952.            Form="mfsr rD,SR"
  1953.            Notes="Move from segment register."/>
  1954.     </Instruction>
  1955.     <Instruction>
  1956.         <Details
  1957.            Name="Move from Segment Register Indirect"
  1958.            Description="The contents of the low-order 27 bits of the VSID field, and the contents of the KS, KP, N, and L fields, of the SLB entry specified by rB[32:35] are placed into register rD, as follows:&#10;&#10;SLBE Bit(s): Copied to - SLB Field&#10;62-88: rD[37-63] - VSID[25-51]&#10;89-91: rD[33-35] - KS KP N&#10;92: rD[36] - L (SBE[L] must be '0')&#10;&#10;rD[32] is set to '0'. The contents of rD[0-31] are undefined.&#10;&#10;This is a supervisor-level instruction.&#10;&#10;Note: MSR[SF] must be '0' when this instruction is executed. Otherwise, the results are boundedly undefined.&#10;&#10;This instruction must be used only to read an SLB entry that was, or could have been, created by mtsr or mtsrin and has not subsequently been invalidated (i.e., an SLB entry in which ESID&lt; 16, V= '1', VSID&lt; 227, L= '0', and C= '0'). Otherwise the contents of register rD are undefined."
  1959.            OtherRegs=""
  1960.            Pseudocode=""/>
  1961.         <Mnemonic
  1962.            Form="mfsrin rD,rB"
  1963.            Notes="Move from segment register indirect."/>
  1964.     </Instruction>
  1965.     <Instruction>
  1966.         <Details
  1967.            Name="Move from Time Base"
  1968.            Description="The TBR field denotes either the Time Base or Time Base Upper, encoded as shown below. The contents of the designated register are placed into register rD. When reading Time Base Upper, the high-order 32 bits of register RT are set to zero.&#10;&#10;Decimal: spr[5-9] spr[0-4] - Register Name (Access)&#10;268: 01000 01100 - TBL (User)&#10;269: 01000 01101 - TBU (User)&#10;&#10;Note: The order of the two 5-bit halves of the TBR number is reversed.&#10;&#10;If the TBR field contains any value other than one of the values shown in above, then one of the following occurs:&#10; * The system illegal instruction error handler is invoked.&#10; * The system supervisor-level instruction error handler is invoked.&#10; * The results are boundedly undefined.&#10;&#10;It is important to note that some implementations may implement mftb and mfspr identically, therefore, a TBR number must not match an SPR number."
  1969.            OtherRegs=""
  1970.            Pseudocode="         n = tbr[5-9] || tbr[0-4]&#10;         if n = 268 then&#10;           rD = TB&#10;         else if n = 269 then&#10;           rD = (32)0 || TB[0-31]"/>
  1971.         <Mnemonic
  1972.            Form="mftb rD,TBR"
  1973.            Notes="Move from time base."/>
  1974.         <Mnemonic
  1975.            Form="mftbu rD"
  1976.            Notes="Equivalent to: mftb rD,269."/>
  1977.     </Instruction>
  1978.     <Instruction>
  1979.         <Details
  1980.            Name="Move to Condition Register Fields"
  1981.            Description="The contents of the low-order 32 bits of rS are placed into the condition register under control of the field mask specified by CRM. The field mask identifies the 4-bit fields affected. Let i be an integer in the range 0-7. If CRM(i) = '1', CR field i (CR bits [(4 * i) through (4 * i + 3)]) is set to the contents of the corresponding field of the low-order 32 bits of rS.&#10;&#10;Note: Updating a subset of the eight fields of the condition register may have a substantially poorer performance on some implementations than updating all of the fields."
  1982.            OtherRegs="CR fields selected by mask"
  1983.            Pseudocode="        mask = (4)(CRM[0]) || (4)(CRM[1]) ||... (4)(CRM[7])&#10;        CR = (rS[32-63] &amp; mask) | (CR &amp; ! mask)"/>
  1984.         <Mnemonic
  1985.            Form="mtcrf CRM,rS"
  1986.            Notes="Move to condition register fields"/>
  1987.         <Mnemonic
  1988.            Form="mtcr rS"
  1989.            Notes="Move to condition register. Equivalent to: mtcrf 0xFF,rS."/>
  1990.     </Instruction>
  1991.     <Instruction>
  1992.         <Details
  1993.            Name="Move to FPSCR Bit"
  1994.            Description="Bit crbD of the FPSCR is cleared."
  1995.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPSCR bit crbD&#10;      Note: Bits [1] and [2] (FEX and VX) cannot be explicitly cleared."
  1996.            Pseudocode=""/>
  1997.         <Mnemonic
  1998.            Form="mtfsb0 crbD"
  1999.            Notes="Clear specified FPSCR bit."/>
  2000.         <Mnemonic
  2001.            Form="mtfsb0. crbD"
  2002.            Notes="Clear specified FPSCR bit and record."/>
  2003.     </Instruction>
  2004.     <Instruction>
  2005.         <Details
  2006.            Name="Move to FPSCR Bit"
  2007.            Description="Bit crbD of the FPSCR is set."
  2008.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPSCR bit crbD and FX&#10;      Note: Bits [1] and [2] (FEX and VX) cannot be explicitly set."
  2009.            Pseudocode=""/>
  2010.         <Mnemonic
  2011.            Form="mtfsb1 crbD"
  2012.            Notes="Set specified FPSCR bit."/>
  2013.         <Mnemonic
  2014.            Form="mtfsb1. crbD"
  2015.            Notes="Set specified FPSCR bit and record."/>
  2016.     </Instruction>
  2017.     <Instruction>
  2018.         <Details
  2019.            Name="Move to FPSCR Fields"
  2020.            Description="The low-order 32 bits of frB are placed into the FPSCR under control of the field mask specified by FM. The field mask identifies the 4-bit fields affected. Let i be an integer in the range 0-7. If FM[i] = '1', FPSCR field i(FPSCR bits [(4 * i) through (4 * i + 3)]) is set to the contents of the corresponding field of the low-order 32 bits of register frB.&#10;&#10;FPSCR[FX] is altered only if FM[0] = '1'.&#10;&#10;Note: Updating fewer than all eight fields of the FPSCR may have a substantially poorer performance on some implementations than updating all the fields.&#10;&#10;When FPSCR[0-3] is specified, bits [0] (FX) and [3] (OX) are set to the values of frB[32] and frB[35] (that is, even if this instruction causes OX to change from '0' to '1', FX is set from frB[32] and not by the usual rule that FX is set when an exception bit changes from '0' to '1'). Bits [1] and [2] (FEX and VX) are set according to the usual rule and not from frB[33-34]."
  2021.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                 (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPSCR fields selected by mask"
  2022.            Pseudocode=""/>
  2023.         <Mnemonic
  2024.            Form="mtfsf FM,frB"
  2025.            Notes="Move to FPSCR fields."/>
  2026.         <Mnemonic
  2027.            Form="mtfsf. FM,frB"
  2028.            Notes="Move to FPSCR fields and record."/>
  2029.     </Instruction>
  2030.     <Instruction>
  2031.         <Details
  2032.            Name="Move to FPSCR Field Immediate"
  2033.            Description="The value of the IMM field is placed into FPSCR field crfD.&#10;&#10;FPSCR[FX] is altered only if crfD = '0'.&#10;&#10;When FPSCR[0-3] is specified, bits [0] (FX) and [3] (OX) are set to the values of IMM[0] and IMM[3] (that is, even if this instruction causes OX to change from '0' to '1', FX is set from IMM[0] and not by the usual rule that FX is set when an exception bit changes from '0' to '1'). Bits [1] and [2] (FEX and VX) are set according to the usual rule and not from IMM[1-2]."
  2034.            OtherRegs="* Condition Register (CR1 field):&#10;   Affected: FX, FEX, VX, OX                     (if Rc = '1')&#10; * Floating-Point Status and Control Register:&#10;   Affected: FPSCR field crfD"
  2035.            Pseudocode="          FPSCR[crfD] = IMM"/>
  2036.         <Mnemonic
  2037.            Form="mtfsfi crfD,IMM"
  2038.            Notes="Set specified FPSCR Field to immediate value."/>
  2039.         <Mnemonic
  2040.            Form="mtfsfi. crfD,IMM"
  2041.            Notes="Set specified FPSCR Field to immediate value and record."/>
  2042.     </Instruction>
  2043.     <Instruction>
  2044.         <Details
  2045.            Name="Move to Machine State Register"
  2046.            Description="The MSR is set based on the contents of register rS and the L field.&#10;&#10;L= '0'.  The result of ORing bits [58] and [49] of register rS is placed into MSR[58]. The result of ORing bits [59] and [49] of register rS is placed into MSR[59]. Bits [32-47, 49, 50, 52-57, 60-63] of register rS are placed into the corresponding bits of the MSR. The remaining bits of the MSR are unchanged.&#10;&#10;L= '1'.  Bits [48, 62] of rS are placed into the corresponding bits of the MSR. The remaining bits of the MSR are unchanged.&#10;&#10;This instruction is a supervisor-level instruction. If L= '0' this instruction is context synchronizing except with respect to alterations to the [LE] bit. If L= '1' this instruction is execution synchronizing; in addition, the alterations of the [EE] and [RI] bits take effect as soon as the instruction completes.&#10;&#10;Note: A reference to an mtmsr instruction that modifies an MSR bit other than the EE or RI bit implies L= '0'.&#10;&#10;Note: mtmsr serves as both a basic and an extended mnemonic. The assembler will recognize an mtmsr mnemonic with two operands as the basic form, and an mtmsr mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be '0'."
  2047.            OtherRegs="MSR"
  2048.            Pseudocode="         MSR = (rS)&#10;         if L = 0 then&#10;           MSR[58] = (rS[58] | rS[49])&#10;           MSR[59] = (rS[59] | rS[49])&#10;           MSR[32-47,49,50,52-57,60-63] = rS[32-47,49,50,52-57,60-63]&#10;         else&#10;           MSR[48,62] = rS[48,62]"/>
  2049.         <Mnemonic
  2050.            Form="mtmsr rS,L"
  2051.            Notes="Move to machine state register."/>
  2052.     </Instruction>
  2053.     <Instruction>
  2054.         <Details
  2055.            Name="Move to Machine State Register Doubleword"
  2056.            Description="The MSR is set based on the contents of register rS and the L field.&#10;&#10;L= '0'. The result of ORing bits [0] and [1] of register rS is placed into MSR[0]. The result of ORing bits [59] and [49] of register rS is placed into MSR[59]. Bits [1-2, 4-47, 49, 50, 52-57, 60-63] of register rS are placed into the corresponding bits of the MSR. The remaining bits of the MSR are unchanged.&#10;&#10;L= '1'. Bits [48, 62] of rS are placed into the corresponding bits of the MSR. The remaining bits of the MSR are unchanged.&#10;&#10;This instruction is a supervisor-level instruction. If L= '0' this instruction is context synchronizing except with respect to alterations to the [LE] bit. If L= '1' this instruction is execution synchronizing; in addition, the alterations of the [EE] and [RI] bits take effect as soon as the instruction completes.&#10;&#10;Note: Processors designed prior to Version 2.01 of the architecture ignore the L field. These processors set the MSR as if L were '0', and perform synchronization as if L were '1'. Therefore software that uses mtmsrd and runs on such processors must obey the following rules.&#10;&#10; 1. If L= '1', the contents of bits of register rS other than bits [48] and [62] must be such that if L were '0' the instruction would not alter the contents of the corresponding MSR bits.&#10; 2. If L = '0' and the instruction alters the contents of any of the MSR bits listed below, the instruction must be followed by a context synchronizing instruction or event in order to ensure that the context alteration caused by the mtmsrd instruction has taken effect on such processors.&#10;&#10;To obtain the best performance on processors, if the context synchronizing instruction is isync the isync should immediately follow the mtmsrd. (Some such processors treat an isync instruction that immediately follows an mtmsrd instruction having L = '0' as a no-op, thereby avoiding the performance penalty of a second context synchronization.)&#10;&#10;Note: mtmsrd serves as both a basic and an extended mnemonic. The Assembler will recognize an mtmsrd mnemonic with two operands as the basic form, and an mtmsrd mnemonic with one operand as the extended form. In the extended form the L operand is omitted and assumed to be '0'."
  2057.            OtherRegs="MSR"
  2058.            Pseudocode=""/>
  2059.         <Mnemonic
  2060.            Form="mtmsrd rS,L"
  2061.            Notes="Move to machine state register doubleword."/>
  2062.     </Instruction>
  2063.     <Instruction>
  2064.         <Details
  2065.            Name="Move to One Condition Register Field"
  2066.            Description="If exactly one bit of the CRM field is set to 1, let n be the position of that bit in the field (0 &lt;= n &lt;= 7). The contents of bits [32+4*n to 32+4*n + 3] of register rS are placed into CR field n (CR bits [4*n to 4*n+3]). Otherwise, the contents of the Condition Register are undefined.&#10;&#10;Note: This form of the mtocrf instruction is intended to replace the old form of the instruction (mtcrf) which will eventually be phased out of the architecture. The new form is backward compatible with most processors that comply with versions of the architecture prior to Version 2.01. On those processors, the new form is treated as the old form. However, on some processors that comply with versions of the architecture that precede Version 2.01 the new form of mtocrf may cause the system illegal instruction error handler to be invoked."
  2067.            OtherRegs="CR fields selected by CRM"
  2068.            Pseudocode="         count = 0&#10;         do i = 0 to 7&#10;           if CRM[i] = 1 then&#10;           n = i&#10;           count = count + 1&#10;         if count = 1 then &#10;           CR[4 * n to 4 * n + 3] = rS[32 + 4 * n to 32 + 4 * n + 3]&#10;         else &#10;           CR = undefined"/>
  2069.         <Mnemonic
  2070.            Form="mtocrf CRM,rS"
  2071.            Notes="Move to one condition register field."/>
  2072.     </Instruction>
  2073.     <Instruction>
  2074.         <Details
  2075.            Name="Move to Special-Purpose Register"
  2076.            Description="In the PowerPC UISA, the SPR field denotes a special-purpose register, encoded as shown below. The contents of rS are placed into the designated special-purpose register. For special-purpose registers that are 32 bits long, the low-order 32 bits of rS are placed into the SPR.&#10;&#10;Decimal: spr[5-9] spr[0-4] - Register Name&#10;1: 00000 00001 - XER&#10;8: 00000 01000 - LR&#10;9: 00000 01001 - CTR&#10;&#10;Note:&#10; 1. The order of the two 5-bit halves of the SPR number is reversed compared with actual instruction coding.&#10;&#10;If the SPR field contains any value other than one of the values shown above, and the processor is operating in user mode, one of the following occurs:&#10; * The system illegal instruction error handler is invoked.&#10; * The system supervisor instruction error handler is invoked.&#10; * The results are boundedly undefined."
  2077.            OtherRegs="See above"
  2078.            Pseudocode="           n = spr[5-9] || spr[0-4]&#10;           if length (SPR(n)) = 64 then&#10;             SPR(n) = (rS)&#10;           else&#10;             SPR(n) = rS[32-63]"/>
  2079.         <Mnemonic
  2080.            Form="mtspr SPR,rS"
  2081.            Notes="Move to special-purpose register."/>
  2082.         <Mnemonic
  2083.            Form="mtxer rS"
  2084.            Notes="Move to XER. Equivalent to: mtspr 1,rS."/>
  2085.         <Mnemonic
  2086.            Form="mtlr rS"
  2087.            Notes="Move to link register. Equivalent to: mtspr 8,rS."/>
  2088.         <Mnemonic
  2089.            Form="mtctr rS"
  2090.            Notes="Move to count register. Equivalent to: mtspr 9,rS."/>
  2091.         <Mnemonic
  2092.            Form="mtdsisr rS"
  2093.            Notes="Move to DSISR. Equivalent to: mtspr 18,rS."/>
  2094.         <Mnemonic
  2095.            Form="mtdar rS"
  2096.            Notes="Move to data address register. Equivalent to: mtspr 19,rS."/>
  2097.         <Mnemonic
  2098.            Form="mtdec rS"
  2099.            Notes="Move to decrementer. Equivalent to: mtspr 22,rS."/>
  2100.         <Mnemonic
  2101.            Form="mtsdr1 rS"
  2102.            Notes="Move to SDR1. Equivalent to: mtspr 25,rS."/>
  2103.         <Mnemonic
  2104.            Form="mtsrr0 rS"
  2105.            Notes="Move to save and restore register 0. Equivalent to: mtspr 26,rS."/>
  2106.         <Mnemonic
  2107.            Form="mtsrr1 rS"
  2108.            Notes="Move to save and restore register 1. Equivalent to: mtspr 27,rS."/>
  2109.         <Mnemonic
  2110.            Form="mtasr rS"
  2111.            Notes="Move to address space register. Equivalent to: mtspr 280,rS."/>
  2112.         <Mnemonic
  2113.            Form="mtear rS"
  2114.            Notes="Move to external access register. Equivalent to: mtspr 282,rS."/>
  2115.         <Mnemonic
  2116.            Form="mttbl rS"
  2117.            Notes="Move to time base lower. Equivalent to: mtspr 284,rS."/>
  2118.         <Mnemonic
  2119.            Form="mttbu rS"
  2120.            Notes="Move to time base upper. Equivalent to: mtspr 285,rS."/>
  2121.         <Mnemonic
  2122.            Form="mfspr rD,SPR"
  2123.            Notes="Move from special-purpose register."/>
  2124.         <Mnemonic
  2125.            Form="mfxer rD"
  2126.            Notes="Move from XER. Equivalent to: mtspr rD,1."/>
  2127.         <Mnemonic
  2128.            Form="mflr rD"
  2129.            Notes="Move from link register. Equivalent to: mtspr rD,8."/>
  2130.         <Mnemonic
  2131.            Form="mfctr rD"
  2132.            Notes="Move from count register. Equivalent to: mtspr rD,9."/>
  2133.         <Mnemonic
  2134.            Form="mfdsisr rD"
  2135.            Notes="Move from DSISR. Equivalent to: mtspr rD,18."/>
  2136.         <Mnemonic
  2137.            Form="mfdar rD"
  2138.            Notes="Move from data address register. Equivalent to: mtspr rD,19."/>
  2139.         <Mnemonic
  2140.            Form="mfdec rD"
  2141.            Notes="Move from decrementer. Equivalent to: mtspr rD,22."/>
  2142.         <Mnemonic
  2143.            Form="mfsdr1 rD"
  2144.            Notes="Move from SDR1. Equivalent to: mtspr rD,25."/>
  2145.         <Mnemonic
  2146.            Form="mfsrr0 rD"
  2147.            Notes="Move from save and restore register 0. Equivalent to: mtspr rD,26."/>
  2148.         <Mnemonic
  2149.            Form="mfsrr1 rD"
  2150.            Notes="Move from save and restore register 1. Equivalent to: mtspr rD,27."/>
  2151.         <Mnemonic
  2152.            Form="mfasr rD"
  2153.            Notes="Move from address space register. Equivalent to: mtspr rD,280."/>
  2154.         <Mnemonic
  2155.            Form="mfear rD"
  2156.            Notes="Move from external access register. Equivalent to: mtspr rD,282."/>
  2157.         <Mnemonic
  2158.            Form="mftbl rD"
  2159.            Notes="Move from time base lower. Equivalent to: mtspr rD,284."/>
  2160.         <Mnemonic
  2161.            Form="mftbu rD"
  2162.            Notes="Move from time base upper. Equivalent to: mtspr rD,285."/>
  2163.     </Instruction>
  2164.     <Instruction>
  2165.         <Details
  2166.            Name="Move to Segment Register"
  2167.            Description="This is a supervisor-level instruction.&#10;&#10;Note: MSR[SF] must be '0' when this instruction is executed. Otherwise, the results are boundedly undefined.&#10;&#10;The SLB entry specified by SR is loaded from register rS, as follows.&#10;SLBE Bit(s): Set to - SLB Field(s)&#10;0-31: 0x0000 0000 - ESID[0-31]&#10;32-35: SR - ESID[32-35]&#10;36: '1' -  V&#10;37-61: 0x00_0000 || 0b0 -  VSID[0-24]&#10;62-88: rS[37-63] - VSID[25-51]&#10;89-91: rS[33-35] - KS KP N&#10;92: rS[36] - L (rS[36] must be '0')&#10;93: '0' - C"
  2168.            OtherRegs=""
  2169.            Pseudocode=""/>
  2170.         <Mnemonic
  2171.            Form="mtsr SR,rS"
  2172.            Notes="Move to segment register."/>
  2173.     </Instruction>
  2174.     <Instruction>
  2175.         <Details
  2176.            Name="Move to Segment Register Indirect"
  2177.            Description="This is a supervisor-level instruction.&#10;&#10;Note: MSR[SF] must be '0' when this instruction is executed. Otherwise, the results are boundedly undefined.&#10;&#10;The SLB entry specified by rB[32-35] is loaded from register rS, as follows.&#10;SLBE Bit(s): Set to - SLB Field(s)&#10;0-31: 0x0000 0000 - ESID[0-31]&#10;32-35: SR - ESID[32-35]&#10;36: '1' -  V&#10;37-61: 0x00_0000 || 0b0 -  VSID[0-24]&#10;62-88: rS[37-63] - VSID[25-51]&#10;89-91: rS[33-35] - KS KP N&#10;92: rS[36] - L (rS[36] must be '0')&#10;93: '0' - C"
  2178.            OtherRegs=""
  2179.            Pseudocode=""/>
  2180.         <Mnemonic
  2181.            Form="mtsrin rS,rB"
  2182.            Notes="Move to segment register indirect."/>
  2183.     </Instruction>
  2184.     <Instruction>
  2185.         <Details
  2186.            Name="Multiply High Doubleword"
  2187.            Description="The 64-bit operands are (rA) and (rB). The high-order 64 bits of the 128-bit product of the operands are placed into rD.&#10;&#10;Both the operands and the product are interpreted as signed integers.&#10;&#10;This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value."
  2188.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO              (if Rc = '1')&#10;      Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 64-bit&#10;      result."
  2189.            Pseudocode="         prod[0-127] = (rA) * (rB)&#10;         rD = prod[0-63]"/>
  2190.         <Mnemonic
  2191.            Form="mulhd rD,rA,rB"
  2192.            Notes="Multiply signed doubleword. The result is the high-order 64 bits of the 128 bit product."/>
  2193.         <Mnemonic
  2194.            Form="mulhd. rD,rA,rB"
  2195.            Notes="Multiply signed doubleword and record. The result is the high-order 64 bits of the 128 bit product."/>
  2196.     </Instruction>
  2197.     <Instruction>
  2198.         <Details
  2199.            Name="Multiply High Doubleword Unsigned"
  2200.            Description="The 64-bit operands are (rA) and (rB). The high-order 64 bits of the 128-bit product of the operands are placed into rD.&#10;&#10;Both the operands and the product are interpreted as unsigned integers, except that if Rc = '1' the first three bits of CR0 field are set by signed comparison of the result to zero.&#10;&#10;This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value."
  2201.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO              (if Rc = '1')&#10;      Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 64-bit&#10;      result."
  2202.            Pseudocode="         prod[0-127] = (rA) * (rB)&#10;         rD = prod[0-63]"/>
  2203.         <Mnemonic
  2204.            Form="mulhdu rD,rA,rB"
  2205.            Notes="Multiply unsigned doubleword. The result is the high-order 64 bits of the 128 bit product."/>
  2206.         <Mnemonic
  2207.            Form="mulhdu. rD,rA,rB"
  2208.            Notes="Multiply unsigned doubleword and record. The result is the high-order 64 bits of the 128 bit product."/>
  2209.     </Instruction>
  2210.     <Instruction>
  2211.         <Details
  2212.            Name="Multiply High Word"
  2213.            Description="The 64-bit product is formed from the contents of the low-order 32 bits of rA and rB. The high-order 32 bits of the 64-bit product of the operands are placed into the low-order 32 bits of rD. The high-order 32 bits of rD are undefined.&#10;&#10;Both the operands and the product are interpreted as signed integers.&#10;&#10;This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value."
  2214.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO               (if Rc = '1')&#10;   LT, GT, EQ undefined                   (if Rc = '1' and 64-bit mode)&#10;      Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 32-bit&#10;      result."
  2215.            Pseudocode="         prod[0-63] = rA[32-63] * rB[32-63]&#10;         rD[32-63] = prod[0-31]&#10;         rD[0-31] = undefined"/>
  2216.         <Mnemonic
  2217.            Form="mulhw rD,rA,rB"
  2218.            Notes="Multiply signed word. The result is the high-order 32 bits of the 64 bit product."/>
  2219.         <Mnemonic
  2220.            Form="mulhw. rD,rA,rB"
  2221.            Notes="Multiply signed word and record. The result is the high-order 32 bits of the 64 bit product."/>
  2222.     </Instruction>
  2223.     <Instruction>
  2224.         <Details
  2225.            Name="Multiply High Word Unsigned"
  2226.            Description="The 32-bit operands are the contents of the low-order 32 bits of rA and rB. The high-order 32 bits of the 64-bit product of the operands are placed into the low-order 32 bits of rD. The high-order 32 bits of rD are undefined.&#10;&#10;Both the operands and the product are interpreted as unsigned integers, except that if Rc = '1' the first three bits of CR0 field are set by signed comparison of the result to zero.&#10;&#10;This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value."
  2227.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO               (if Rc = '1')&#10;   LT, GT, EQ undefined                   (if Rc = '1' and 64-bit mode)&#10;      Note: The setting of CR0 bits LT, GT, and EQ is mode-dependent, and reflects overflow of the 32-bit&#10;      result."
  2228.            Pseudocode="         prod[0-63] = rA[32-63] * rB[32-63]&#10;         rD[32-63] = prod[0-31]&#10;         rD[0-31] = undefined"/>
  2229.         <Mnemonic
  2230.            Form="mulhwu rD,rA,rB"
  2231.            Notes="Multiply unsigned word. The result is the high-order 32 bits of the 64 bit product."/>
  2232.         <Mnemonic
  2233.            Form="mulhwu. rD,rA,rB"
  2234.            Notes="Multiply unsigned word and record. The result is the high-order 32 bits of the 64 bit product."/>
  2235.     </Instruction>
  2236.     <Instruction>
  2237.         <Details
  2238.            Name="Multiply Low Doubleword"
  2239.            Description="The 64-bit operands are the contents of rA and rB. The low-order 64 bits of the 128-bit product of the operands are placed into rD.&#10;&#10;Both the operands and the product are interpreted as signed integers. The low-order 64 bits of the product are independent of whether the operands are regarded as signed or unsigned 64-bit integers. If OE = '1', then OV is set if the product cannot be represented in 64 bits.&#10;&#10;This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value."
  2240.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')&#10;      Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).&#10; * XER:&#10;   Affected: SO, OV                        (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the 64-bit&#10;      result."
  2241.            Pseudocode="         prod[0-127] = (rA) *       (rB)&#10;         rD = prod[64-127]"/>
  2242.         <Mnemonic
  2243.            Form="mulld rD,rA,rB"
  2244.            Notes="Multiply signed doubleword. The result is the low-order 64 bits of the 128 bit product."/>
  2245.         <Mnemonic
  2246.            Form="mulld. rD,rA,rB"
  2247.            Notes="Multiply signed doubleword and record. The result is the low-order 64 bits of the 128 bit product."/>
  2248.         <Mnemonic
  2249.            Form="mulldo rD,rA,rB"
  2250.            Notes="Multiply signed doubleword and overflow. The result is the low-order 64 bits of the 128 bit product."/>
  2251.         <Mnemonic
  2252.            Form="mulldo. rD,rA,rB"
  2253.            Notes="Multiply signed doubleword overflow and record. The result is the low-order 64 bits of the 128 bit product."/>
  2254.     </Instruction>
  2255.     <Instruction>
  2256.         <Details
  2257.            Name="Multiply Low Immediate"
  2258.            Description="The 64-bit first operand is (rA). The 64-bit second operand is the sign-extended value of the SIMM field. The low-order 64-bits of the 128-bit product of the operands are placed into rD.&#10;&#10;Both the operands and the product are interpreted as signed integers. The low-order 64 bits of the product are calculated independently of whether the operands are treated as signed or unsigned 64-bit integers.&#10;&#10;This instruction can be used with mulhdx or mulhwx to calculate a full 128-bit product."
  2259.            OtherRegs=""
  2260.            Pseudocode="        prod[0-127] = (rA) * EXTS(SIMM)&#10;        rD = prod[64-127]"/>
  2261.         <Mnemonic
  2262.            Form="mulli rD,rA,SIMM"
  2263.            Notes="Multiply signed doubleword with sign-extended immediate. The result is the low-order 64 bits of the 128 bit product."/>
  2264.     </Instruction>
  2265.     <Instruction>
  2266.         <Details
  2267.            Name="Multiply Low Word"
  2268.            Description="The 32-bit operands are the contents of the low-order 32 bits of rA and rB. The low-order 32 bits of the 64-bit product (rA) * (rB) are placed into rD.&#10;&#10;If [OE] = '1', then [OV] is set if the product cannot be represented in 32 bits. Both the operands and the product are interpreted as signed integers.&#10;&#10;This instruction can be used with mulhwx to calculate a full 64-bit product.&#10;&#10;Note: This instruction may execute faster on some implementations if rB contains the operand having the smaller absolute value."
  2269.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')&#10;      Note: CR0 field may not reflect the infinitely precise result if overflow occurs (see XER below).&#10; * XER:&#10;   Affected: SO, OV                        (if OE = '1')&#10;      Note: The setting of the affected bits in the XER is mode-independent, and reflects overflow of the low-&#10;      order 32-bit result."
  2270.            Pseudocode="         rD = rA[32-63] * rB[32-63]"/>
  2271.         <Mnemonic
  2272.            Form="mullw rD,rA,rB"
  2273.            Notes="Multiply signed word. The result is the low-order 32 bits of the 64 bit product."/>
  2274.         <Mnemonic
  2275.            Form="mullw. rD,rA,rB"
  2276.            Notes="Multiply signed word and record. The result is the low-order 32 bits of the 64 bit product."/>
  2277.         <Mnemonic
  2278.            Form="mullwo rD,rA,rB"
  2279.            Notes="Multiply signed word and overflow. The result is the low-order 32 bits of the 64 bit product."/>
  2280.         <Mnemonic
  2281.            Form="mullwo. rD,rA,rB"
  2282.            Notes="Multiply signed word overflow and record. The result is the low-order 32 bits of the 64 bit product."/>
  2283.     </Instruction>
  2284.     <Instruction>
  2285.         <Details
  2286.            Name="NAND"
  2287.            Description="The contents of rS are ANDed with the contents of rB and the complemented result is placed into rA.&#10;&#10;A nand with rS = rB can be used to obtain the one's complement."
  2288.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO            (if Rc = '1')"
  2289.            Pseudocode="        rA = ! ((rS) &amp; (rB))"/>
  2290.         <Mnemonic
  2291.            Form="nand rA,rS,rB"
  2292.            Notes="NAND."/>
  2293.         <Mnemonic
  2294.            Form="nand. rA,rS,rB"
  2295.            Notes="NAND and record."/>
  2296.     </Instruction>
  2297.     <Instruction>
  2298.         <Details
  2299.            Name="Negate"
  2300.            Description="The value '1' is added to the complement of the value in rA, and the resulting two's complement is placed into rD.&#10;&#10;If executing in the default 64-bit mode and rA contains the most negative 64-bit number (0x8000_0000_0000_0000), the result is the most negative number and, if OE = '1', OV is set. Similarly, if executing in 32-bit mode of a 64-bit implementation and the low-order 32 bits of rA contains the most negative 32-bit number (0x8000_0000), then the low-order 32 bits of the result contain the most negative 32-bit&#10;number and, if OE = '1', OV is set."
  2301.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                  (if Rc = '1')&#10; * XER:&#10;   Affected: SO OV                           (if OE = '1')"
  2302.            Pseudocode="        rD = ! (rA) + 1"/>
  2303.         <Mnemonic
  2304.            Form="neg rD,rA"
  2305.            Notes="Negate."/>
  2306.         <Mnemonic
  2307.            Form="neg. rD,rA"
  2308.            Notes="Negate and record."/>
  2309.         <Mnemonic
  2310.            Form="nego rD,rA"
  2311.            Notes="Negate and overflow."/>
  2312.         <Mnemonic
  2313.            Form="nego. rD,rA"
  2314.            Notes="Negate overflow and record."/>
  2315.     </Instruction>
  2316.     <Instruction>
  2317.         <Details
  2318.            Name="NOR"
  2319.            Description="The contents of rS are ORed with the contents of rB and the complemented result is placed into rA.&#10;&#10;A nor with rS = rB can be used to obtain the one's complement."
  2320.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO             (if Rc = '1')"
  2321.            Pseudocode="        rA = ! ((rS) | (rB))"/>
  2322.         <Mnemonic
  2323.            Form="nor rA,rS,rB"
  2324.            Notes="NOR."/>
  2325.         <Mnemonic
  2326.            Form="nor. rA,rS,rB"
  2327.            Notes="NOR and record."/>
  2328.         <Mnemonic
  2329.            Form="not rA,rS"
  2330.            Notes="Equivalent to: nor rA,rS,rS."/>
  2331.     </Instruction>
  2332.     <Instruction>
  2333.         <Details
  2334.            Name="OR"
  2335.            Description="The contents of rS are ORed with the contents of rB and the result is placed into rA."
  2336.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO              (if Rc = '1')"
  2337.            Pseudocode="       rA = (rS) | (rB)"/>
  2338.         <Mnemonic
  2339.            Form="or rA,rS,rB"
  2340.            Notes="OR."/>
  2341.         <Mnemonic
  2342.            Form="or. rA,rS,rB"
  2343.            Notes="OR and record."/>
  2344.         <Mnemonic
  2345.            Form="mr rA,rS"
  2346.            Notes="Equivalent to: or rA,rS,rS."/>
  2347.     </Instruction>
  2348.     <Instruction>
  2349.         <Details
  2350.            Name="OR with Complement"
  2351.            Description="The contents of rS are ORed with the complement of the contents of rB and the result is placed into rA."
  2352.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO             (if Rc = '1')"
  2353.            Pseudocode="        rA = (rS) | ! (rB)"/>
  2354.         <Mnemonic
  2355.            Form="orc rA,rS,rB"
  2356.            Notes="OR with complement."/>
  2357.         <Mnemonic
  2358.            Form="orc. rA,rS,rB"
  2359.            Notes="OR with complement and record."/>
  2360.     </Instruction>
  2361.     <Instruction>
  2362.         <Details
  2363.            Name="OR Immediate"
  2364.            Description="The contents of rS are ORed with 0x0000_0000_0000 || UIMM and the result is placed into rA.&#10;&#10;The preferred no-op (an instruction that does nothing) is ori 0,0,0."
  2365.            OtherRegs=""
  2366.            Pseudocode="       rA = (rS) | ((48)0 || UIMM)"/>
  2367.         <Mnemonic
  2368.            Form="ori rA,rS,UIMM"
  2369.            Notes="OR with imm16."/>
  2370.         <Mnemonic
  2371.            Form="nop"
  2372.            Notes="Equivalent to: ori 0,0,0."/>
  2373.     </Instruction>
  2374.     <Instruction>
  2375.         <Details
  2376.            Name="OR Immediate Shifted"
  2377.            Description="The contents of rS are ORed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA."
  2378.            OtherRegs=""
  2379.            Pseudocode="        rA = (rS) | ((32)0 || UIMM || (16)0)"/>
  2380.         <Mnemonic
  2381.            Form="oris rA,rS,UIMM"
  2382.            Notes="OR with imm16 shifted left by 16 bits."/>
  2383.     </Instruction>
  2384.     <Instruction>
  2385.         <Details
  2386.            Name="Return from Interrupt Doubleword"
  2387.            Description="Bit [0] of SRR1 is placed into MSR[0]. If MSR[3] = '1' then bits [3,51] of SRR1 are placed into the corresponding bits of the MSR. The result of ORing bits [58] and [49] of SRR1 is placed into MSR[58]. The result of ORing bits [59] and [49] of SRR1 is placed into MSR[59]. Bits [1-2, 4-32, 37-41, 48-50, 52-57, and 60-63] of SRR1 are placed into the corresponding bits of the MSR.&#10;&#10;If the new MSR value does not enable any pending exceptions, then the next instruction is fetched, under control of the new MSR value, from the address SRR0[0-61] || '00' (when MSR[SF] = '1') or 0x0000_0000 || SRR0[32-61] || '00' (when MSR[SF] = '0'). If the new MSR value enables one or more pending exceptions, the exception associated with the highest priority pending exception is generated; in this case the value placed into SRR0 by the exception processing mechanism is the address of the instruction that would have been executed next had the exception not occurred.&#10;&#10;Note: An implementation may define additional MSR bits, and in this case, may also cause them to be saved to SRR1 from MSR on an exception and restored to MSR from SRR1 on an rfid.&#10;&#10;This is a supervisor-level, context synchronizing instruction."
  2388.            OtherRegs="MSR"
  2389.            Pseudocode="       MSR[0] = SRR1[0] | SRR1[1]&#10;       MSR[58] = SRR1[58] | SRR1[49]&#10;       MSR59] = SRR1[59] | SRR1[49]&#10;       MSR[1-2,4-32,37-41,49-50,52-57,60-63] = SRR1[1-2,4-32,37-41,49-50,52-57,60-63]&#10;       NIA = iea SRR0[0-61] || '00'"/>
  2390.         <Mnemonic
  2391.            Form="rfid"
  2392.            Notes="Return from interrupt doubleword."/>
  2393.     </Instruction>
  2394.     <Instruction>
  2395.         <Details
  2396.            Name="Rotate Left Doubleword then Clear Left"
  2397.            Description="The contents of rS are rotated left the number of bits specified by operand in the low-order six bits of rB. A mask is generated having '1' bits from bit [MB] through bit [63] and '0' bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA.&#10;&#10;Note that the rldcl instruction can be used to extract and rotate bit fields using the methods shown below:&#10; * To extract an n-bit field, that starts at variable bit position b in register rS, right-justified into rA (clearing the remaining 64 - n bits of rA), set the low-order six bits of rB to b + n and MB = 64 - n.&#10; * To rotate the contents of a register left by variable n bits, set the low-order six bits of rB to n and MB = '0', and to shift the contents of a register right, set the low-order six bits of rB to(64 - n), and MB = '0'."
  2398.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                         (if Rc = '1')"
  2399.            Pseudocode="         n = rB[58-63]&#10;         r = ROTL[64](rS, n)&#10;         b = mb[5] || mb[0-4]&#10;         m = MASK(b, 63)&#10;         rA = r &amp; m"/>
  2400.         <Mnemonic
  2401.            Form="rldcl rA,rS,rB,MB"
  2402.            Notes="Rotate left doubleword then clear left."/>
  2403.         <Mnemonic
  2404.            Form="rldcl. rA,rS,rB,MB"
  2405.            Notes="Rotate left doubleword then clear left and record."/>
  2406.         <Mnemonic
  2407.            Form="rotld rA,rS,rB"
  2408.            Notes="Equivalent to: rldcl rA,rS,rB,0."/>
  2409.     </Instruction>
  2410.     <Instruction>
  2411.         <Details
  2412.            Name="Rotate Left Doubleword then Clear Right"
  2413.            Description="The contents of rS are rotated left the number of bits specified by the low-order six bits of rB. A mask is generated having '1' bits from bit [0] through bit [ME] and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA.&#10;&#10;Note that rldcr can be used to extract and rotate bit fields using the methods shown below:&#10; * To extract an n-bit field, that starts at variable bit position b in register rS, left-justified into rA (clearing the remaining 64 - n bits of rA), set the low-order six bits of rB to b and ME = n - 1.&#10; * To rotate the contents of a register left by variable n bits, set the low-order six bits of rB to n and ME = 63, and to shift the contents of a register right, set the low-order six bits of rB to(64 - n), and ME = 63."
  2414.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                         (if Rc = '1')"
  2415.            Pseudocode="         n = rB[58-63]&#10;         r = ROTL[64](rS, n)&#10;         e = me[5] || me[0-4]&#10;         m = MASK(0, e)&#10;         rA = r &amp; m"/>
  2416.         <Mnemonic
  2417.            Form="rldcr rA,rS,rB,ME"
  2418.            Notes="Rotate left doubleword then clear right."/>
  2419.         <Mnemonic
  2420.            Form="rldcr. rA,rS,rB,ME"
  2421.            Notes="Rotate left doubleword then clear right and record."/>
  2422.     </Instruction>
  2423.     <Instruction>
  2424.         <Details
  2425.            Name="Rotate Left Doubleword Immediate then Clear"
  2426.            Description="The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having '1' bits from bit [MB] through bit [63 - SH] and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA.&#10;&#10;The rldic can be used to clear and shift bit fields using the methods shown below:&#10; * To clear the high-order b bits of the contents of a register and then shift the result left by n bits, set SH = n and MB = b - n.&#10; * To clear the high-order n bits of a register, set SH = '0' and MB = n."
  2427.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                         (if Rc = '1')"
  2428.            Pseudocode="         n = sh[5] || sh[0-4]&#10;         r = ROTL[64](rS, n)&#10;         b = mb[5] || mb[0-4]&#10;         m = MASK(b, ! n)&#10;         rA = r &amp; m"/>
  2429.         <Mnemonic
  2430.            Form="rldic rA,rS,SH,MB"
  2431.            Notes="Rotate left doubleword Immediate then clear."/>
  2432.         <Mnemonic
  2433.            Form="rldic. rA,rS,SH,MB"
  2434.            Notes="Rotate left doubleword Immediate then clear and record."/>
  2435.         <Mnemonic
  2436.            Form="clrlsldi rA,rS,b,n"
  2437.            Notes="Equivalent to: rldic rA,rS,n,b - n."/>
  2438.     </Instruction>
  2439.     <Instruction>
  2440.         <Details
  2441.            Name="Rotate Left Doubleword Immediate then Clear Left"
  2442.            Description="The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having '1' bits from bit MB through bit 63 and 0 bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA.&#10;&#10;The rldicl can be used to extract, rotate, shift, and clear bit fields using the methods shown below:&#10; * To extract an n-bit field, that starts at bit position b in rS, right-justified into rA (clearing the remaining 64-n bits of rA), set SH = b + n and MB = 64 - n.&#10; * To rotate the contents of a register left by n bits, set SH = n and MB = '0'; to rotate the contents of a register right by n bits, set SH = (64 - n), and MB = '0'.&#10; * To shift the contents of a register right by n bits, set SH = 64 - n and MB = n.&#10; * To clear the high-order n bits of a register, set SH = '0' and MB = n."
  2443.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                         (if Rc = '1')"
  2444.            Pseudocode="          n = sh[5] || sh[0-4]&#10;          r = ROTL[64](rS, n)&#10;          b = mb[5] || mb[0-4]&#10;          m = MASK(b, 63)&#10;          rA = r &amp; m"/>
  2445.         <Mnemonic
  2446.            Form="rldicl rA,rS,SH,MB"
  2447.            Notes="Rotate left doubleword immediate then clear left."/>
  2448.         <Mnemonic
  2449.            Form="rldicl. rA,rS,SH,MB"
  2450.            Notes="Rotate left doubleword immediate then clear left and record."/>
  2451.         <Mnemonic
  2452.            Form="extrdi rA,rS,n,b (n &gt; 0)"
  2453.            Notes="Equivalent to: rldicl rA,rS,b + n,64 - n."/>
  2454.         <Mnemonic
  2455.            Form="rotldi rA,rS,n"
  2456.            Notes="Equivalent to: rldicl rA,rS,n,0."/>
  2457.         <Mnemonic
  2458.            Form="rotrdi rA,rS,n"
  2459.            Notes="Equivalent to: rldicl rA,rS,64 - n,0."/>
  2460.         <Mnemonic
  2461.            Form="srdi rA,rS,n (n &lt; 64)"
  2462.            Notes="Equivalent to: rldicl rA,rS,64 - n,n."/>
  2463.         <Mnemonic
  2464.            Form="clrldi rA,rS,n (n &lt; 64)"
  2465.            Notes="Equivalent to: rldicl rA,rS,0,n."/>
  2466.     </Instruction>
  2467.     <Instruction>
  2468.         <Details
  2469.            Name="Rotate Left Doubleword Immediate then Clear Right"
  2470.            Description="The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having '1' bits from bit [0] through bit [ME] and '0' bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA.&#10;&#10;The rldicr can be used to extract, rotate, shift, and clear bit fields using the methods shown below:&#10; * To extract an n-bit field, that starts at bit position b in rS, left-justified into rA (clearing the remaining 64-n bits of rA), set SH = b and ME = n - 1.&#10; * To rotate the contents of a register left (right) by n bits, set SH = n (64 - n) and ME = 63.&#10; * To shift the contents of a register left by n bits, by setting SH = n and ME = 63 - n.&#10; * To clear the low-order n bits of a register, by setting SH = '0' and ME = 63 - n."
  2471.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                        (if Rc = '1')"
  2472.            Pseudocode="          n = sh[5] || sh[0-4]&#10;          r = ROTL[64](rS, n)&#10;          e = me[5] || me[0-4]&#10;          m = MASK(0, e)&#10;          rA = r &amp; m"/>
  2473.         <Mnemonic
  2474.            Form="rldicr rA,rS,SH,ME"
  2475.            Notes="Rotate left doubleword immediate then clear right."/>
  2476.         <Mnemonic
  2477.            Form="rldicr. rA,rS,SH,ME"
  2478.            Notes="Rotate left doubleword immediate then clear right and record."/>
  2479.         <Mnemonic
  2480.            Form="extldi rA,rS,n,b"
  2481.            Notes="Equivalent to: rldicr rA,rS,b,n - 1."/>
  2482.         <Mnemonic
  2483.            Form="sldi rA,rS,n"
  2484.            Notes="Equivalent to: rldicr rA,rS,n,63 - n."/>
  2485.         <Mnemonic
  2486.            Form="clrrdi rA,rS,n"
  2487.            Notes="Equivalent to: rldicr rA,rS,0,63 - n."/>
  2488.     </Instruction>
  2489.     <Instruction>
  2490.         <Details
  2491.            Name="Rotate Left Doubleword Immediate then Mask Insert"
  2492.            Description="The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having '1' bits from bit MB through bit 63 - SH and 0 bits elsewhere. The rotated data is inserted into rA under control of the generated mask.&#10;&#10;Note: rldimi can be used to insert an n-bit field, that is right-justified in rS, into rA starting at bit position b, by setting SH = 64 - (b + n) and MB = b."
  2493.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                         (if Rc = '1')"
  2494.            Pseudocode="          n = sh[5] || sh[0-4]&#10;          r = ROTL[64](rS, n)&#10;          b = mb[5] || mb[0-4]&#10;          m = MASK(b, ! n)&#10;          rA = (r &amp; m) | (rA &amp; ! m)"/>
  2495.         <Mnemonic
  2496.            Form="rldimi rA,rS,SH,MB"
  2497.            Notes="Rotate left doubleword immediate then mask insert."/>
  2498.         <Mnemonic
  2499.            Form="rldimi. rA,rS,SH,MB"
  2500.            Notes="Rotate left doubleword immediate then mask insert and record."/>
  2501.         <Mnemonic
  2502.            Form="insrdi rA,rS,n,b"
  2503.            Notes="Equivalent to: rldimi rA,rS,64 - (b + n),b."/>
  2504.     </Instruction>
  2505.     <Instruction>
  2506.         <Details
  2507.            Name="Rotate Left Word Immediate then Mask Insert"
  2508.            Description="The contents of rS are rotated left the number of bits specified by operand SH. A mask is generated having '1' bits from bit [MB + 32] through bit [ME + 32] and '0' bits elsewhere. The rotated data is inserted into rA under control of the generated mask.&#10;&#10;rlwimi can be used to insert a bit field into the contents of rA using the methods shown below:&#10; * To insert an n-bit field, that is left-justified in the low-order 32 bits of rS, into the high-order 32 bits of rA starting at bit position b, set SH = 32 - b, MB = b, and ME = (b + n) - 1.&#10; * To insert an n-bit field, that is right-justified in the low-order 32 bits of rS, into the high-order 32 bits of rA starting at bit position b, set SH = 32 - (b + n), MB = b, and ME = (b + n) - 1."
  2509.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                 (if Rc = '1')"
  2510.            Pseudocode="          n = SH&#10;          r = ROTL[32](rS[32-63], n)&#10;          m = MASK(MB + 32, ME + 32)&#10;          rA = (r &amp; m) | (rA &amp; ! m)"/>
  2511.         <Mnemonic
  2512.            Form="rlwimi rA,rS,SH,MB,ME"
  2513.            Notes="Rotate left word immediate then mask insert."/>
  2514.         <Mnemonic
  2515.            Form="rlwimi. rA,rS,SH,MB,ME"
  2516.            Notes="Rotate left word Immediate then mask insert and record."/>
  2517.         <Mnemonic
  2518.            Form="inslwi rA,rS,n,b"
  2519.            Notes="Equivalent to: rlwimi rA,rS,32 - b,b,b + n - 1."/>
  2520.         <Mnemonic
  2521.            Form="insrwi rA,rS,n,b (n &gt; 0)"
  2522.            Notes="Equivalent to: rlwimi rA,rS,32 - (b + n),b,(b + n) - 1."/>
  2523.     </Instruction>
  2524.     <Instruction>
  2525.         <Details
  2526.            Name="Rotate Left Word Immediate then AND with Mask"
  2527.            Description="The contents of rS[32-63] are rotated left the number of bits specified by operand SH. A mask is generated having '1' bits from bit [MB + 32] through bit [ME + 32] and '0' bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA. The upper 32 bits of rA are cleared.&#10;&#10;rlwinm can be used to extract, rotate, shift, and clear bit fields using the methods shown below:&#10; * To extract an n-bit field, that starts at bit position b in the high-order 32 bits of rS, right-justified into rA (clearing the remaining 32 - n bits of rA), set SH = b + n, MB = 32 - n, and ME = 31.&#10; * To extract an n-bit field, that starts at bit position b in the high-order 32 bits of rS, left-justified into rA (clearing the remaining 32 - n bits of rA), set SH = b, MB = '0', and ME = n - 1.&#10; * To rotate the contents of a register left (or right) by n bits, set SH = n (32 - n), MB = '0', and ME = 31.&#10; * To shift the contents of a register right by n bits, by setting SH = 32 - n, MB = n, and ME = 31. It can be used to clear the high-order b bits of a register and then shift the result left by n bits by setting SH = n, MB = b - n and ME = 31 - n.&#10; * To clear the low-order n bits of a register, by setting SH = '0', MB = '0', and ME = 31 - n.&#10;&#10;For all uses mentioned, the high-order 32 bits of rA are cleared."
  2528.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                 (if Rc = '1')"
  2529.            Pseudocode="       n = SH&#10;       r = ROTL[32](rS[32-63], n)&#10;       m = MASK(MB + 32, ME + 32)&#10;       rA = r &amp; m"/>
  2530.         <Mnemonic
  2531.            Form="rlwinm rA,rS,SH,MB,ME"
  2532.            Notes="Rotate left word immediate then AND with mask"/>
  2533.         <Mnemonic
  2534.            Form="rlwinm. rA,rS,SH,MB,ME"
  2535.            Notes="Rotate left word immediate then AND with mask and record."/>
  2536.         <Mnemonic
  2537.            Form="extlwi rA,rS,n,b (n &gt; 0)"
  2538.            Notes="Equivalent to: rlwinm rA,rS,b,0,n - 1."/>
  2539.         <Mnemonic
  2540.            Form="extrwi rA,rS,n,b (n &gt; 0)"
  2541.            Notes="Equivalent to: rlwinm rA,rS,b + n,32 - n,31."/>
  2542.         <Mnemonic
  2543.            Form="rotlwi rA,rS,n"
  2544.            Notes="Equivalent to: rlwinm rA,rS,n,0,31."/>
  2545.         <Mnemonic
  2546.            Form="rotrwi rA,rS,n"
  2547.            Notes="Equivalent to: rlwinm rA,rS,32 - n,0,31."/>
  2548.         <Mnemonic
  2549.            Form="slwi rA,rS,n (n &lt; 32)"
  2550.            Notes="Equivalent to: rlwinm rA,rS,n,0,31 - n."/>
  2551.         <Mnemonic
  2552.            Form="srwi rA,rS,n (n &lt; 32)"
  2553.            Notes="Equivalent to: rlwinm rA,rS,32 - n,n,31."/>
  2554.         <Mnemonic
  2555.            Form="clrlwi rA,rS,n (n &lt; 32)"
  2556.            Notes="Equivalent to: rlwinm rA,rS,0,n,31."/>
  2557.         <Mnemonic
  2558.            Form="clrrwi rA,rS,n (n &lt; 32)"
  2559.            Notes="Equivalent to: rlwinm rA,rS,0,0,31 - n."/>
  2560.         <Mnemonic
  2561.            Form="clrlslwi rA,rS,b,n (n &lt;= b &lt; 32)"
  2562.            Notes="Equivalent to: rlwinm rA,rS,n,b - n,31 - n."/>
  2563.     </Instruction>
  2564.     <Instruction>
  2565.         <Details
  2566.            Name="Rotate Left Word then AND with Mask"
  2567.            Description="The contents of rS are rotated left the number of bits specified by the low-order five bits of rB. A mask is generated having '1' bits from bit [MB + 32] through bit [ME + 32] and '0' bits elsewhere. The rotated data is ANDed with the generated mask and the result is placed into rA.&#10;&#10;rlwnm can be used to extract and rotate bit fields using the methods shown as follows:&#10; * To extract an n-bit field, that starts at variable bit position b in the high-order 32 bits of rS, right-justified into rA (clearing the remaining 32 - n bits of rA), by setting the low-order five bits of rB to b + n, MB = 32 - n, and ME = 31.&#10; * To extract an n-bit field, that starts at variable bit position b in the high-order 32 bits of rS, left-justified into rA (clearing the remaining 32 - n bits of rA), by setting the low-order five bits of rB to b, MB = '0', and ME = n - 1.&#10; * To rotate the contents of a register left (or right) by n bits, by setting the low-order five bits of rB to n (32-n), MB = '0', and ME = 31.&#10;&#10;For all uses mentioned, the high-order 32 bits of rA are cleared."
  2568.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                  (if Rc = '1')"
  2569.            Pseudocode="         n = rB[59-63]&#10;         r = ROTL[32](rS[32-63], n)&#10;         m = MASK(MB + 32, ME + 32)&#10;         rA = r &amp; m"/>
  2570.         <Mnemonic
  2571.            Form="rlwnm rA,rS,rB,MB,ME"
  2572.            Notes="Rotate left word then AND with mask."/>
  2573.         <Mnemonic
  2574.            Form="rlwnm. rA,rS,rB,MB,ME"
  2575.            Notes="Rotate left word then AND with mask and record."/>
  2576.         <Mnemonic
  2577.            Form="rotlw rA,rS,rB"
  2578.            Notes="Equivalent to: rlwnm rA,rS,rB,0,31."/>
  2579.     </Instruction>
  2580.     <Instruction>
  2581.         <Details
  2582.            Name="System Call"
  2583.            Description="In the PowerPC UISA, the sc instruction calls the operating system to perform a service. When control is returned to the program that executed the system call, the content of the registers depends on the register conventions used by the program providing the system service.&#10;&#10;This instruction is context synchronizing."
  2584.            OtherRegs="Dependent on the system service"
  2585.            Pseudocode=""/>
  2586.         <Mnemonic
  2587.            Form="sc"
  2588.            Notes="System call."/>
  2589.     </Instruction>
  2590.     <Instruction>
  2591.         <Details
  2592.            Name="SLB Invalidate All"
  2593.            Description="For all SLB entries except SLB entry 0, the [V] bit in the entry is set to 0, making the entry invalid, and the remaining fields of the entry are set to undefined values. SLB entry 0 is not altered.&#10;&#10;Note: If slbia is executed when instruction address translation is enabled (MSR[IR]= '1'), software can ensure that attempting to fetch the instruction following the slbia does not cause an Instruction Segment interrupt by placing the slbia and the subsequent instruction in the effective segment mapped by SLB entry 0. (This assumes that no other interrupts occur between executing the slbia and executing the subsequent instruction.)&#10;&#10;This instruction is supervisor-level.&#10;&#10;It is not necessary that the ASR point to a valid segment table when issuing slbia."
  2594.            OtherRegs=""
  2595.            Pseudocode="        for each SLB entry except SLB entry 0 SLBE[V] = 0&#10;        all other fields of SLBE = undefined"/>
  2596.         <Mnemonic
  2597.            Form="slbia"
  2598.            Notes="Invalidate all entries in the SLB."/>
  2599.     </Instruction>
  2600.     <Instruction>
  2601.         <Details
  2602.            Name="SLB Invalidate Entry"
  2603.            Description="Let the Effective Segment ID (ESID) be rB[0-35]. Let the class be rB[36]. The class value must be the same as the class value in the SLB entry that translates the ESID, or the class value that was in the SLB entry that most recently translated the ESID if the translation is no longer in the SLB. If the class value is not the same, the results of translating effective addresses for which EA[0-35] = ESID are undefined, and the next paragraph need not apply.&#10;&#10;If the SLB contains an entry that translates the specified ESID, the [V] bit in that entry is set to '0', making the entry invalid, and the remaining fields of the entry are set to undefined values.&#10;&#10;rB[37-63] must be zeroes.&#10;&#10;If this instruction is executed in 32-bit mode, rB[0-31] must be zeros (i.e., the ESID must be in the range&#10;[0-15]).&#10;&#10;This instruction is supervisor-level.&#10;&#10;Note: If the optional 'Bridge' facility is implemented, the Move To Segment Register instructions create SLB&#10;entries in which the class value is '0'."
  2604.            OtherRegs=""
  2605.            Pseudocode="        esid = (rB)0:35&#10;        class = (rB)36&#10;        if class = SLBE[C] for SLB entry that translates&#10;           or most recently translated esid&#10;        then for SLB entry (if any) that translates esid&#10;           SLBE[V] = 0&#10;           all other fields of SLBE = undefined&#10;        else translation of esid = undefined"/>
  2606.         <Mnemonic
  2607.            Form="slbie rB"
  2608.            Notes="Invalidate the specified entry in the SLB."/>
  2609.     </Instruction>
  2610.     <Instruction>
  2611.         <Details
  2612.            Name="SLB Move From Entry ESID"
  2613.            Description="If the SLB entry specified by bits [52-63] of register rB is valid (V= '1'), the contents of the ESID and V fields of the entry are placed into register rD.&#10;&#10;If the SLB entry specified by bits [52-63] of register rB is invalid (V= '0'), rD[36] is set to 0 and the contents of rD[0-35] and rD[37-63] are undefined. The high-order bits of rB[52-63] that correspond to SLB entries beyond the size of the SLB provided by the implementation must be zeros.&#10;&#10;This instruction is supervisor-level."
  2614.            OtherRegs=""
  2615.            Pseudocode="        rD[0-35] ESID&#10;        rD[36] V&#10;        rD[37-63] must be 0b000|| 0x00_0000&#10;        rB[0-51] must be 0x0_0000_0000_0000&#10;        rB[52-6]3 index, which selects the SLB entry"/>
  2616.         <Mnemonic
  2617.            Form="slbmfee rD,"
  2618.            Notes="Move the specified SLB entry's ESID and V fields to register."/>
  2619.     </Instruction>
  2620.     <Instruction>
  2621.         <Details
  2622.            Name="SLB Move From Entry VSID"
  2623.            Description="If the SLB entry specified by bits [52-63] of register rB is valid (V= '1'), the contents of the VSID, KS, KP, N, L, and C fields of the entry are placed into register rD.&#10;&#10;On implementations that support a virtual address size of only n bits, n&lt; 80, rD[0 to 79- n] are set to zeros. If the SLB entry specified by bits [52-63] of register rB is invalid (V= '0'), the contents of register rD are undefined. The high-order bits of rB[52-63] that correspond to SLB entries beyond the size of the SLB provided by the implementation must be zeros.&#10;&#10;This is a supervisor-level instruction."
  2624.            OtherRegs=""
  2625.            Pseudocode="       rD[0-51] VSID&#10;       rD[52] Ks&#10;       rD[53] KP&#10;       rD[54] N&#10;       rD[55] L&#10;       rD[56] C&#10;       rD[57-63] must be 0b000_0000&#10;       rB[0-51] must be 0x0_0000_0000_0000&#10;       rB[52-63] index, which selects the SLB entry"/>
  2626.         <Mnemonic
  2627.            Form="slbmfev rD,"
  2628.            Notes="Move the specified SLB entry's VSID, KS, KP, N, L, and C fields to register."/>
  2629.     </Instruction>
  2630.     <Instruction>
  2631.         <Details
  2632.            Name="SLB Move To Entry"
  2633.            Description="The SLB entry specified by bits [52-63] of register rB is loaded from register rS and from the remainder of register rB.&#10;&#10;On implementations that support a virtual address size of only n bits, n&lt; 80, rS[0 to 79- n] must be zeros. The high-order bits of rB[52-63] that correspond to SLB entries beyond the size of the SLB provided by the implementation must be zeros. If this instruction is executed in 32-bit mode, rB[0-31] must be zeros (i.e., the ESID must be in the range 0-15). This instruction cannot be used to invalidate an SLB. &#10;&#10;This is a supervisor-level instruction."
  2634.            OtherRegs=""
  2635.            Pseudocode="         rS[0-51] VSID&#10;         rS[52]Ks&#10;         rS[53] Kp&#10;         rS[54] N&#10;         rS[55]L&#10;         rS[56] C&#10;         rS[57-63] must be 0b000_0000&#10;         rB[0-35] ESID&#10;         rB[36] V&#10;         rB[37-5]1 must be 0b000 || 0x000&#10;         rB[52-63] index, which selects the SLB entry"/>
  2636.         <Mnemonic
  2637.            Form="slbmte rS,"
  2638.            Notes="Move to the specified SLB entry."/>
  2639.     </Instruction>
  2640.     <Instruction>
  2641.         <Details
  2642.            Name="Shift Left Doubleword"
  2643.            Description="The contents of rS are shifted left the number of bits specified by the low-order seven bits of rB. Bits shifted out of position 0 are lost. Zeros are supplied to the vacated positions on the right. The result is placed into rA. Shift amounts from 64 to 127 give a zero result."
  2644.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')"
  2645.            Pseudocode="       n = rB[58-63]&#10;       r = ROTL[64](rS, n)&#10;       if rB[57] = 0 then&#10;         m = MASK(0, 63 - n)&#10;       else &#10;         m = (64)0&#10;       rA = r &amp; m"/>
  2646.         <Mnemonic
  2647.            Form="sld rA,rS,rB"
  2648.            Notes="Shift left doubleword."/>
  2649.         <Mnemonic
  2650.            Form="sld. rA,rS,rB"
  2651.            Notes="Shift left doubleword and record."/>
  2652.     </Instruction>
  2653.     <Instruction>
  2654.         <Details
  2655.            Name="Shift Left Word"
  2656.            Description="The contents of the low-order 32 bits of rS are shifted left the number of bits specified by the low-order six bits of rB. Bits shifted out of position 32 are lost. Zeros are supplied to the vacated positions on the right. The 32-bit result is placed into the low-order 32 bits of rA. The high-order 32 bits of rA are cleared. Shift amounts from 32 to 63 give a zero result."
  2657.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')"
  2658.            Pseudocode="        n = rB[59-63]&#10;        r = ROTL[32](rS[32-63], n)&#10;        if rB[58] = 0 then&#10;          m = MASK(32, 63 - n)&#10;        else &#10;          m = (64)0&#10;        rA = r &amp; m"/>
  2659.         <Mnemonic
  2660.            Form="slw rA,rS,rB"
  2661.            Notes="Shift left word."/>
  2662.         <Mnemonic
  2663.            Form="slw. rA,rS,rB"
  2664.            Notes="Shift left word and record."/>
  2665.     </Instruction>
  2666.     <Instruction>
  2667.         <Details
  2668.            Name="Shift Right Algebraic Doubleword"
  2669.            Description="The contents of rS are shifted right the number of bits specified by the low-order seven bits of rB. Bits shifted out of position 63 are lost. Bit [0] of rS is replicated to fill the vacated positions on the left. The result is placed into rA. XER[CA] is set if rS is negative and any '1' bits are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to be set equal to rS, and XER[CA] to be cleared. Shift amounts from 64 to 127 give a result of 64 sign bits in rA, and cause XER[CA] to receive the sign bit of rS.&#10;&#10;Note: The srad instruction, followed by addze, can by used to divide quickly by 2n. The setting of the CA bit, by srad, is independent of mode."
  2670.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                  (if Rc = '1')&#10; * XER:&#10;   Affected: CA"
  2671.            Pseudocode="        n = rB[58-63]&#10;        r = ROTL[64](rS, 64 - n)&#10;        if rB[57] = 0 then&#10;          m = MASK(n, 63)&#10;        else &#10;          m = (64)0&#10;        S = rS[0]&#10;        rA = (r &amp; m) | (((64)S) &amp; ! m)&#10;        XER[CA] = S &amp; ((r &amp; ! m) | 0)"/>
  2672.         <Mnemonic
  2673.            Form="srad rA,rS,rB"
  2674.            Notes="Shift right doubleword. The result is sign extended."/>
  2675.         <Mnemonic
  2676.            Form="srad. rA,rS,rB"
  2677.            Notes="Shift right doubleword and record. The result is sign extended."/>
  2678.     </Instruction>
  2679.     <Instruction>
  2680.         <Details
  2681.            Name="Shift Right Algebraic Doubleword Immediate"
  2682.            Description="The contents of rS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit 0 of rS is replicated to fill the vacated positions on the left. The result is placed into rA. XER[CA] is set if rS is negative and any '1' bits are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to be set equal to rS, and XER[CA] to be cleared.&#10;&#10;Note: The sradi instruction, followed by addze, can by used to divide quickly by 2n. The setting of the XER[CA] bit, by sradi, is independent of mode."
  2683.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                    (if Rc = '1')&#10; * XER:&#10;   Affected: CA"
  2684.            Pseudocode="         n = sh[5] || sh[0-4]&#10;         r = ROTL[64](rS, 64 - n)&#10;         m = MASK(n, 63)&#10;         S = rS[0]&#10;         rA = (r &amp; m) | (((64)S) &amp; ! m)&#10;         XER[CA] = S &amp; ((r &amp; ! m) != 0)"/>
  2685.         <Mnemonic
  2686.            Form="sradi rA,rS,SH"
  2687.            Notes="Shift right doubleword immediate. The result is sign extended."/>
  2688.         <Mnemonic
  2689.            Form="sradi. rA,rS,SH"
  2690.            Notes="Shift right doubleword immediate and record. The result is sign extended."/>
  2691.     </Instruction>
  2692.     <Instruction>
  2693.         <Details
  2694.            Name="Shift Right Algebraic Word"
  2695.            Description="The contents of the low-order 32 bits of rS are shifted right the number of bits specified by the low-order six bits of rB. Bits shifted out of position 63 are lost. Bit [32] of rS is replicated to fill the vacated positions on the left. The 32-bit result is placed into the low-order 32 bits of rA. Bit [32] of rS is replicated to fill the high-order 32 bits of rA. XER[CA] is set if the low-order 32 bits of rS contain a negative number and any '1' bits are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to receive the sign-extended value of the low-order 32 bits of rS, and XER[CA] to be cleared. Shift amounts from 32 to 63 give a result of 64 sign bits, and cause XER[CA] to receive the sign bit of the low-order 32 bits of rS.&#10;&#10;Note: The sraw instruction, followed by addze, can by used to divide quickly by 2n. The setting of the XER[CA] bit, by sraw, is independent of mode."
  2696.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                 (if Rc = '1')&#10; * XER:&#10;   Affected: CA"
  2697.            Pseudocode="        n = rB[59-63]&#10;        r = ROTL[32](rS[32-63], 64 - n)&#10;        if rB[58] = 0 then&#10;          m = MASK(n + 32, 63)&#10;        else &#10;          m = (64)0&#10;        S = rS[32]&#10;        rA = r &amp; m | (64)S &amp; ! m&#10;        XER[CA] = S &amp; (r &amp; ! m[32-63] != 0"/>
  2698.         <Mnemonic
  2699.            Form="sraw rA,rS,rB"
  2700.            Notes="Shift right doubleword. The result is sign extended."/>
  2701.         <Mnemonic
  2702.            Form="sraw. rA,rS,rB"
  2703.            Notes="Shift right doubleword and record. The result is sign extended."/>
  2704.     </Instruction>
  2705.     <Instruction>
  2706.         <Details
  2707.            Name="Shift Right Algebraic Word Immediate"
  2708.            Description="The contents of the low-order 32 bits of rS are shifted right SH bits. Bits shifted out of position 63 are lost. Bit [32] of rS is replicated to fill the vacated positions on the left. The 32-bit result is placed into the low-order 32 bits of rA. Bit [32] of rS is replicated to fill the high-order 32 bits of rA. XER[CA] is set if the low-order 32 bits of rS contain a negative number and any '1' bits are shifted out of position 63; otherwise XER[CA] is cleared. A shift amount of zero causes rA to receive the sign-extended value of the low-order 32 bits of rS, and XER[CA] to be cleared.&#10;&#10;Note: The srawi instruction, followed by addze, can be used to divide quickly by 2n. The setting of the CA bit, by srawi, is independent of mode."
  2709.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                  (if Rc = '1')&#10; * XER:&#10;   Affected: CA"
  2710.            Pseudocode="         n = SH&#10;         r = ROTL[32](rS[32-63], 64 - n)&#10;         m= MASK(n + 32, 63)&#10;         S = rS[32]&#10;         rA = r &amp; m | (64)S &amp; ! m&#10;         XER[CA] = S &amp; ((r &amp; ! m)[32-63] != 0)"/>
  2711.         <Mnemonic
  2712.            Form="srawi rA,rS,SH"
  2713.            Notes="Shift right word immediate. The result is sign extended."/>
  2714.         <Mnemonic
  2715.            Form="srawi. rA,rS,SH"
  2716.            Notes="Shift right word immediate and record. The result is sign extended."/>
  2717.     </Instruction>
  2718.     <Instruction>
  2719.         <Details
  2720.            Name="Shift Right Doubleword"
  2721.            Description="The contents of rS are shifted right the number of bits specified by the low-order seven bits of rB. Bits shifted out of position 63 are lost. Zeros are supplied to the vacated positions on the left. The result is placed into rA.  Shift amounts from 64 to 127 give a zero result."
  2722.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')"
  2723.            Pseudocode="       n = rB[58-63]&#10;       r = ROTL[64](rS, 64 - n)&#10;       if rB[57] = 0 then&#10;         m = MASK(n, 63)&#10;       else &#10;         m = (64)0&#10;       rA = r &amp; m"/>
  2724.         <Mnemonic
  2725.            Form="srd rA,rS,rB"
  2726.            Notes="Shift right doubleword."/>
  2727.         <Mnemonic
  2728.            Form="srd. rA,rS,rB"
  2729.            Notes="Shift right doubleword and record."/>
  2730.     </Instruction>
  2731.     <Instruction>
  2732.         <Details
  2733.            Name="Shift Right Word"
  2734.            Description="The contents of the low-order 32 bits of rS are shifted right the number of bits specified by the low-order six bits of rB. Bits shifted out of position 63 are lost. Zeros are supplied to the vacated positions on the left. The 32-bit result is placed into the low-order 32 bits of rA. The high-order 32 bits of rA are cleared. Shift amounts from 32 to 63 give a zero result."
  2735.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO               (if Rc = '1')"
  2736.            Pseudocode="        n = rB[58-63]&#10;        r = ROTL[32](rS[32-63], 64 - n)&#10;        if rB[58] = 0 then&#10;          m = MASK(n + 32, 63)&#10;        else &#10;          m = (64)0&#10;        rA = r &amp; m"/>
  2737.         <Mnemonic
  2738.            Form="srw rA,rS,rB"
  2739.            Notes="Shift right word."/>
  2740.         <Mnemonic
  2741.            Form="srw. rA,rS,rB"
  2742.            Notes="Shift right word and record."/>
  2743.     </Instruction>
  2744.     <Instruction>
  2745.         <Details
  2746.            Name="Store Byte"
  2747.            Description="The effective address is the sum (rA|0) + d. The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA."
  2748.            OtherRegs=""
  2749.            Pseudocode="       if rA = 0 then &#10;         b = 0&#10;       else&#10;         b = (rA)&#10;       EA = b + EXTS(d)&#10;       MEM(EA,1) = rS[56-63]"/>
  2750.         <Mnemonic
  2751.            Form="stb rS,d(rA)"
  2752.            Notes="Store byte. The addressing mode is register indirect with immediate index."/>
  2753.     </Instruction>
  2754.     <Instruction>
  2755.         <Details
  2756.            Name="Store Byte with Update"
  2757.            Description="The effective address is the sum (rA) + d. The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2758.            OtherRegs=""
  2759.            Pseudocode="        EA = (rA) + EXTS(d)&#10;        MEM(EA, 1) = rS[56-63]&#10;        rA = EA"/>
  2760.         <Mnemonic
  2761.            Form="stbu rS,d(rA)"
  2762.            Notes="Store byte with update. The addressing mode is register indirect with immediate index."/>
  2763.     </Instruction>
  2764.     <Instruction>
  2765.         <Details
  2766.            Name="Store Byte with Update Indexed"
  2767.            Description="EA is the sum (rA) + (rB). The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2768.            OtherRegs=""
  2769.            Pseudocode="        EA = (rA) + (rB)&#10;        MEM(EA, 1) = rS[56-63]&#10;        rA = EA"/>
  2770.         <Mnemonic
  2771.            Form="stbux rS,rA,rB"
  2772.            Notes="Store byte with update. The addressing mode is register indirect with index."/>
  2773.     </Instruction>
  2774.     <Instruction>
  2775.         <Details
  2776.            Name="Store Byte Indexed"
  2777.            Description="EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into the byte in memory addressed by EA."
  2778.            OtherRegs=""
  2779.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        MEM(EA,1) = rS[56-63]"/>
  2780.         <Mnemonic
  2781.            Form="stbx rS,rA,rB"
  2782.            Notes="Store byte. The addressing mode is register indirect with index."/>
  2783.     </Instruction>
  2784.     <Instruction>
  2785.         <Details
  2786.            Name="Store Doubleword"
  2787.            Description="EA is the sum (rA|0) + (ds || '00'). The contents of rS are stored into the doubleword in memory addressed by EA."
  2788.            OtherRegs=""
  2789.            Pseudocode="       if rA = 0 then &#10;         b = 0&#10;       else&#10;         b = (rA)&#10;       EA = b + EXTS(ds || '00')&#10;       (MEM(EA, 8)) = (rS)"/>
  2790.         <Mnemonic
  2791.            Form="std rS,ds(rA)"
  2792.            Notes="Store doubleword. The addressing mode is register indirect with immediate index."/>
  2793.     </Instruction>
  2794.     <Instruction>
  2795.         <Details
  2796.            Name="Store Doubleword Conditional Indexed"
  2797.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;If a reservation exists, and the memory address specified by the stdcx. instruction is the same as that specified by the load and reserve instruction that established the reservation, the contents of rS are stored into the doubleword in memory addressed by EA and the reservation is cleared.&#10;&#10;If a reservation exists, but the memory address specified by the stdcx. instruction is not the same as that specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it is undefined whether the contents of rS are stored into the doubleword in memory addressed by EA.&#10;&#10;If no reservation exists, the instruction completes without altering memory.&#10;&#10;CR0 field is set to reflect whether the store operation was performed as follows.&#10;&#10;      CR0[LT GT EQ S0] = 0b00 || store_performed || XER[SO]&#10;&#10;EA must be a multiple of eight. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions.&#10;&#10;Note: When used correctly, the load and reserve and store conditional instructions can provide an atomic update function for a single aligned word (load word and reserve and store word conditional) or doubleword (load doubleword and reserve and store doubleword conditional) of memory.&#10;&#10;In general, correct use requires that load word and reserve be paired with store word conditional, and load doubleword and reserve with store doubleword conditional, with the same memory address specified by both instructions of the pair. The only exception is that an unpaired store word conditional or store doubleword conditional instruction to any (scratch) EA can be used to clear any reservation held by the processor.&#10;&#10;A reservation is cleared if any of the following events occurs:&#10; * The processor holding the reservation executes another load and reserve instruction; this clears the first reservation and establishes a new one.&#10; * The processor holding the reservation executes a store conditional instruction to any address.&#10; * Another processor executes any store instruction to the address associated with the reservation.&#10; * Any mechanism, other than the processor holding the reservation, stores to the address associated with&#10;   the reservation."
  2798.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO"
  2799.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else &#10;           b = (rA)&#10;         EA = b + (rB)&#10;         if RESERVE then&#10;           if RESERVE_ADDR = physical_addr(EA)&#10;             MEM(EA, 8) = (rS)&#10;             CR0 = '00' || '1' || XER[SO]&#10;           else&#10;             u = undefined 1-bit value&#10;             if u then &#10;               MEM(EA, 8) = (rS)&#10;             CR0 = '00' || u || XER[SO]&#10;           RESERVE = 0&#10;         else&#10;           CR0 = '00' || '0' || XER[SO]"/>
  2800.         <Mnemonic
  2801.            Form="stdcx. rS,rA,rB"
  2802.            Notes="Store doubleword if reservation exists. The addressing mode is register indirect with index."/>
  2803.     </Instruction>
  2804.     <Instruction>
  2805.         <Details
  2806.            Name="Store Doubleword with Update"
  2807.            Description="EA is the sum (rA) + (ds || '00'). The contents of rS are stored into the doubleword in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2808.            OtherRegs=""
  2809.            Pseudocode="        EA = (rA) + EXTS(ds || '00')&#10;        (MEM(EA, 8)) = (rS)&#10;        rA = EA"/>
  2810.         <Mnemonic
  2811.            Form="stdu rS,ds(rA)"
  2812.            Notes="Store doubleword with update. The addressing mode is register indirect with immediate index."/>
  2813.     </Instruction>
  2814.     <Instruction>
  2815.         <Details
  2816.            Name="Store Doubleword with Update Indexed"
  2817.            Description="EA is the sum (rA) + (rB). The contents of rS are stored into the doubleword in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2818.            OtherRegs=""
  2819.            Pseudocode="        EA = (rA) + (rB)&#10;        MEM(EA, 8) = (rS)&#10;        rA = EA"/>
  2820.         <Mnemonic
  2821.            Form="stdux rS,rA,rB"
  2822.            Notes="Store doubleword with update. The addressing mode is register indirect with index."/>
  2823.     </Instruction>
  2824.     <Instruction>
  2825.         <Details
  2826.            Name="Store Doubleword Indexed"
  2827.            Description="EA is the sum (rA|0) + (rB). The contents of rS are stored into the doubleword in memory addressed by EA."
  2828.            OtherRegs=""
  2829.            Pseudocode="        if rA = 0 then b = 0&#10;        elseb = (rA)&#10;        EA = b + (rB)&#10;        (MEM(EA, 8)) = (rS)"/>
  2830.         <Mnemonic
  2831.            Form="stdx rS,rA,rB"
  2832.            Notes="Store doubleword. The addressing mode is register indirect with index."/>
  2833.     </Instruction>
  2834.     <Instruction>
  2835.         <Details
  2836.            Name="Store Floating-Point Double"
  2837.            Description="EA is the sum (rA|0) + d.&#10;&#10;The contents of register frS are stored into the doubleword in memory addressed by EA."
  2838.            OtherRegs=""
  2839.            Pseudocode="       if rA = 0 then &#10;         b = 0&#10;       else&#10;         b = (rA)&#10;       EA = b + EXTS(d)&#10;       MEM(EA,8) = (frS)"/>
  2840.         <Mnemonic
  2841.            Form="stfd frS,d(rA)"
  2842.            Notes="Store double precision floating point. The addressing mode is register indirect with immediate index."/>
  2843.     </Instruction>
  2844.     <Instruction>
  2845.         <Details
  2846.            Name="Store Floating-Point Double with Update"
  2847.            Description="EA is the sum (rA) + d.&#10;&#10;The contents of register frS are stored into the doubleword in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2848.            OtherRegs=""
  2849.            Pseudocode="        EA = (rA) + EXTS(d)&#10;        MEM(EA, 8) = (frS)&#10;        rA = EA"/>
  2850.         <Mnemonic
  2851.            Form="stfdu frS,d(rA)"
  2852.            Notes="Store double precision floating point with update. The addressing mode is register indirect with immediate index."/>
  2853.     </Instruction>
  2854.     <Instruction>
  2855.         <Details
  2856.            Name="Store Floating-Point Double with Update Indexed"
  2857.            Description="EA is the sum (rA) + (rB).&#10;&#10;The contents of register frS are stored into the doubleword in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2858.            OtherRegs=""
  2859.            Pseudocode="         EA = (rA) + (rB)&#10;         MEM(EA, 8) = (frS)&#10;         rA = EA"/>
  2860.         <Mnemonic
  2861.            Form="stfdux frS,rA,rB"
  2862.            Notes="Store double precision floating point with update. The addressing mode is register indirect with index."/>
  2863.     </Instruction>
  2864.     <Instruction>
  2865.         <Details
  2866.            Name="Store Floating-Point Double Indexed"
  2867.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The contents of register frS are stored into the doubleword in memory addressed by EA."
  2868.            OtherRegs=""
  2869.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        MEM(EA,8) = (frS)"/>
  2870.         <Mnemonic
  2871.            Form="stfdx frS,rA,rB"
  2872.            Notes="Store double precision floating point. The addressing mode is register indirect with index."/>
  2873.     </Instruction>
  2874.     <Instruction>
  2875.         <Details
  2876.            Name="Store Floating-Point as Integer Word Indexed"
  2877.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The contents of the low-order 32 bits of register frS are stored, without conversion, into the word in memory addressed by EA.&#10;&#10;If the contents of register frS were produced, either directly or indirectly, by an lfs instruction, a single-precision arithmetic instruction, or frsp, then the value stored is undefined. The contents of frS are produced directly by such an instruction if frS is the target register for the instruction. The contents of frS are produced indirectly by such an instruction if frS is the final target register of a sequence of one or more floating-point move instructions, with the input to the sequence having been produced directly by such an instruction."
  2878.            OtherRegs=""
  2879.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else &#10;           b = (rA)&#10;         EA = b + (rB)&#10;         MEM(EA, 4) = frS[32-63]"/>
  2880.         <Mnemonic
  2881.            Form="stfiwx frS,rA,rB"
  2882.            Notes="Store the low order 32 bits of the specified floating point register. The addressing mode is register indirect with index."/>
  2883.     </Instruction>
  2884.     <Instruction>
  2885.         <Details
  2886.            Name="Store Floating-Point Single"
  2887.            Description="The contents of register frS are converted to single-precision and stored into the word in memory addressed by EA. Note that the value to be stored should be in single-precision format prior to the execution of the stfs instruction."
  2888.            OtherRegs=""
  2889.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + EXTS(d)&#10;        MEM(EA,4) = SINGLE(frS)&#10;        "/>
  2890.         <Mnemonic
  2891.            Form="stfs frS,d(rA)"
  2892.            Notes="Store single precision floating point. The addressing mode is register indirect with immediate index."/>
  2893.     </Instruction>
  2894.     <Instruction>
  2895.         <Details
  2896.            Name="Store Floating-Point Single with Update"
  2897.            Description="EA is the sum (rA) + d.&#10;&#10;The contents of frS are converted to single-precision and stored into the word in memory addressed by EA. Note that the value to be stored should be in single-precision format prior to the execution of the stfsu instruction.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2898.            OtherRegs=""
  2899.            Pseudocode="        EA = (rA) + EXTS(d)&#10;        MEM(EA, 4) = SINGLE(frS)&#10;        rA = EA"/>
  2900.         <Mnemonic
  2901.            Form="stfsu frS,d(rA)"
  2902.            Notes="Store single precision floating point with update. The addressing mode is register indirect with immediate index."/>
  2903.     </Instruction>
  2904.     <Instruction>
  2905.         <Details
  2906.            Name="Store Floating-Point Single with Update Indexed"
  2907.            Description="EA is the sum (rA) + (rB).&#10;&#10;The contents of frS are converted to single-precision and stored into the word in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2908.            OtherRegs=""
  2909.            Pseudocode="         EA = (rA) + (rB)&#10;         MEM(EA, 4) = SINGLE(frS)&#10;         rA = EA"/>
  2910.         <Mnemonic
  2911.            Form="stfsux frS,rA,rB"
  2912.            Notes="Store single precision floating point with update. The addressing mode is register indirect with index."/>
  2913.     </Instruction>
  2914.     <Instruction>
  2915.         <Details
  2916.            Name="Store Floating-Point Single Indexed"
  2917.            Description="EA is the sum (rA|0) + (rB).&#10;&#10;The contents of register frS are converted to single-precision and stored into the word in memory addressed by EA."
  2918.            OtherRegs=""
  2919.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        MEM(EA,4) = SINGLE(frS)"/>
  2920.         <Mnemonic
  2921.            Form="stfsx frS,rA,rB"
  2922.            Notes="Store single precision floating point. The addressing mode is register indirect with index."/>
  2923.     </Instruction>
  2924.     <Instruction>
  2925.         <Details
  2926.            Name="Store Halfword"
  2927.            Description="EA is the sum (rA|0) + d. The contents of the low-order 16 bits of rS are stored into the halfword in memory addressed by EA."
  2928.            OtherRegs=""
  2929.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + EXTS(d)&#10;        MEM(EA,2) = rS[48-63]"/>
  2930.         <Mnemonic
  2931.            Form="sth rS,d(rA)"
  2932.            Notes="Store halfword. The addressing mode is register indirect with immediate index."/>
  2933.     </Instruction>
  2934.     <Instruction>
  2935.         <Details
  2936.            Name="Store Halfword Byte-Reverse Indexed"
  2937.            Description=""
  2938.            OtherRegs=""
  2939.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         MEM(EA,2) = rS[56-63] || rS[48-55]&#10;         "/>
  2940.         <Mnemonic
  2941.            Form="sthbrx rS,rA,rB"
  2942.            Notes="Store byte-reversed halfword. The addressing mode is register indirect with index."/>
  2943.     </Instruction>
  2944.     <Instruction>
  2945.         <Details
  2946.            Name="Store Halfword with Update"
  2947.            Description="EA is the sum (rA) + d. The contents of the low-order 16 bits of rS are stored into the halfword in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2948.            OtherRegs=""
  2949.            Pseudocode="        EA = (rA) + EXTS(d)&#10;        MEM(EA, 2) = rS[48-63]&#10;        rA = EA"/>
  2950.         <Mnemonic
  2951.            Form="sthu rS,d(rA)"
  2952.            Notes="Store halfword with update. The addressing mode is register indirect with immediate index."/>
  2953.     </Instruction>
  2954.     <Instruction>
  2955.         <Details
  2956.            Name="Store Halfword with Update Indexed"
  2957.            Description="EA is the sum (rA) + (rB). The contents of the low-order 16 bits of rS are stored into the halfword in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  2958.            OtherRegs=""
  2959.            Pseudocode="        EA = (rA) + (rB)&#10;        MEM(EA, 2) = rS[48-63]&#10;        rA = EA"/>
  2960.         <Mnemonic
  2961.            Form="sthux rS,rA,rB"
  2962.            Notes="Store halfword with update. The addressing mode is register indirect with index."/>
  2963.     </Instruction>
  2964.     <Instruction>
  2965.         <Details
  2966.            Name="Store Halfword Indexed"
  2967.            Description="EA is the sum (rA|0) + (rB). The contents of the low-order 16 bits of rS are stored into the halfword in memory addressed by EA."
  2968.            OtherRegs=""
  2969.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        MEM(EA,2) = rS[48-63]"/>
  2970.         <Mnemonic
  2971.            Form="sthx rS,rA,rB"
  2972.            Notes="Store halfword. The addressing mode is register indirect with index."/>
  2973.     </Instruction>
  2974.     <Instruction>
  2975.         <Details
  2976.            Name="Store Multiple Word"
  2977.            Description="EA is the sum (rA|0) + d.&#10;&#10;n = (32 - rS).&#10;&#10;n consecutive words starting at EA are stored from the low-order 32 bits of GPRs rS through r31. For example, if rS = 30, 2 words are stored.&#10;&#10;EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions.&#10;&#10;Note: In some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results."
  2978.            OtherRegs=""
  2979.            Pseudocode="       if rA = 0 then &#10;         b = 0&#10;       else&#10;         b = (rA)&#10;       EA = b + EXTS(d)&#10;       r = rS&#10;       do while r &lt;= 31&#10;         MEM(EA, 4) = GPR(r)[32-63]&#10;         r = r + 1&#10;         EA = EA + 4"/>
  2980.         <Mnemonic
  2981.            Form="stmw rS,d(rA)"
  2982.            Notes="Store multiple word. The addressing mode is register indirect with immediate index."/>
  2983.     </Instruction>
  2984.     <Instruction>
  2985.         <Details
  2986.            Name="Store String Word Immediate"
  2987.            Description="EA is (rA|0). Let n = NB if NB != 0, n = 32 if NB = '0'; n is the number of bytes to store. Let nr = CEIL(n / 4); nr is the number of registers to supply data.&#10;&#10;n consecutive bytes starting at EA are stored from GPRs rS through rS + nr - 1. Data is stored from the low-order four bytes of each GPR. Bytes are stored left to right from each register. The sequence of registers&#10;wraps around through r0 if required.&#10;&#10;Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. For additional information about data alignment exceptions.&#10;&#10;Note: In some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results."
  2988.            OtherRegs=""
  2989.            Pseudocode="        if rA = 0 then &#10;          EA = 0&#10;        else&#10;          EA = (rA)&#10;        if NB = 0 then &#10;          n = 32&#10;        else&#10;          n = NB&#10;        r = rS - 1&#10;        i = 32&#10;        do while n &gt; 0&#10;          if i = 32 then &#10;            r = r + 1 (mod 32)&#10;          MEM(EA,1) = GPR(r)[i to i + 7]&#10;          i = i + 8&#10;          if i = 64 then &#10;            i = 32&#10;          EA = EA + 1&#10;          n = n - 1"/>
  2990.         <Mnemonic
  2991.            Form="stswi rS,rA,NB"
  2992.            Notes="Store string word. The number of bytes to store is specified by an immediate. The addressing mode is register indirect."/>
  2993.     </Instruction>
  2994.     <Instruction>
  2995.         <Details
  2996.            Name="Store String Word Indexed"
  2997.            Description="EA is the sum (rA|0) + (rB). Let n = XER[25-31]; n is the number of bytes to store. Let nr = CEIL(n / 4); nr is the number of registers to supply data.&#10;&#10;n consecutive bytes starting at EA are stored from GPRs rS through rS + nr - 1. Data is stored from the low-order four bytes of each GPR. Bytes are stored left to right from each register. The sequence of registers wraps around through r0 if required. If n = '0', no bytes are stored.&#10;&#10;Under certain conditions (for example, segment boundary crossing) the data alignment exception handler may be invoked. For additional information about data alignment exceptions.&#10;&#10;Note: In some implementations, this instruction is likely to have a greater latency and take longer to execute, perhaps much longer, than a sequence of individual load or store instructions that produce the same results."
  2998.            OtherRegs=""
  2999.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        n = XER[25-31]&#10;        r = rS - 1&#10;        i = 32&#10;        do while n &gt; 0&#10;          if i = 32 then &#10;            r = r + 1 (mod 32)&#10;          MEM(EA, 1) = GPR(r)[i to i + 7]&#10;          i = i + 8&#10;          if i = 64 then &#10;            i = 32&#10;          EA = EA + 1&#10;          n = n - 1"/>
  3000.         <Mnemonic
  3001.            Form="stswx rS,rA,rB"
  3002.            Notes="Store string word. The number of bytes to store is specified by XER[25-31]. The addressing mode is register indirect with index."/>
  3003.     </Instruction>
  3004.     <Instruction>
  3005.         <Details
  3006.            Name="Store Word"
  3007.            Description="EA is the sum (rA|0) + d. The contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA."
  3008.            OtherRegs=""
  3009.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + EXTS(d)&#10;        MEM(EA,4) = rS[32-63]"/>
  3010.         <Mnemonic
  3011.            Form="stw rS,d(rA)"
  3012.            Notes="Store word. The addressing mode is register indirect with immediate index."/>
  3013.     </Instruction>
  3014.     <Instruction>
  3015.         <Details
  3016.            Name="Store Word Byte-Reverse Indexed"
  3017.            Description="EA is the sum (rA|0) + (rB). The contents of the low-order eight bits of rS are stored into bits [0-7] of the word in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are stored into bits [8-15] of the word in memory addressed by EA. The contents of the subsequent eight low-order bits of rS are stored into bits [16-23] of the word in memory addressed by EA. The contents of the subsequent eight low- order bits of rS are stored into bits [24-31] of the word in memory addressed by EA."
  3018.            OtherRegs=""
  3019.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         MEM(EA,4) = rS[56-63] || rS[48-55] || rS[40-47] || rS[32-39]"/>
  3020.         <Mnemonic
  3021.            Form="stwbrx rS,rA,rB"
  3022.            Notes="Store byte-reversed word. The addressing mode is register indirect with index."/>
  3023.     </Instruction>
  3024.     <Instruction>
  3025.         <Details
  3026.            Name="Store Word Conditional Indexed"
  3027.            Description="EA is the sum (rA|0) + (rB). If the reserved bit is set, the stwcx. instruction stores rS to effective address (rA + rB), clears the reserved bit, and sets CR0[EQ]. If the reserved bit is not set, the stwcx. instruction does not do a store; it leaves the reserved bit cleared and clears CR0[EQ]. Software must look at CR0[EQ] to see if the stwcx. was successful.&#10;&#10;The reserved bit is set by the lwarx instruction. The reserved bit is cleared by any stwcx. instruction to any address, and also by snooping logic if it detects that another processor does any kind of store to the block indicated in the reservation buffer when reserved is set.&#10;&#10;If a reservation exists, and the memory address specified by the stwcx. instruction is the same as that specified by the load and reserve instruction that established the reservation, the contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA and the reservation is cleared.&#10;&#10;If a reservation exists, but the memory address specified by the stwcx. instruction is not the same as that specified by the load and reserve instruction that established the reservation, the reservation is cleared, and it is undefined whether the contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA.&#10;&#10;If no reservation exists, the instruction completes without altering memory.&#10;&#10;CR0 field is set to reflect whether the store operation was performed as follows:&#10;&#10;      CR0[LT GT EQ S0] = 0b00 || store_performed || XER[SO]&#10;&#10;EA must be a multiple of four. If it is not, either the system alignment exception handler is invoked or the results are boundedly undefined. For additional information about alignment and DSI exceptions.&#10;&#10;The granularity with which reservations are managed is implementation-dependent. Therefore, the memory to be accessed by the load and reserve and store conditional instructions should be allocated by a system library program."
  3028.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO"
  3029.            Pseudocode="         if rA = 0 then &#10;           b = 0&#10;         else &#10;           b = (rA)&#10;         EA = b + (rB)&#10;         if RESERVE then&#10;           if RESERVE_ADDR = physical_addr(EA)&#10;             MEM(EA, 4) = rS[32-63]&#10;             CR0 = '00' || '1' || XER[SO]&#10;           else&#10;             u = undefined 1-bit value&#10;             if u then &#10;               MEM(EA, 4) = rS[32-63]&#10;             CR0 = '00' || u || XER[SO]&#10;           RESERVE = 0&#10;         else&#10;           CR0 = '00' || '0' || XER[SO]"/>
  3030.         <Mnemonic
  3031.            Form="stwcx. rS,rA,rB"
  3032.            Notes="Store word if reservation exists. The addressing mode is register indirect with index."/>
  3033.     </Instruction>
  3034.     <Instruction>
  3035.         <Details
  3036.            Name="Store Word with Update"
  3037.            Description="EA is the sum (rA) + d. The contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  3038.            OtherRegs=""
  3039.            Pseudocode="        EA = (rA) + EXTS(d)&#10;        MEM(EA, 4) = rS[32-63]&#10;        rA = EA"/>
  3040.         <Mnemonic
  3041.            Form="stwu rS,d(rA)"
  3042.            Notes="Store word with update. The addressing mode is register indirect with immediate index."/>
  3043.     </Instruction>
  3044.     <Instruction>
  3045.         <Details
  3046.            Name="Store Word with Update Indexed"
  3047.            Description="EA is the sum (rA) + (rB). The contents of the low-order 32 bits of rS are stored into the word in memory addressed by EA.&#10;&#10;EA is placed into rA.&#10;&#10;If rA = '0', the instruction form is invalid."
  3048.            OtherRegs=""
  3049.            Pseudocode="        EA = (rA) + (rB)&#10;        MEM(EA, 4) = rS[32-63]&#10;        rA = EA"/>
  3050.         <Mnemonic
  3051.            Form="stwux rS,rA,rB"
  3052.            Notes="Store word with update. The addressing mode is register indirect with index."/>
  3053.     </Instruction>
  3054.     <Instruction>
  3055.         <Details
  3056.            Name="Store Word Indexed"
  3057.            Description="EA is the sum (rA|0) + (rB). The contents of the low-order 32 bits of rS are is stored into the word in memory addressed by EA."
  3058.            OtherRegs=""
  3059.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b =    (rA)&#10;        EA = b + (rB)&#10;        MEM(EA,4) = rS[32-63]"/>
  3060.         <Mnemonic
  3061.            Form="stwx rS,rA,rB"
  3062.            Notes="Store word. The addressing mode is register indirect with index."/>
  3063.     </Instruction>
  3064.     <Instruction>
  3065.         <Details
  3066.            Name="Subtract From"
  3067.            Description="The sum ! (rA) + (rB) + 1 is placed into rD."
  3068.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO               (if Rc = '1')&#10; * XER:&#10;   Affected: SO, OV                       (if OE = '1')"
  3069.            Pseudocode="         rD = ! (rA) + (rB) + 1"/>
  3070.         <Mnemonic
  3071.            Form="subf rD,rA,rB"
  3072.            Notes="Subtract from."/>
  3073.         <Mnemonic
  3074.            Form="subf. rD,rA,rB"
  3075.            Notes="Subtract from and record."/>
  3076.         <Mnemonic
  3077.            Form="subfo rD,rA,rB"
  3078.            Notes="Subtract from overflow."/>
  3079.         <Mnemonic
  3080.            Form="subfo. rD,rA,rB"
  3081.            Notes="Subtract from overflow and record."/>
  3082.         <Mnemonic
  3083.            Form="sub rD,rA,rB"
  3084.            Notes="Equivalent to: subf rD,rB,rA."/>
  3085.     </Instruction>
  3086.     <Instruction>
  3087.         <Details
  3088.            Name="Subtract from Carrying"
  3089.            Description="The sum ! (rA) + (rB) + 1 is placed into rD."
  3090.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO              (if Rc = '1')&#10;   Note: CR0 field may not reflect the infinitely precise result if overflow occurs.&#10; * XER:&#10;   Affected: CA&#10;   Affected: SO, OV                       (if OE = '1')&#10;   Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit&#10;   result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  3091.            Pseudocode="        rD = ! (rA) + (rB) + 1"/>
  3092.         <Mnemonic
  3093.            Form="subfc rD,rA,rB"
  3094.            Notes="Subtract from carrying."/>
  3095.         <Mnemonic
  3096.            Form="subfc. rD,rA,rB"
  3097.            Notes="Subtract from carrying and record."/>
  3098.         <Mnemonic
  3099.            Form="subfco rD,rA,rB"
  3100.            Notes="Subtract from carrying and overflow."/>
  3101.         <Mnemonic
  3102.            Form="subfco. rD,rA,rB"
  3103.            Notes="Subtract from carrying overflow and record."/>
  3104.         <Mnemonic
  3105.            Form="subc rD,rA,rB"
  3106.            Notes="Equivalent to: subfc rD,rB,rA."/>
  3107.     </Instruction>
  3108.     <Instruction>
  3109.         <Details
  3110.            Name="Subtract from Extended"
  3111.            Description="The sum ! (rA) + (rB) + XER[CA] is placed into rD."
  3112.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO             (if Rc = '1')&#10;   Note: CR0 field may not reflect the infinitely precise result if overflow occurs.&#10; * XER:&#10;   Affected: CA&#10;   Affected: SO, OV                      (if OE = '1')&#10;   Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit&#10;   result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  3113.            Pseudocode="       rD = ! (rA) + (rB) + XER[CA]"/>
  3114.         <Mnemonic
  3115.            Form="subfe rD,rA,rB"
  3116.            Notes="Subtract from extended."/>
  3117.         <Mnemonic
  3118.            Form="subfe. rD,rA,rB"
  3119.            Notes="Subtract from extended and record."/>
  3120.         <Mnemonic
  3121.            Form="subfeo rD,rA,rB"
  3122.            Notes="Subtract from extended and overflow."/>
  3123.         <Mnemonic
  3124.            Form="subfeo. rD,rA,rB"
  3125.            Notes="Subtract from extended overflow and record."/>
  3126.     </Instruction>
  3127.     <Instruction>
  3128.         <Details
  3129.            Name="Subtract from Immediate Carrying"
  3130.            Description="The sum ! (rA) + EXTS(SIMM) + 1 is placed into rD."
  3131.            OtherRegs="XER:&#10;   Affected: CA&#10;   Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit&#10;   result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  3132.            Pseudocode="         rD = ! (rA) + EXTS(SIMM) + 1"/>
  3133.         <Mnemonic
  3134.            Form="subfic rD,rA,SIMM"
  3135.            Notes="Subtract from sign-extended imm16 and carrying."/>
  3136.     </Instruction>
  3137.     <Instruction>
  3138.         <Details
  3139.            Name="Subtract from Minus One Extended"
  3140.            Description="The sum ! (rA) + XER[CA] + (64)1 is placed into rD."
  3141.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO             (if Rc = '1')&#10;   Note: CR0 field may not reflect the infinitely precise result if overflow occurs.&#10; * XER:&#10;   Affected: CA&#10;   Affected: SO, OV                      (if OE = '1')&#10;   Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit&#10;   result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  3142.            Pseudocode="       rD = ! (rA) + XER[CA] - 1"/>
  3143.         <Mnemonic
  3144.            Form="subfme rD,rA"
  3145.            Notes="Subtract from minus one extended."/>
  3146.         <Mnemonic
  3147.            Form="subfme. rD,rA"
  3148.            Notes="Subtract from minus one extended and record."/>
  3149.         <Mnemonic
  3150.            Form="subfmeo rD,rA"
  3151.            Notes="Subtract from minus one extended and overflow."/>
  3152.         <Mnemonic
  3153.            Form="subfmeo. rD,rA"
  3154.            Notes="Subtract from minus one extended, overflow and record."/>
  3155.     </Instruction>
  3156.     <Instruction>
  3157.         <Details
  3158.            Name="Subtract from Zero Extended"
  3159.            Description="The sum ! (rA) + XER[CA] is placed into rD."
  3160.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO             (if Rc = '1')&#10;   Note: CR0 field may not reflect the infinitely precise result if overflow occurs.&#10; * XER:&#10;   Affected: CA&#10;   Affected: SO, OV                      (if OE = '1')&#10;   Note: The setting of the affected bits in the XER is mode-dependent, and reflects overflow of the 64-bit&#10;   result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode."
  3161.            Pseudocode="        rD = ! (rA) + XER[CA]"/>
  3162.         <Mnemonic
  3163.            Form="subfze rD,rA"
  3164.            Notes="Subtract from zero extended."/>
  3165.         <Mnemonic
  3166.            Form="subfze. rD,rA"
  3167.            Notes="Subtract from zero extended and record."/>
  3168.         <Mnemonic
  3169.            Form="subfzeo rD,rA"
  3170.            Notes="Subtract from zero extended and overflow."/>
  3171.         <Mnemonic
  3172.            Form="subfzeo. rD,rA"
  3173.            Notes="Subtract from zero extended overflow and record."/>
  3174.     </Instruction>
  3175.     <Instruction>
  3176.         <Details
  3177.            Name="Synchronize"
  3178.            Description="The sync instruction creates a memory barrier. The set of memory accesses that is ordered by the memory barrier depends on the value of the L field.&#10;&#10;L = '0' ('heavyweight sync'). The memory barrier provides an ordering function for the memory accesses associated with all instructions that are executed by the processor executing the sync instruction. The applicable pairs are all pairs ai,bj in which bj is a data access, except that if ai is the memory access caused by an icbi instruction then bj may be performed with respect to the processor executing the sync instruction before ai is performed with respect to that processor.&#10;&#10;L= '1' ('lightweight sync'). The memory barrier provides an ordering function for the memory accesses caused by Load, Store, and dcbz instructions that are executed by the processor executing the sync instruction and for which the specified memory location is in memory that is Memory Coherence Required and is neither Write Through Required nor Caching Inhibited. The applicable pairs are all pairs ai,bj of such accesses except those in which ai is an access caused by a store or dcbz instruction and bj is an access caused by a load instruction.&#10;&#10;L= '2' (ptesync). This variant of the synchronize instruction is designated the page table entry sync and is specified by the extended mnemonic ptesync. This variant has all of the properties of sync with L = '0' and with some additional properties.&#10;&#10;L= '3'. Reserved. The results of executing a sync instruction with L= '3' are boundedly undefined.&#10;&#10;The ordering done by the memory barrier is cumulative. The sync instruction may complete before memory accesses associated with instructions preceding the sync instruction have been performed.&#10;&#10;If L= '0', the sync instruction has the following additional properties:&#10; * Executing the sync instruction ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and that no subsequent instructions are initiated until after the sync instruction completes.&#10; * The sync instruction is execution synchronizing. However, address translation and reference and change recording associated with subsequent instructions may be performed before the sync instruction completes.&#10; * The memory barrier provides the additional ordering function such that if a given instruction that is the result of a Store in set B is executed, all applicable memory accesses in set A have been performed with respect to the processor executing the instruction to the extent required by the associated memory coherence properties. The single exception is that any memory access in set A that is caused by an icbi instruction executed by the processor executing the sync instruction (P1) may not have been performed with respect to P1.&#10;&#10;   The cumulative properties of the barrier apply to the execution of the given instruction as they would to aLoad that returned a value that was the result of a Store in set B.&#10;&#10;If L='2', the sync instruction (ptesync) has the following additional properties:&#10; * The memory barrier created by the ptesync instruction provides an ordering function for the memory accesses associated with all instructions that are executed by the processor executing the ptesync instruction and, as elements of set A, for all reference and change bit updates associated with additional address translations that were performed, by the processor executing the ptesync instruction, before the ptesync instruction is executed. The applicable pairs are all pairs ai,bj in which bj is a data access and ai is not an instruction fetch.&#10; * The ptesync instruction causes all reference and change bit updates associated with address translations that were performed, by the processor executing the ptesync instruction, before the ptesync instruction is executed, to be performed with respect to that processor before the ptesync instruction's memory barrier is created.&#10; * The ptesync instruction provides an ordering function for all stores to the page table caused by store instructions preceding the ptesync instruction with respect to searches of the page table that are performed, by the processor executing the ptesync instruction, after the ptesync instruction completes.  Executing a ptesync instruction ensures that all such stores will be performed, with respect to the processor executing the ptesync instruction, before any implicit accesses to the affected page table entries, by such page table searches, are performed with respect to that processor.&#10; * In conjunction with the tlbie and tlbsync instructions, the ptesync instruction provides an ordering function for TLB invalidations and related memory accesses on other processors as described in the tlbsync instruction description.&#10;&#10;Note: The functions performed by the ptesync instruction may take a significant amount of time to complete, so this form of the instruction should be used only if the functions listed above are needed. Otherwise sync with L = '0' should be used (or sync with L = '1' or eieio, if appropriate).&#10;&#10;This instruction is execution synchronizing."
  3179.            OtherRegs=""
  3180.            Pseudocode=""/>
  3181.         <Mnemonic
  3182.            Form="sync L"
  3183.            Notes="Provides an ordering function for load and store instructions. The effects are cumulative."/>
  3184.     </Instruction>
  3185.     <Instruction>
  3186.         <Details
  3187.            Name="Trap Doubleword"
  3188.            Description="The contents of rA are compared with the contents of rB. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked."
  3189.            OtherRegs=""
  3190.            Pseudocode="         a = (rA)&#10;         b = (rB)&#10;         if (a &lt; b) &amp; TO[0] then TRAP&#10;         if (a &gt; b) &amp; TO[1] then TRAP&#10;         if (a = b) &amp; TO[2] then TRAP&#10;         if (a &lt;U b) &amp; TO[3] then TRAP&#10;         if (a &gt;U b) &amp; TO[4] then TRAP"/>
  3191.         <Mnemonic
  3192.            Form="td TO,rA,rB"
  3193.            Notes="Trap conditional doubleword."/>
  3194.         <Mnemonic
  3195.            Form="tdlt"
  3196.            Notes="Trap doubleword if less than."/>
  3197.         <Mnemonic
  3198.            Form="tdle"
  3199.            Notes="Trap doubleword if less than or equal."/>
  3200.         <Mnemonic
  3201.            Form="tdeq"
  3202.            Notes="Trap doubleword if equal."/>
  3203.         <Mnemonic
  3204.            Form="tdge rA,rB"
  3205.            Notes="Trap doubleword if greater than or equal. Equivalent to: td 12,rA,rB."/>
  3206.         <Mnemonic
  3207.            Form="tdgt"
  3208.            Notes="Trap doubleword if greater than."/>
  3209.         <Mnemonic
  3210.            Form="tdnl"
  3211.            Notes="Trap doubleword if not less than."/>
  3212.         <Mnemonic
  3213.            Form="tdne rA,rB"
  3214.            Notes="Trap doubleword if not equal. Equivalent to: td 24,rA,rB."/>
  3215.         <Mnemonic
  3216.            Form="tdng"
  3217.            Notes="Trap doubleword if not greater than."/>
  3218.         <Mnemonic
  3219.            Form="tdllt"
  3220.            Notes="Trap doubleword if logically less than."/>
  3221.         <Mnemonic
  3222.            Form="tdlle"
  3223.            Notes="Trap doubleword if logically less than or equal."/>
  3224.         <Mnemonic
  3225.            Form="tdlge"
  3226.            Notes="Trap doubleword if logically greater than or equal."/>
  3227.         <Mnemonic
  3228.            Form="tdlgt"
  3229.            Notes="Trap doubleword if logically greater than."/>
  3230.         <Mnemonic
  3231.            Form="tdlnl rA,rB"
  3232.            Notes="Trap doubleword if logically not less than. Equivalent to: td 5,rA,rB."/>
  3233.         <Mnemonic
  3234.            Form="tdlng"
  3235.            Notes="Trap doubleword if logically not greater than."/>
  3236.     </Instruction>
  3237.     <Instruction>
  3238.         <Details
  3239.            Name="Trap Doubleword Immediate"
  3240.            Description="The contents of rA are compared with the sign-extended value of the SIMM field. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked."
  3241.            OtherRegs=""
  3242.            Pseudocode="        a = (rA)&#10;        if (a &lt; EXTS(SIMM)) &amp; TO[0] then TRAP&#10;        if (a &gt; EXTS(SIMM)) &amp; TO[1] then TRAP&#10;        if (a = EXTS(SIMM)) &amp; TO[2] then TRAP&#10;        if (a &lt;U EXTS(SIMM)) &amp; TO[3] then TRAP&#10;        if (a &gt;U EXTS(SIMM)) &amp; TO[4] then TRAP"/>
  3243.         <Mnemonic
  3244.            Form="tdi TO,rA,SIMM"
  3245.            Notes="Trap conditional doubleword with sign extended imm16."/>
  3246.         <Mnemonic
  3247.            Form="tdlti rA,value"
  3248.            Notes="Trap doubleword immediate if less than. Equivalent to: tdi 16,rA,value."/>
  3249.         <Mnemonic
  3250.            Form="tdlei"
  3251.            Notes="Trap doubleword immediate if less than or equal."/>
  3252.         <Mnemonic
  3253.            Form="tdeqi"
  3254.            Notes="Trap doubleword immediate if equal."/>
  3255.         <Mnemonic
  3256.            Form="tdgei"
  3257.            Notes="Trap doubleword immediate if greater than or equal."/>
  3258.         <Mnemonic
  3259.            Form="tdgti"
  3260.            Notes="Trap doubleword immediate if greater than."/>
  3261.         <Mnemonic
  3262.            Form="tdnli"
  3263.            Notes="Trap doubleword immediate if not less than."/>
  3264.         <Mnemonic
  3265.            Form="tdnei rA,value"
  3266.            Notes="Trap doubleword immediate if not equal. Equivalent to: tdi 24,rA,value."/>
  3267.         <Mnemonic
  3268.            Form="tdngi"
  3269.            Notes="Trap doubleword immediate if not greater than."/>
  3270.         <Mnemonic
  3271.            Form="tdllti"
  3272.            Notes="Trap doubleword immediate if logically less than."/>
  3273.         <Mnemonic
  3274.            Form="tdllei"
  3275.            Notes="Trap doubleword immediate if logically less than or equal."/>
  3276.         <Mnemonic
  3277.            Form="tdlgei"
  3278.            Notes="Trap doubleword immediate if logically greater than or equal."/>
  3279.         <Mnemonic
  3280.            Form="tdlgti"
  3281.            Notes="Trap doubleword immediate if logically greater than."/>
  3282.         <Mnemonic
  3283.            Form="tdlnli"
  3284.            Notes="Trap doubleword immediate if logically not less than."/>
  3285.         <Mnemonic
  3286.            Form="tdlngi"
  3287.            Notes="Trap doubleword immediate if logically not greater than."/>
  3288.     </Instruction>
  3289.     <Instruction>
  3290.         <Details
  3291.            Name="Translation Lookaside Buffer Invalidate All"
  3292.            Description="The entire translation lookaside buffer (TLB) is invalidated (that is, all entries are removed).&#10;&#10;The TLB is invalidated regardless of the settings of MSR[IR] and MSR[DR]. The invalidation is done without reference to the SLB, segment table, or segment registers.&#10;&#10;This instruction does not cause the entries to be invalidated in other processors.&#10;&#10;This is a supervisor-level instruction and optional in the PowerPC Architecture."
  3293.            OtherRegs=""
  3294.            Pseudocode="       All TLB entries = invalid"/>
  3295.         <Mnemonic
  3296.            Form="tlbia"
  3297.            Notes="Translation lookaside buffer invalidate all entries."/>
  3298.     </Instruction>
  3299.     <Instruction>
  3300.         <Details
  3301.            Name="Translation Lookaside Buffer Invalidate Entry"
  3302.            Description="The contents of rB[0-15] must be 0x0000. If the L field of the instruction is '1' let the page size be large; otherwise let the page size be 4 KB.&#10;&#10;All TLB entries that have all of the following properties are made invalid on all processors that are in the same partition as the processor executing the tlbie instruction.&#10; * The entry translates a virtual address for which VPN[32 to 79- p] is equal to rB[16 to 63- p].&#10; * The page size of the entry matches the page size specified by the L field of the instruction.&#10;&#10;Additional TLB entries may also be made invalid on any processor that is in the same partition as the processor executing the tlbie instruction.&#10;&#10;MSR[SF] must be '1' when this instruction is executed; otherwise the results are undefined.&#10;&#10;The operation performed by this instruction is ordered by the eieio (or sync or ptesync) instruction with respect to a subsequent tlbsync instruction executed by the processor executing the tlbie instruction. The operations caused by tlbie and tlbsync are ordered by eieio as a third set of operations, which is independent of the other two sets that eieio orders.&#10;&#10;This is a supervisor-level instruction and optional in the PowerPC Architecture."
  3303.            OtherRegs=""
  3304.            Pseudocode="        if L = 0 then &#10;          pg_size = 4 KB&#10;        else &#10;          pg_size = large page size&#10;        p = log_base_2(pg_size)&#10;        for each processor in the partition&#10;          for each TLB entry&#10;            if (entry_VPN[32 to 79-p] = (RB[16 to63-p]) &amp; (entry_pg_size = pg_size) then &#10;              TLB entry = invalid"/>
  3305.         <Mnemonic
  3306.            Form="tlbie rB,"
  3307.            Notes="Translation lookaside buffer invalidate specified entry."/>
  3308.     </Instruction>
  3309.     <Instruction>
  3310.         <Details
  3311.            Name="Translation Lookaside Buffer Invalidate Entry Local"
  3312.            Description="The contents of rB[0-15] must be 0x0000. If the L field of the instruction is '1' let the page size be large; other-&#10;wise let the page size be 4KB.&#10;&#10;All TLB entries that have all of the following properties are made invalid on the processor which executes this instruction.&#10; * The entry translates a virtual address for which VPN[32 to (79- p)] is equal to rB[16 to (63- p)].&#10; * The page size of the entry matches the page size specified by the L field of the instruction.&#10;&#10;Only TLB entries on the processor executing this instruction are affected. rB[52 - 63] must be zero. MSR[SF] must be '1' when this instruction is executed; otherwise the results are undefined.&#10;&#10;The operation performed by this instruction is ordered by the eieio (or sync or ptesync) instruction with respect to a subsequent tlbsync instruction executed by the processor executing the tlbiel instruction. The operations caused by tlbiel and tlbsync are ordered by eieio as a third set of operations, which is independent of the other two sets that eieio orders.&#10;&#10;This is a supervisor-level instruction and optional in the PowerPC Architecture.&#10;&#10;Support of large pages for tlbiel is optional. On implementations that do not support large pages for tlbiel, the following properties apply:&#10; *    The syntax of the instruction is 'tlbiel rB'.&#10; *    Bit [10] of the instruction is a reserved bit.&#10; *    In the RTL, the first three lines and the third from last line are ignored.&#10; *    The last list item in the paragraph that begins 'All TLB entries ...', namely 'The page size of the entry matches the page size specified by the L field of the instruction', is ignored.&#10;&#10;Note: To synchronize the completion of this processor local form of tlbie, only a ptesync is required (tlbsync should not be used)."
  3313.            OtherRegs=""
  3314.            Pseudocode="         if L = 0&#10;           then pg_size = 4 KB&#10;           else pg_size = large page size&#10;         p = log_base_2(pg_size)&#10;         for each TLB entry&#10;           if (entry_VPN[32 to (79-p)] = rB[16 to (63-p)] &amp; (entry_pg_size = pg_size) then&#10;             TLB entry = invalid"/>
  3315.         <Mnemonic
  3316.            Form="tlbiel rB,L"
  3317.            Notes="Translation lookaside buffer invalidate specified entry for the local processor."/>
  3318.     </Instruction>
  3319.     <Instruction>
  3320.         <Details
  3321.            Name="TLB Synchronize"
  3322.            Description="If an implementation sends a broadcast for tlbie then it will also send a broadcast for tlbsync. Executing a tlbsync instruction ensures that all tlbie instructions previously executed by the processor executing the tlbsync instruction have completed on all other processors.&#10;&#10;The operation performed by this instruction is treated as a caching-inhibited and guarded data access with respect to the ordering done by eieio.&#10;&#10;This instruction is supervisor-level and optional in the PowerPC Architecture.&#10;&#10;Note: tlbsync should not be used to synchronize the completion of tlbiel."
  3323.            OtherRegs=""
  3324.            Pseudocode=""/>
  3325.         <Mnemonic
  3326.            Form="tlbsync"
  3327.            Notes="Ensures that all tlbie instructions previously executed by the processor have completed on all other processors"/>
  3328.     </Instruction>
  3329.     <Instruction>
  3330.         <Details
  3331.            Name="Trap Word"
  3332.            Description="The contents of the low-order 32 bits of rA are compared with the contents of the low-order 32 bits of rB. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked."
  3333.            OtherRegs=""
  3334.            Pseudocode="        a = EXTS(rA[32-63])&#10;        b = EXTS(rB[32-63])&#10;        if (a &lt; b) &amp; TO[0] then &#10;          TRAP&#10;        if (a &gt; b) &amp; TO[1] then &#10;          TRAP&#10;        if (a = b) &amp; TO[2] then &#10;          TRAP&#10;        if (a &lt;U b) &amp; TO[3] then &#10;          TRAP&#10;        if (a &gt;U b) &amp; TO[4] then &#10;          TRAP"/>
  3335.         <Mnemonic
  3336.            Form="tw TO,rA,rB"
  3337.            Notes="Trap conditional word."/>
  3338.         <Mnemonic
  3339.            Form="trap"
  3340.            Notes="Trap unconditionally. Equivalent to: tw 31,0,0."/>
  3341.         <Mnemonic
  3342.            Form="twlt"
  3343.            Notes="Trap word if less than."/>
  3344.         <Mnemonic
  3345.            Form="twle"
  3346.            Notes="Trap word if less than or equal."/>
  3347.         <Mnemonic
  3348.            Form="tweq rA,rB"
  3349.            Notes="Trap word if equal. Equivalent to: tw 4,rA,rB."/>
  3350.         <Mnemonic
  3351.            Form="twge"
  3352.            Notes="Trap word if greater than or equal."/>
  3353.         <Mnemonic
  3354.            Form="twgt"
  3355.            Notes="Trap word if greater than."/>
  3356.         <Mnemonic
  3357.            Form="twnl"
  3358.            Notes="Trap word if not less than."/>
  3359.         <Mnemonic
  3360.            Form="twne"
  3361.            Notes="Trap word if not equal."/>
  3362.         <Mnemonic
  3363.            Form="twng"
  3364.            Notes="Trap word if not greater than."/>
  3365.         <Mnemonic
  3366.            Form="twllt"
  3367.            Notes="Trap word if logically less than."/>
  3368.         <Mnemonic
  3369.            Form="twlle"
  3370.            Notes="Trap word if logically less than or equal."/>
  3371.         <Mnemonic
  3372.            Form="twlge rA,rB"
  3373.            Notes="Trap word if logically greater than or equal. Equivalent to: tw 5,rA,rB."/>
  3374.         <Mnemonic
  3375.            Form="twlgt"
  3376.            Notes="Trap word if logically greater than."/>
  3377.         <Mnemonic
  3378.            Form="twlnl"
  3379.            Notes="Trap word if logically not less than."/>
  3380.         <Mnemonic
  3381.            Form="twlng"
  3382.            Notes="Trap word if logically not greater than."/>
  3383.     </Instruction>
  3384.     <Instruction>
  3385.         <Details
  3386.            Name="Trap Word Immediate"
  3387.            Description="The contents of the low-order 32 bits of rA are compared with the sign-extended value of the SIMM field. If any bit in the TO field is set and its corresponding condition is met by the result of the comparison, then the system trap handler is invoked."
  3388.            OtherRegs=""
  3389.            Pseudocode="         a = EXTS(rA[32-63])&#10;         if (a &lt; EXTS(SIMM)) &amp; TO[0] then &#10;           TRAP&#10;         if (a &gt; EXTS(SIMM)) &amp; TO[1] then &#10;           TRAP&#10;         if (a = EXTS(SIMM)) &amp; TO[2] then &#10;           TRAP&#10;         if (a &lt;U EXTS(SIMM)) &amp; TO[3] then &#10;           TRAP&#10;         if (a &gt;U EXTS(SIMM)) &amp; TO[4] then &#10;           TRAP"/>
  3390.         <Mnemonic
  3391.            Form="twi TO,rA,SIMM"
  3392.            Notes="Trap conditional word with sign extended imm16."/>
  3393.         <Mnemonic
  3394.            Form="twlti"
  3395.            Notes="Trap word immediate if less than."/>
  3396.         <Mnemonic
  3397.            Form="twlei"
  3398.            Notes="Trap word immediate if less than or equal."/>
  3399.         <Mnemonic
  3400.            Form="tweqi"
  3401.            Notes="Trap word immediate if equal."/>
  3402.         <Mnemonic
  3403.            Form="twgei"
  3404.            Notes="Trap word immediate if greater than or equal."/>
  3405.         <Mnemonic
  3406.            Form="twgti rA,value"
  3407.            Notes="Trap word immediate if greater than. Equivalent to: twi 8,rA,value."/>
  3408.         <Mnemonic
  3409.            Form="twnli"
  3410.            Notes="Trap word immediate if not less than."/>
  3411.         <Mnemonic
  3412.            Form="twnei"
  3413.            Notes="Trap word immediate if not equal."/>
  3414.         <Mnemonic
  3415.            Form="twngi"
  3416.            Notes="Trap word immediate if not greater than."/>
  3417.         <Mnemonic
  3418.            Form="twllti"
  3419.            Notes="Trap word immediate if logically less than."/>
  3420.         <Mnemonic
  3421.            Form="twllei rA,value"
  3422.            Notes="Trap word immediate if logically less than or equal. Equivalent to: twi 6,rA,value."/>
  3423.         <Mnemonic
  3424.            Form="twlgei"
  3425.            Notes="Trap word immediate if logically greater than or equal."/>
  3426.         <Mnemonic
  3427.            Form="twlgti"
  3428.            Notes="Trap word immediate if logically greater than."/>
  3429.         <Mnemonic
  3430.            Form="twlnli"
  3431.            Notes="Trap word immediate if logically not less than."/>
  3432.         <Mnemonic
  3433.            Form="twlngi"
  3434.            Notes="Trap word immediate if logically not greater than."/>
  3435.     </Instruction>
  3436.     <Instruction>
  3437.         <Details
  3438.            Name="XOR"
  3439.            Description="The contents of rS is XORed with the contents of rB and the result is placed into rA."
  3440.            OtherRegs="* Condition Register (CR0 field):&#10;   Affected: LT, GT, EQ, SO                (if Rc = '1')"
  3441.            Pseudocode="       rA = (rS)+ (rB)"/>
  3442.         <Mnemonic
  3443.            Form="xor rA,rS,rB"
  3444.            Notes="XOR."/>
  3445.         <Mnemonic
  3446.            Form="xor. rA,rS,rB"
  3447.            Notes="XOR and record."/>
  3448.     </Instruction>
  3449.     <Instruction>
  3450.         <Details
  3451.            Name="XOR Immediate"
  3452.            Description="The contents of rS are XORed with 0x0000_0000_0000 || UIMM and the result is placed into rA."
  3453.            OtherRegs=""
  3454.            Pseudocode="        rA = (rS)+ ((48)0 || UIMM)"/>
  3455.         <Mnemonic
  3456.            Form="xori rA,rS,UIMM"
  3457.            Notes="XOR with imm16."/>
  3458.     </Instruction>
  3459.     <Instruction>
  3460.         <Details
  3461.            Name="XOR Immediate Shifted"
  3462.            Description="The contents of rS are XORed with 0x0000_0000 || UIMM || 0x0000 and the result is placed into rA."
  3463.            OtherRegs=""
  3464.            Pseudocode="        rA = (rS)+ ((32)0 || UIMM || (16)0)"/>
  3465.         <Mnemonic
  3466.            Form="xoris rA,rS,UIMM"
  3467.            Notes="XOR with imm16 shifted left by 16 bits."/>
  3468.     </Instruction>
  3469.     <Instruction>
  3470.         <Details
  3471.            Name="Data Stream Stop"
  3472.            Description="Note: A does not represent rA in this instruction.&#10;&#10;If A='0' and a data stream associated with the stream ID specified by STRM exists, this instruction terminates prefetching of that data stream. It has no effect if the specified stream does not exist.&#10;&#10;If A='1', this instruction terminates prefetching of all existing data streams (the STRM field is ignored.)&#10;&#10;In addition, executing a dss instruction ensures that all accesses associated with data stream prefetching caused by preceding dst and dstst instructions that specified the same stream ID as that specified by the dss instruction (A='0'), or by all preceding dst and dstst instructions (A='1'), will be in group G1 with respect to the memory barrier created by a subsequent sync instruction.&#10;&#10;Note: dss and dsall are not supported on the Cell Broadband Engine Processor."
  3473.            OtherRegs=""
  3474.            Pseudocode="         DataStreamPrefetchControl = 'stop' || STRM"/>
  3475.         <Mnemonic
  3476.            Form="dss STRM"
  3477.            Notes="Data stream stop."/>
  3478.         <Mnemonic
  3479.            Form="dssall STRM"
  3480.            Notes="Data stream stop all."/>
  3481.     </Instruction>
  3482.     <Instruction>
  3483.         <Details
  3484.            Name="Data Stream Touch"
  3485.            Description="This instruction initiates a software directed cache prefetch. The instruction is a hint to hardware that performance will probably be improved if the cache blocks containing the specified data stream are fetched into the data cache because the program will probably soon load from the stream.&#10;&#10;The instruction associates the data stream specified by the contents of rA and rB with the stream ID specified by STRM. The instruction defines a data stream STRM as starting at an 'Effective Address' (rA) and having 'Count' units of 'Size' bytes separated by 'Stride' bytes (as specified in rB). The T bit of the instruction indicates whether the data stream is likely to be loaded from fairly frequently in the near future (T ='0') or to be transient and referenced very few times (T ='1').&#10;&#10;The dst instruction does the following:&#10; * Defines the characteristics of a data stream STRM by the contents of rA and rB&#10; * Associates the stream with a specified stream ID, STRM (Range for STRM is 0-3)&#10; * Indicates that the data in the specified stream STRM starting at the address in rA may soon be loaded&#10; * Indicates whether memory locations within the stream are likely to be needed over a longer period of time (T='0') or be treated as transient data (T='1')&#10; * Terminates prefetching from any stream that was previously associated with the specified stream ID, STRM&#10;&#10;The specified data stream is encoded for 64-bit as:&#10; * Effective Address: rA, where rA != '0'&#10; * Block Size: rB[35-39] if rB[35-39] != '0'; otherwise 32&#10; * Block Count: rB[40-47] if rB[40-47] != '0'; otherwise 256&#10; * Block Stride: rB[48-63] if rB[48-63] != '0'; otherwise 32768&#10;&#10;Note: dst and dstt are not supported on the Cell Broadband Engine Processor."
  3486.            OtherRegs=""
  3487.            Pseudocode="         addr[0:63] = (rA)&#10;         DataStreamPrefetchControl = 'start' || STRM || T || (rB) || addr"/>
  3488.         <Mnemonic
  3489.            Form="dst rA,rB,STRM"
  3490.            Notes="Data stream touch."/>
  3491.         <Mnemonic
  3492.            Form="dstt rA,rB,STRM"
  3493.            Notes="Data stream touch transient."/>
  3494.     </Instruction>
  3495.     <Instruction>
  3496.         <Details
  3497.            Name="Data Stream Touch for Store"
  3498.            Description="This instruction initiates a software directed cache prefetch. The instruction is a hint to hardware that performance will probably be improved if the cache blocks containing the specified data stream are fetched into the data cache because the program will probably soon write to (store into) the stream.&#10;&#10;The instruction associates the data stream specified by the contents of registers rA and rB with the stream ID specified by STRM. The instruction defines a data stream STRM as starting at an 'Effective Address' (rA) and having 'Count' units of 'Size' bytes separated by 'Stride' bytes (as specified in rB). The T bit of the instruction indicates whether the data stream is likely to be stored into fairly frequently in the near future (T ='0'), or to be transient and referenced very few times (T ='1').&#10;&#10;The dstst instruction does the following:&#10; * Defines the characteristics of a data stream STRM by the contents of rA and rB&#10; * Associates the stream with a specified stream ID, STRM (Range for STRM is 0-3)&#10; * Indicates that the data in the specified stream STRM starting at the address in rA may soon be stored in to memory&#10; * Indicates whether memory locations within the stream are likely to be stored into fairly frequently in the near future (T='0') or be treated as transient data (T='1')&#10; * Terminates prefetching from any stream that was previously associated with the specified stream ID, STRM.&#10;&#10;The specified data stream is encoded for 64-bit as:&#10; * Effective Address: rA, where rA != '0'&#10; * Block Size: rB[35-39] if rB[35-39] != '0'; otherwise 32&#10; * Block Count: rB[40-47] if rB[40-47] != '0'; otherwise 256&#10; * Block Stride: rB[48-63] if rB[48-63] != '0'; otherwise 32768&#10;&#10;Note: dstst and dststt are not supported on the Cell Broadband Engine Processor."
  3499.            OtherRegs=""
  3500.            Pseudocode="         addr[0:63] = (rA)&#10;         DataStreamPrefetchControl = 'start' || T || static || (rB) || addr"/>
  3501.         <Mnemonic
  3502.            Form="dstst rA,rB,STRM"
  3503.            Notes="Data stream touch for store."/>
  3504.         <Mnemonic
  3505.            Form="dststt rA,rB,STRM"
  3506.            Notes="Data stream touch for store transient."/>
  3507.     </Instruction>
  3508.     <Instruction>
  3509.         <Details
  3510.            Name="Load Vector Element Byte Indexed"
  3511.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB. Let m be the value of bits [60-63] of EA, where m is the byte offset of the byte in its aligned quadword in memory.&#10;&#10;If the processor is in big-endian mode, the byte addressed by EA is loaded into byte m of register vD. If the processor is in little-endian mode, the byte addressed by EA is loaded into byte (15-m) of register vD. The remaining bytes in vD are set to undefined values.&#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3512.            OtherRegs=""
  3513.            Pseudocode="        if rA=0 then &#10;          b = 0    &#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        eb = EA[60:63]&#10;        vD = undefined&#10;        if the processor is in big-endian mode then &#10;          (vD)[eb*8:(eb*8)+7] = MEM(EA,1)&#10;        else &#10;          (vD)[120-(eb*8):127-(eb*8)] = MEM(EA,1)"/>
  3514.         <Mnemonic
  3515.            Form="lvebx vD,rA,rB"
  3516.            Notes="Load vector element byte. The addressing mode is register indirect with index."/>
  3517.     </Instruction>
  3518.     <Instruction>
  3519.         <Details
  3520.            Name="Load Vector Element Halfword Indexed"
  3521.            Description="Let the effective address EA be the result of ANDing the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB with the value 0xFFFF_FFFF_FFFF_FFFE. Let m be the value of bits [60-62] of EA, where m is the halfword offset of the halfword in its aligned quadword in memory.&#10;&#10;If the processor is in big-endian mode, the halfword addressed by EA is loaded into halfword m of register vD. If the processor is in little-endian mode, the halfword addressed by EA is loaded into halfword (7-m) of register vD. The remaining halfwords in register vD are set to undefined values. &#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3522.            OtherRegs=""
  3523.            Pseudocode="        if rA=0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = (b + (rB)) &amp; 0xFFFF_FFFF_FFFF_FFFE&#10;        eb = EA[60:63]&#10;        vD = undefined&#10;        if the processor is in big-endian mode then &#10;          (vD)[(eb*8):(eb*8)+15] = MEM(EA,2)&#10;        else&#10;          (vD)[112-(eb*8):127-(eb*8)] = MEM(EA,2)"/>
  3524.         <Mnemonic
  3525.            Form="lvehx vD,rA,rB"
  3526.            Notes="Load vector element halfword. The addressing mode is register indirect with index."/>
  3527.     </Instruction>
  3528.     <Instruction>
  3529.         <Details
  3530.            Name="Load Vector Element Word Indexed"
  3531.            Description="Let the effective address EA be the result of ANDing the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB with the value 0xFFFF_FFFF_FFFF_FFFC. Let m be the value of bits 60:61 of EA, where m is the word offset of the word in its aligned quadword in memory.&#10;&#10;If the processor is in big-endian mode, the word addressed by EA is loaded into word m of register vD. If the processor is in little-endian mode, the word addressed by EA is loaded into word (3-m) of register vD. The remaining words in register vD are set to undefined values. Figure 6-5 shows this instruction.&#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3532.            OtherRegs="None"
  3533.            Pseudocode="         if rA=0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = (b + (rB)) &amp; 0xFFFF_FFFF_FFFF_FFFC&#10;         eb = EA[60:63]&#10;         vD = undefined&#10;         if the processor is in big-endian mode then &#10;           (vD)[eb*8:(eb*8)+31]= MEM(EA,4)&#10;         else &#10;           (vD)[96-(eb*8):127-(eb*8)]= MEM(EA,4)"/>
  3534.         <Mnemonic
  3535.            Form="lvewx vD,rA,rB"
  3536.            Notes="Load vector element word. The addressing mode is register indirect with index."/>
  3537.     </Instruction>
  3538.     <Instruction>
  3539.         <Details
  3540.            Name="Load Vector for Shift Left"
  3541.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB. Let sh be the value of bits[ 60-63] of the effective address (EA).&#10;&#10;Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F. Bytes sh:sh+15 of X are placed into register vD. &#10;&#10;The lvsl instruction followed by a Vector Permute (vperm) would do a simulated alignment of a four-element floating-point vector misaligned on quadword boundary at address 0x0....C."
  3542.            OtherRegs=""
  3543.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else &#10;          b = (rA)&#10;        addr[0:63] = b + (rB)&#10;        sh = addr[60:63]                                        &#10;        if sh = 0x0 then &#10;          vD[0-127] = 0x000102030405060708090A0B0C0D0E0F                                         &#10;        if sh = 0x1 then &#10;          vD[0-127] = 0x0102030405060708090A0B0C0D0E0F10                                          &#10;        if sh = 0x2 then &#10;          vD[0-127] = 0x02030405060708090A0B0C0D0E0F1011&#10;        if sh = 0x3 then &#10;          vD[0-127] = 0x030405060708090A0B0C0D0E0F101112                                          &#10;        if sh = 0x4 then &#10;          vD[0-127] = 0x0405060708090A0B0C0D0E0F10111213            &#10;        if sh = 0x5 then &#10;          vD[0-127] = 0x05060708090A0B0C0D0E0F1011121314&#10;        if sh = 0x6 then &#10;          vD[0-127] = 0x060708090A0B0C0D0E0F101112131415&#10;        if sh = 0x7 then &#10;          vD[0-127] = 0x0708090A0B0C0D0E0F10111213141516&#10;        if sh = 0x8 then &#10;          vD[0-127] = 0x08090A0B0C0D0E0F1011121314151617&#10;        if sh = 0x9 then &#10;          vD[0-127] = 0x090A0B0C0D0E0F101112131415161718&#10;        if sh = 0xA then &#10;          vD[0-127] = 0x0A0B0C0D0E0F10111213141516171819&#10;        if sh = 0xB then &#10;          vD[0-127] = 0x0B0C0D0E0F101112131415161718191A&#10;        if sh = 0xC then &#10;          vD[0-127] = 0x0C0D0E0F101112131415161718191A1B&#10;        if sh = 0xD then &#10;          vD[0-127] = 0x0D0E0F101112131415161718191A1B1C&#10;        if sh = 0xE then &#10;          vD[0-127] = 0x0E0F101112131415161718191A1B1C1D&#10;        if sh = 0xF then &#10;          vD[0-127] = 0x0F101112131415161718191A1B1C1D1E"/>
  3544.         <Mnemonic
  3545.            Form="lvsl vD,rA,rB"
  3546.            Notes="Load vector for shift left."/>
  3547.     </Instruction>
  3548.     <Instruction>
  3549.         <Details
  3550.            Name="Load Vector for Shift Right"
  3551.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB. Let sh be the value of bits [60-63] of EA.&#10;&#10;Let X be the 32-byte value 0x00 || 0x01 || 0x02 || ... || 0x1E || 0x1F. Bytes (16-sh):(31-sh) of X are placed into register vD.&#10;&#10;Note: lvsl and lvsr can be used to create the permute control vector to be used by a subsequent vperm instruction. Let X and Y be the contents of vA and vB specified by the vperm. The control vector created by lvsl causes the vperm to select the high-order 16 bytes of the result of shifting the 32-byte value X || Y left by sh bytes. The control vector created by vsr causes the vperm to select the low-order 16 bytes of the result of shifting X || Y right by sh bytes.&#10;&#10;These instructions can also be used to rotate or shift the contents of a vector register by sh bytes. For rotating, the vector register to be rotated should be specified as both vA and vB for vperm. For shifting left, the vB register for vperm should contain all zeros and vA should contain the value to be shifted, and vice versa for shifting right. Figure 6-6 shows a similar instruction only in that figure the shift is to the left."
  3552.            OtherRegs=""
  3553.            Pseudocode="        if rA = 0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        sh = EA[60:63]&#10;        if sh=0x0 then &#10;          (vD) = 0x101112131415161718191A1B1C1D1E1F&#10;        if sh=0x1 then &#10;          (vD) = 0x0F101112131415161718191A1B1C1D1E&#10;        if sh=0x2 then &#10;          (vD) = 0x0E0F101112131415161718191A1B1C1D&#10;        if sh=0x3 then &#10;          (vD) = 0x0D0E0F101112131415161718191A1B1C&#10;        if sh=0x4 then &#10;          (vD) = 0x0C0D0E0F101112131415161718191A1B&#10;        if sh=0x5 then &#10;          (vD) = 0x0B0C0D0E0F101112131415161718191A&#10;        if sh=0x6 then &#10;          (vD) = 0x0A0B0C0D0E0F10111213141516171819&#10;        if sh=0x7 then &#10;          (vD) = 0x090A0B0C0D0E0F101112131415161718&#10;        if sh=0x8 then &#10;          (vD) = 0x08090A0B0C0D0E0F1011121314151617&#10;        if sh=0x9 then &#10;          (vD) = 0x0708090A0B0C0D0E0F10111213141516&#10;        if sh=0xA then &#10;          (vD) = 0x060708090A0B0C0D0E0F101112131415&#10;        if sh=0xB then &#10;          (vD) = 0x05060708090A0B0C0D0E0F1011121314&#10;        if sh=0xC then &#10;          (vD) = 0x0405060708090A0B0C0D0E0F10111213&#10;        if sh=0xD then &#10;          (vD) = 0x030405060708090A0B0C0D0E0F101112&#10;        if sh=0xE then &#10;          (vD) = 0x02030405060708090A0B0C0D0E0F1011&#10;        if sh=0xF then &#10;          (vD) = 0x0102030405060708090A0B0C0D0E0F10"/>
  3554.         <Mnemonic
  3555.            Form="lvsr vD,rA,rB"
  3556.            Notes="Load vector for shift right."/>
  3557.     </Instruction>
  3558.     <Instruction>
  3559.         <Details
  3560.            Name="Load Vector Indexed"
  3561.            Description="Let the effective address EA be the result of ANDing the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB with the value 0xFFFF_FFFF_FFFF_FFF0.&#10;&#10;If the processor is in big-endian mode, the quadword in memory addressed by EA is loaded into register vD.&#10;&#10;If the processor is in little-endian mode, the doubleword addressed by EA is loaded into register vD[64-127] and the doubleword addressed by (EA+8) is loaded into register vD[0-63]. &#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3562.            OtherRegs=""
  3563.            Pseudocode="           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = (b + (rB)) &amp; 0xFFFF_FFFF_FFFF_FFF0&#10;         if the processor is in big-endian mode then &#10;           vD = MEM(EA,16)&#10;         else &#10;           vD = MEM(EA+8,8) || MEM(EA,8)"/>
  3564.         <Mnemonic
  3565.            Form="lvx vD,rA,rB"
  3566.            Notes="Load vector. The addressing mode is register indirect with index."/>
  3567.     </Instruction>
  3568.     <Instruction>
  3569.         <Details
  3570.            Name="Load Vector Indexed Last"
  3571.            Description="Let the effective address EA be the result of ANDing the sum of the contents of register rA, or the value 0 if rA is equal to 0, and the contents of register rB with the value 0xFFFF_FFFF_FFFF_FFF0.&#10;&#10;If the processor is in big-endian mode, the quadword addressed by EA is loaded into register vD.&#10;&#10;If the processor is in little-endian mode, the doubleword addressed by EA is loaded into bits [64-127] of register vD and the doubleword addressed by (EA+8) is loaded into bits [0-63] of register vD.&#10;&#10;This instruction provides a hint that the quadword addressed by EA will probably not be needed again by the program in the near future.&#10;&#10;Note that on some implementations, the hint provided by the lvxl instruction and the corresponding hint provided by the Store Vector Indexed Last (stvxl) instruction are applied to the entire cache block containing the specified quadword. On such implementations, the effect of the hint may be to cause that cache block to be considered a likely candidate for reuse when space is needed in the cache for a new block. Thus, on such implementations, the hint should be used with caution if the cache block containing the quadword also contains data that may be needed by the program in the near future. Also, the hint may be used before the last reference in a sequence of references to the quadword if the subsequent references are likely to occur sufficiently soon that the cache block containing the quadword is not likely to be displaced from the cache before the last reference. &#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3572.            OtherRegs=""
  3573.            Pseudocode="        if rA=0 then &#10;          b = 0           &#10;        else&#10;          b = (rA)&#10;        EA = (b + (rB)) &amp; 0xFFFF_FFFF_FFFF_FFF0&#10;        if the processor is in big-endian mode then &#10;          vD = MEM(EA,16)&#10;        else &#10;          vD = MEM(EA+8,8) || MEM(EA,8)&#10;        mark_cache_block_as_not_likely_to_be_needed_again_anytime_soon(EA)"/>
  3574.         <Mnemonic
  3575.            Form="lvxl vD,rA,rB"
  3576.            Notes="Load vector. The addressing mode is register indirect with index. The quadword at the effective address will probably not be used in future."/>
  3577.     </Instruction>
  3578.     <Instruction>
  3579.         <Details
  3580.            Name="Move from Vector Status and Control Register"
  3581.            Description="The contents of the VSCR are placed into register vD.&#10;&#10;Note: The programmer should assume that mtvscr and mfvscr take substantially longer to execute than&#10;other VX instructions."
  3582.            OtherRegs=""
  3583.            Pseudocode="         vD = 96(0) || (VSCR)"/>
  3584.         <Mnemonic
  3585.            Form="mfvscr vD"
  3586.            Notes="Move from vector status and control register."/>
  3587.     </Instruction>
  3588.     <Instruction>
  3589.         <Details
  3590.            Name="Move to Vector Status and Control Register"
  3591.            Description="The contents of register vB are placed into the VSCR."
  3592.            OtherRegs=""
  3593.            Pseudocode="        VSCR = (vB)[96:127]"/>
  3594.         <Mnemonic
  3595.            Form="mtvscr vB"
  3596.            Notes="Move to vector status and control register."/>
  3597.     </Instruction>
  3598.     <Instruction>
  3599.         <Details
  3600.            Name="Store Vector Element Byte Indexed"
  3601.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB. Let m be the value of bits [60:63] of EA, where m is the byte offset of the byte in its aligned quadword in memory.&#10;&#10;If the processor is in big-endian mode, byte m of register vS is stored into the byte in memory addressed by EA. If the processor is in little-endian mode, byte (15-m) of register vS is stored into the byte addressed by EA.&#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3602.            OtherRegs=""
  3603.            Pseudocode="         if rA=0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         eb = EA[60:63]&#10;         if the processor is in big-endian mode then &#10;           MEM(EA,1) = (vS)[eb*8:(eb*8)+7]&#10;         else &#10;           MEM(EA,1) = (vS)[120-(eb * 8):127-(eb * 8)]"/>
  3604.         <Mnemonic
  3605.            Form="stvebx vS,rA,rB"
  3606.            Notes="Store vector element byte. The addressing mode is register indirect with index."/>
  3607.     </Instruction>
  3608.     <Instruction>
  3609.         <Details
  3610.            Name="Store Vector Element Halfword Indexed"
  3611.            Description="Let the effective address EA be the result of ANDing the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB with 0xFFFF_FFFF_FFFF_FFFE. Let m be the value of bits [60:62] of EA, where m is the halfword offset of the halfword in its aligned quadword in memory.&#10;&#10;If the processor is in big-endian mode, halfword m of register vS is stored into the halfword addressed by EA.  If the processor is in little-endian mode, halfword (7-m) of register vS is stored into the halfword addressed by EA. &#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3612.            OtherRegs=""
  3613.            Pseudocode="         if rA=0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = (b + (rB)) &amp; 0xFFFF_FFFF_FFFF_FFFE&#10;         eb = EA[0:63]&#10;         if the processor is in big-endian mode then &#10;           MEM(EA,2) = vS[eb*8:(eb*8)+15]&#10;         else &#10;           MEM(EA,2) = vS[112-(eb*8):127-(eb*8)]"/>
  3614.         <Mnemonic
  3615.            Form="stvehx vS,rA,rB"
  3616.            Notes="Store vector element halfword. The addressing mode is register indirect with index."/>
  3617.     </Instruction>
  3618.     <Instruction>
  3619.         <Details
  3620.            Name="Store Vector Element Word Indexed"
  3621.            Description="Let the effective address EA be the result of ANDing the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB with 0xFFFF_FFFF_FFFF_FFFC. Let m be the value of bits [60:61] of EA, where m is the word offset of the word in its aligned quadword in memory.&#10;&#10;If the processor is in big-endian mode, word m of register vS is stored into the word addressed by EA. If the processor is in little-endian mode, word (3-m) of register vS is stored into the word addressed by EA.&#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3622.            OtherRegs=""
  3623.            Pseudocode="         if rA=0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = (b + (rB)) &amp; 0xFFFF_FFFF_FFFF_FFFC&#10;         eb = EA[60:63]&#10;         if the processor is in big-endian mode then &#10;           MEM(EA,4) = (vS)[eb*8:(eb*8)+31]&#10;         else &#10;           MEM(EA,4) = (vS)[96-(eb*8):127-(eb*8)]"/>
  3624.         <Mnemonic
  3625.            Form="stvewx vS,rA,rB"
  3626.            Notes="Store vector element word. The addressing mode is register indirect with index."/>
  3627.     </Instruction>
  3628.     <Instruction>
  3629.         <Details
  3630.            Name="Store Vector Indexed"
  3631.            Description="Let the effective address EA be the result of ANDing the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB with 0xFFFF_FFFF_FFFF_FFF0.&#10;&#10;If the processor is in big-endian mode, the contents of register vS are stored into the quadword addressed by EA. If the processor is in little-endian mode, the contents of register vS[64-127] are stored into the double-word addressed by EA, and the contents of register vS[0-63] are stored into the doubleword addressed by (EA+8).&#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3632.            OtherRegs=""
  3633.            Pseudocode="        if rA=0 then &#10;          b = 0&#10;        else &#10;          b = (rA)&#10;        EA = (b + (rB)) &amp; 0xFFFF_FFFF_FFFF_FFF0&#10;        if the processor is in big-endian mode then &#10;          MEM(EA,16) = (vS)&#10;        else &#10;          MEM(EA,16) = (vS)[64:127] || (vS)[0:63]"/>
  3634.         <Mnemonic
  3635.            Form="stvx vS,rA,rB"
  3636.            Notes="Store vector. The addressing mode is register indirect with index."/>
  3637.     </Instruction>
  3638.     <Instruction>
  3639.         <Details
  3640.            Name="Store Vector Indexed Last"
  3641.            Description="Let the effective address EA be the result of ANDing the sum of the contents of register rA, or the value 0 if rA is equal to '0', and the contents of register rB with 0xFFFF_FFFF_FFFF_FFF0.&#10;&#10;If the processor is in big-endian mode, the contents of register vS are stored into the quadword addressed by EA. If the processor is in little-endian mode, the contents of vS[64-127] are stored into the doubleword addressed by EA, and the contents of vS[0-63] are stored into the doubleword addressed by (EA+8). The stvxl instruction provides a hint that the quadword addressed by EA will probably not be needed again by the program in the near future.&#10;&#10;Note that on some implementations, the hint provided by the stvxl instruction is applied to the entire cache block containing the specified quadword. On such implementations, the effect of the hint may be to cause that cache block to be considered a likely candidate for reuse when space is needed in the cache for a new block. Thus, on such implementations, the hint should be used with caution if the cache block containing the quadword also contains data that may be needed by the program in the near future. Also, the hint may be used before the last reference in a sequence of references to the quadword if the subsequent references are likely to occur sufficiently soon that the cache block containing the quadword is not likely to be displaced from the cache before the last reference. &#10;&#10;Note: Little-endian mode is not supported on the Cell Broadband Engine Processor."
  3642.            OtherRegs=""
  3643.            Pseudocode="         if rA=0 then &#10;           b = 0 &#10;         else &#10;           b = (rA)&#10;         EA = (b + (rB)) &amp; 0xFFFF_FFFF_FFFF_FFF0&#10;         if the processor is in big-endian mode then &#10;           MEM(EA,16) = (vS)&#10;         else &#10;           MEM(EA,16) = (vS)[64:127] || (vS)[0:63]&#10;         mark_cache_block_as_not_likely_to_be_needed_again_anytime_soon(EA)"/>
  3644.         <Mnemonic
  3645.            Form="stvxl vS,rA,rB"
  3646.            Notes="Store vector. The addressing mode is register indirect with index. The quadword at the effective address will probably not be used in future."/>
  3647.     </Instruction>
  3648.     <Instruction>
  3649.         <Details
  3650.            Name="Vector Add Carryout Unsigned Word"
  3651.            Description="Each unsigned-integer word element i register n vA is added to the corresponding unsigned-integer word element in vB. The carry out of bit [0] of the 32-bit sum is zero-extended to 32 bits and placed into the corresponding word element of register vD."
  3652.            OtherRegs=""
  3653.            Pseudocode="        do i=0 to 127 by 32&#10;          aop[0:32] = ZeroExtend((vA)[i:i+31],33)&#10;          bop[0:32] = ZeroExtend((vB)[i:i+31],33)&#10;          temp[0:32] = aop[0:32] +int bop[0:32]&#10;          (vD)[i:i+31] = ZeroExtend(temp[0],32)&#10;        end"/>
  3654.         <Mnemonic
  3655.            Form="vaddcuw vD,vA,vB"
  3656.            Notes="Vector add carryout unsigned word."/>
  3657.     </Instruction>
  3658.     <Instruction>
  3659.         <Details
  3660.            Name="Vector Add Floating Point"
  3661.            Description="Each single-precision floating-point element in register vA is added to the corresponding single-precision floating-point element in register vB. Each intermediate result is rounded and placed in the corresponding single-precision floating-point element in register vD.&#10;&#10;If VSCR[NJ] ='1', every denormalized operand element is truncated to a '0' of the same sign before the operation is carried out, and each denormalized result element truncates to a '0' of the same sign."
  3662.            OtherRegs=""
  3663.            Pseudocode="         do i = 0 to 127 by 32&#10;           (vD)[i:i+31] = RndToNearFP32((vA)[i:i+31] +fp (vB)[i:i+31])&#10;         end"/>
  3664.         <Mnemonic
  3665.            Form="vaddfp vD,vA,vB"
  3666.            Notes="Vector add floating point."/>
  3667.     </Instruction>
  3668.     <Instruction>
  3669.         <Details
  3670.            Name="Vector Add Signed Byte Saturate"
  3671.            Description="Each signed-integer byte element in register vA is added to the corresponding signed-integer byte element in register vB. If the intermediate result is greater than 2^7-1, it saturates to 2^7-1. If the intermediate result is less than -2^7, it saturates to -2^7. If saturation occurs, the SAT bit is set. The signed-integer result is placed into the corresponding element of register vD."
  3672.            OtherRegs="Vector status and control register (VSCR):&#10;   Affected: SAT"
  3673.            Pseudocode="         do i=0 to 127 by 8&#10;           aop[0:8] = SignExtend((vA)[i:i+7],9)&#10;           bop[0:8] = SignExtend((vB)[i:i+7],9)  &#10;           temp[0:8] = aop[0:8] +int bop[0:8]&#10;           (vD)[i:i+7] = SItoSIsat(temp[0:8],8)&#10;         end"/>
  3674.         <Mnemonic
  3675.            Form="vaddsbs vD,vA,vB"
  3676.            Notes="Vector add signed byte saturate."/>
  3677.     </Instruction>
  3678.     <Instruction>
  3679.         <Details
  3680.            Name="Vector Add Signed Halfword Saturate"
  3681.            Description="Each element of vaddshs is a halfword.&#10;&#10;Each signed-integer halfword element in register vA is added to the corresponding signed-integer halfword element in register vB. If the intermediate result is greater than 2^15-1, it saturates to 2^15-1. If the intermediate result is less than -2^15, it saturates to -2^15. If saturation occurs, the SAT bit is set. The result is placed into the corresponding halfword element of register vD."
  3682.            OtherRegs="Vector status and control register (VSCR):&#10;    Affected: SAT"
  3683.            Pseudocode="         do i=0 to 127 by 16&#10;           aop[0:16] = SignExtend((vA)[i:i+15],16)&#10;           bop[0:16] = SignExtend((vB)[i:i+15],16)&#10;           temp[0:16] = aop[0:16] +int bop[0:16]&#10;           (vD)[i:i+15] = SItoSIsat(temp[0:16],16)&#10;         end"/>
  3684.         <Mnemonic
  3685.            Form="vaddshs vD,vA,vB"
  3686.            Notes="Vector add signed halfword saturate."/>
  3687.     </Instruction>
  3688.     <Instruction>
  3689.         <Details
  3690.            Name="Vector Add Signed Word Saturate"
  3691.            Description="Each element of vaddsws is a word.&#10;&#10;Each signed-integer word element in register vA is added to the corresponding signed-integer word element in register vB. If the intermediate result is greater than 2^31-1, it saturates to 2^31-1. If the intermediate result is less than -2^31, it saturates to -2^31. If saturation occurs, the SAT bit is set. The signed-integer result is placed into the corresponding word element of register vD."
  3692.            OtherRegs="Vector status and control register (VSCR):&#10;   Affected: SAT"
  3693.            Pseudocode="        do i=0 to 127 by 32&#10;          aop[0:32] = SignExtend((vA)[i:i+31],33)&#10;          bop[0:32] = SignExtend((vB)[i:i+31],33)&#10;          temp[0:32] = aop[0:32] +int bop[0:32]&#10;          (vD)[i:i+31] = SItoSIsat(temp[0:32],32)&#10;        end"/>
  3694.         <Mnemonic
  3695.            Form="vaddsws vD,vA,vB"
  3696.            Notes="Vector add signed word saturate."/>
  3697.     </Instruction>
  3698.     <Instruction>
  3699.         <Details
  3700.            Name="Vector Add Unsigned Byte Modulo"
  3701.            Description="Each integer byte element in register vA is modulo added to the corresponding integer byte element in register register vB. The integer result is placed into the corresponding byte element of register vD.&#10;&#10;Note: The vaddubm instruction can be used for unsigned or signed integers."
  3702.            OtherRegs=""
  3703.            Pseudocode="         do i=0 to 127 by 8&#10;           (vD)[i:i+7] = (vA)[i:i+7] +int (vB)[i:i+7]&#10;         end"/>
  3704.         <Mnemonic
  3705.            Form="vaddubm vD,vA,vB"
  3706.            Notes="Vector add unsigned byte modulo."/>
  3707.     </Instruction>
  3708.     <Instruction>
  3709.         <Details
  3710.            Name="Vector Add Unsigned Byte Saturate"
  3711.            Description="Each unsigned-integer byte element in register vA is added to the corresponding unsigned-integer byte element in register vB. If the intermediate result is greater than 2^8-1, it saturates to 2^8-1. If saturation occurs, the SAT bit is set. The unsigned-integer result is placed into the corresponding byte element of register vD."
  3712.            OtherRegs="Vector status and control register (VSCR):&#10;   Affected: SAT"
  3713.            Pseudocode="        do i=0 to 127 by 8&#10;          aop[0:8] = ZeroExtend((vA)[i:i+7],9)&#10;          bop[0:8] = ZeroExtend((vB)[i:i+7],9)&#10;          temp[0:8] = aop[0:8] +int bop[0:8]&#10;          (vD)[i:i+7] = UItoUIsat(temp[0:8],8)&#10;        end"/>
  3714.         <Mnemonic
  3715.            Form="vaddubs vD,vA,vB"
  3716.            Notes="Vector add unsigned byte saturate."/>
  3717.     </Instruction>
  3718.     <Instruction>
  3719.         <Details
  3720.            Name="Vector Add Unsigned Halfword Modulo"
  3721.            Description="Each integer halfword element in register vA is added to the corresponding integer halfword element in register vB. The integer result is placed into the corresponding halfword element of register vD.&#10;&#10;Note: The vadduhm instruction can be used for unsigned or signed integers."
  3722.            OtherRegs=""
  3723.            Pseudocode="         do i=0 to 127 by 16&#10;           (vD)[i:i+15] = (vA)[i:i+15] +int (vB)[i:i+15]&#10;         end"/>
  3724.         <Mnemonic
  3725.            Form="vadduhm vD,vA,vB"
  3726.            Notes="Vector add unsigned halfword modulo."/>
  3727.     </Instruction>
  3728.     <Instruction>
  3729.         <Details
  3730.            Name="Vector Add Unsigned Halfword Saturate"
  3731.            Description="Each unsigned-integer halfword element in register vA is added to the corresponding unsigned-integer half- word element in register vB. If the intermediate result is greater than 2^16-1, it saturates to 2^16-1. If saturation occurs, the SAT bit is set. The unsigned-integer result is placed into the corresponding halfword element of register vD."
  3732.            OtherRegs="Vector status and control register (VSCR):&#10;   Affected: SAT"
  3733.            Pseudocode="        do i=0 to 127 by 16&#10;          aop[0:16] = ZeroExtend((vA)[i:i+15],17)&#10;          bop[0:16] = ZeroExtend((vB)[i:i+15],17)&#10;          temp[0:16] = aop[0:16] +int bop[0:16]&#10;          (vD)[i:i+15] = UItoUIsat(temp[0:16],16)&#10;        end"/>
  3734.         <Mnemonic
  3735.            Form="vadduhs vD,vA,vB"
  3736.            Notes="Vector add unsigned halfword saturate."/>
  3737.     </Instruction>
  3738.     <Instruction>
  3739.         <Details
  3740.            Name="Vector Add Unsigned Word Modulo"
  3741.            Description="Each integer word element in register vA is modulo added to the corresponding integer word element in register vB. The integer result is placed into the corresponding word element of register vD.&#10;&#10;Note: The vadduwm instruction can be used for unsigned or signed integers."
  3742.            OtherRegs=""
  3743.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = (vA)[i:i+31] +int (vB)[i:i+31]&#10;         end"/>
  3744.         <Mnemonic
  3745.            Form="vadduwm vD,vA,vB"
  3746.            Notes="Vector add unsigned word modulo."/>
  3747.     </Instruction>
  3748.     <Instruction>
  3749.         <Details
  3750.            Name="Vector Add Unsigned Word Saturate"
  3751.            Description="Each unsigned-integer word element in register vA is added to the corresponding unsigned-integer word element in register vB. If the intermediate result is greater than 2^32-1, it saturates to 2^32-1. If saturation occurs, the SAT bit is set. The unsigned-integer result is placed into the corresponding word element in register vD."
  3752.            OtherRegs="Vector status and control register (VSCR):&#10;   Affected: SAT"
  3753.            Pseudocode="        do i=0 to 127 by 3&#10;          aop[0:32] = ZeroExtend((vA)[i:i+31],33)&#10;          bop[0:32] = ZeroExtend((vB)[i:i+31],33)&#10;          temp[0:32] = aop[0:32] +int bop[0:32]&#10;          (vD)[i:i+31] = UItoUIsat(temp[0:32],32)&#10;        end"/>
  3754.         <Mnemonic
  3755.            Form="vadduws vD,vA,vB"
  3756.            Notes="Vector add unsigned word saturate."/>
  3757.     </Instruction>
  3758.     <Instruction>
  3759.         <Details
  3760.            Name="Vector Logical AND"
  3761.            Description="The contents of register vA are bitwise ANDed with the contents of register vB and the result is placed into register vD."
  3762.            OtherRegs=""
  3763.            Pseudocode=""/>
  3764.         <Mnemonic
  3765.            Form="vand vD,vA,vB"
  3766.            Notes="Vector logical AND."/>
  3767.     </Instruction>
  3768.     <Instruction>
  3769.         <Details
  3770.            Name="Vector Logical AND with Complement"
  3771.            Description="The contents of register vA are ANDed with the one's complement of the contents of register vB and the result is placed into register vD."
  3772.            OtherRegs=""
  3773.            Pseudocode=""/>
  3774.         <Mnemonic
  3775.            Form="vandc vD,vA,vB"
  3776.            Notes="Vector logical AND with complement."/>
  3777.     </Instruction>
  3778.     <Instruction>
  3779.         <Details
  3780.            Name="Vector Average Signed Byte"
  3781.            Description="Each signed-integer byte element in register vA is added to the corresponding signed-integer byte element in register vB, producing a 9-bit signed-integer sum. The sum is incremented by '1'. The high-order 8 bits of the result are placed into the corresponding byte element in register vD."
  3782.            OtherRegs=""
  3783.            Pseudocode="         do i=0 to 127 by 8&#10;           aop[0:8] = SignExtend((vA)[i:i+7],9)&#10;           bop[0:8] = SignExtend((vB)[i:i+7],9)&#10;           temp[0:8] = aop[0:8] +int bop[0:8] +int 1&#10;           (vD)[i:i+7] = temp[0:7]&#10;         end"/>
  3784.         <Mnemonic
  3785.            Form="vavgsb vD,vA,vB"
  3786.            Notes="Vector average signed byte."/>
  3787.     </Instruction>
  3788.     <Instruction>
  3789.         <Details
  3790.            Name="Vector Average Signed Halfword"
  3791.            Description="Each signed-integer halfword element in register vA is added to the corresponding signed-integer halfword element in register vB, producing an 17-bit signed-integer sum. The sum is incremented by '1'. The high-order 16 bits of the result are placed into the corresponding halfword element in register vD."
  3792.            OtherRegs=""
  3793.            Pseudocode="        do i=0 to 127 by 16&#10;          aop[0:16] = SignExtend((vA)[i:i+15],17)&#10;          bop[0:16] = SignExtend((vB)[i:i+15],17)&#10;          temp[0:16] = aop[0:15] +int bop[0:15] +int 1&#10;          (vD)[i:i+15] = temp[0:15]&#10;        end"/>
  3794.         <Mnemonic
  3795.            Form="vavgsh vD,vA,vB"
  3796.            Notes="Vector average signed halfword."/>
  3797.     </Instruction>
  3798.     <Instruction>
  3799.         <Details
  3800.            Name="Vector Average Signed Word"
  3801.            Description="Each signed-integer word element in register vA is added to the corresponding signed-integer word element in register vB, producing a 33-bit signed-integer sum. The sum is incremented by '1'. The high-order 32 bits of the result are placed into the corresponding word element of register vD."
  3802.            OtherRegs=""
  3803.            Pseudocode="         do i=0 to 127 by 32&#10;           aop[0:32] = SignExtend((vA)[i:i+31],33)&#10;           bop[0:32] = SignExtend((vB)[i:i+31],33)&#10;           temp[0:32] = aop[0:32] +int bop[0:32] +int 1&#10;           (vD)[i:i+31] = temp[0:31]&#10;         end"/>
  3804.         <Mnemonic
  3805.            Form="vavgsw vD,vA,vB"
  3806.            Notes="Vector average signed word."/>
  3807.     </Instruction>
  3808.     <Instruction>
  3809.         <Details
  3810.            Name="Vector Average Unsigned Byte"
  3811.            Description="Each unsigned-integer byte element in register vA is added to the corresponding unsigned-integer byte element in register vB, producing a 9-bit unsigned-integer sum. The sum is incremented by '1'. The high-order 8 bits of the result are placed into the corresponding element of register vD."
  3812.            OtherRegs=""
  3813.            Pseudocode="        do i=0 to 127 by 8&#10;          aop[0:8] = ZeroExtend((vA)[i:i+7],9)&#10;          bop[0:8] = ZeroExtend((vB)[i:i+7],9)&#10;          temp[0:8] = aop[0:8] +int bop[0:8] +int 1&#10;          (vD)[i:i+7] = temp[0:7]&#10;        end"/>
  3814.         <Mnemonic
  3815.            Form="vavgub vD,vA,vB"
  3816.            Notes="Vector average unsigned byte."/>
  3817.     </Instruction>
  3818.     <Instruction>
  3819.         <Details
  3820.            Name="Vector Average Unsigned Halfword"
  3821.            Description="Each unsigned-integer halfword element in register vA is added to the corresponding unsigned-integer half-word element in register vB, producing a 17-bit unsigned-integer. The sum is incremented by '1'. The high-order 16 bits of the result are placed into the corresponding halfword element of register vD."
  3822.            OtherRegs=""
  3823.            Pseudocode="        do i=0 to 127 by 16&#10;          aop[0:16] = ZeroExtend((vA)[i:i+15],17)&#10;          bop[0:16] = ZeroExtend((vB)[i:i+15],17)&#10;          temp[0:16] = aop[0:16] +int bop[0:16] +int 1&#10;          (vD)[i:i+15] = temp[0:15]&#10;        end"/>
  3824.         <Mnemonic
  3825.            Form="vavguh vD,vA,vB"
  3826.            Notes="Vector average unsigned halfword."/>
  3827.     </Instruction>
  3828.     <Instruction>
  3829.         <Details
  3830.            Name="Vector Average Unsigned Word"
  3831.            Description="Each unsigned-integer word element in register vA is added to the corresponding unsigned-integer word&#10;element in register vB, producing an 33-bit unsigned-integer sum. The sum is incremented by '1'. The highorder&#10;32 bits of the result are placed into the corresponding word element of register vD."
  3832.            OtherRegs=""
  3833.            Pseudocode="        do i=0 to 127 by 32&#10;          aop[0:32] = ZeroExtend((vA)[i:i+31],33)&#10;          bop[0:32] = ZeroExtend((vB)[i:i+31],33)&#10;          temp[0:32] = aop[0:32] +int bop[0:32] +int 1&#10;          (vD)[i:i+31] = temp[0:31]&#10;        end&#10;        "/>
  3834.         <Mnemonic
  3835.            Form="vavguw vD,vA,vB"
  3836.            Notes="Vector average unsigned word."/>
  3837.     </Instruction>
  3838.     <Instruction>
  3839.         <Details
  3840.            Name="Vector Convert from Signed Fixed-Point Word"
  3841.            Description="Each signed fixed-point integer word element in register vB is converted to the nearest single-precision floating-point value. The result is divided by 2^UIMM (UIMM = unsigned immediate value) and placed into the corresponding word element in register vD."
  3842.            OtherRegs=""
  3843.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = CnvtSI32ToFP32((vB)[i:i+31]) /fp 2^UIMM&#10;         end"/>
  3844.         <Mnemonic
  3845.            Form="vcfsx vD,vB,UIMM"
  3846.            Notes="Vector convert from signed fixed-point word."/>
  3847.     </Instruction>
  3848.     <Instruction>
  3849.         <Details
  3850.            Name="Vector Convert from Unsigned Fixed-Point Word"
  3851.            Description="Each unsigned fixed-point integer word element in regiser vB is converted to the nearest single-precision floating-point value. The result is divided by 2^UIMM and placed into the corresponding word element in register vD."
  3852.            OtherRegs=""
  3853.            Pseudocode="        do i=0 to 127 by 32&#10;          (vD)[i:i+31] = CnvtUI32ToFP32((vB)[i:i+31]) /fp 2^UIMM&#10;        end"/>
  3854.         <Mnemonic
  3855.            Form="vcfux vD,vB,UIMM"
  3856.            Notes="Vector convert from unsigned fixed-point word."/>
  3857.     </Instruction>
  3858.     <Instruction>
  3859.         <Details
  3860.            Name="Vector Compare Bounds Floating Point"
  3861.            Description="Each single-precision floating-point word element in register vA is compared to the corresponding single-precision floating-point element in register vB. A 2-bit value is formed that indicates whether the element in register vA is within the bounds specified by the element in register vB, as follows.&#10;&#10;Bit [0] of the 2-bit value is '0' if the element in register vA is less than or equal to the element in register vB, and is '1' otherwise. Bit [1] of the 2-bit value is '0' if the element in register vA is greater than or equal to the negative of the element in register vB, and is '1' otherwise.&#10;&#10;The 2-bit value is placed into the high-order two bits of the corresponding word element (bits [0-1] for word element 0, bits [32-33] for word element 1, bits [64-65] for word element 2, bits [96-97] for word element 3) of register vD and the remaining bits of the element are set to '0'.&#10;&#10;If Rc='1', CR Field 6 is set to indicate whether all four elements in register vA are within the bounds specified by the corresponding element in register vB, as follows:&#10; * CR6 = 0b00 || all_within_bounds || 0&#10;&#10;Note: If any single-precision floating-point word element in register vB is negative; the corresponding element in register vA is out of bounds. Note that if a vA or a vB element is a NaN, the two high order bits of the corresponding result will both have the value '1'.&#10;&#10;If VSCR[NJ] ='1', every denormalized operand element is truncated to '0' before the comparison is made."
  3862.            OtherRegs="Condition register (CR6):&#10;    Affected: Bit [2]       (if Rc ='1')"
  3863.            Pseudocode="         do i=0 to 127 by 32&#10;           le = ((vA)[i:i+31] &lt;=fp (vB)[i:i+31])&#10;           ge = ((vA)[i:i+31] &gt;=fp -(vB)[i:i+31])&#10;           (vD)[i:i+31] = !le || !ge || {30}0&#10;         end&#10;         if Rc=1 then&#10;           ib = (vD = {128}0)&#10;           CR[24:27] = 0b00 || ib || 0b0&#10;         end"/>
  3864.         <Mnemonic
  3865.            Form="vcmpbfp vD,vA,vB"
  3866.            Notes="Vector compare bounds floating point."/>
  3867.         <Mnemonic
  3868.            Form="vcmpbfp. vD,vA,vB"
  3869.            Notes="Vector compare bounds floating point and record."/>
  3870.     </Instruction>
  3871.     <Instruction>
  3872.         <Details
  3873.            Name="Vector Compare Equal-to-Floating Point"
  3874.            Description="Each single-precision floating-point word element in register vA is compared to the corresponding single-precision floating-point word element in register vB. The corresponding word element in vD is set to all '1's if the element in register vA is equal to the element in register vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 field is set according to all, some, or none of the elements pairs compare equal:&#10; * CR6 = all_equal || 0b0 || none_equal || 0b0&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding result will be 0x0000_0000."
  3875.            OtherRegs="Condition register (CR6):&#10;    Affected: Bits [0-3]    (if Rc ='1')"
  3876.            Pseudocode="         do i=0 to 127 by 32&#10;           if (vA)[i:i+31] =fp (vB)[i:i+31] then &#10;             (vD)[i:i+31] = 0xFFFF_FFFF&#10;           else &#10;             (vD)[i:i+31] = 0x0000_0000&#10;         end&#10;         if Rc=1 then &#10;           t = ( (vD) = {128}1 )&#10;           f = ( (vD) = {128}0 )&#10;           CR[24:27] = t || 0b0 || f || 0b0&#10;         end"/>
  3877.         <Mnemonic
  3878.            Form="vcmpeqfp vD,vA,vB"
  3879.            Notes="Vector compare equal-to-floating point."/>
  3880.         <Mnemonic
  3881.            Form="vcmpeqfp. vD,vA,vB"
  3882.            Notes="Vector compare equal-to-floating point and record."/>
  3883.     </Instruction>
  3884.     <Instruction>
  3885.         <Details
  3886.            Name="Vector Compare Equal-to Unsigned Byte"
  3887.            Description="Each integer byte element in register vA is compared to the corresponding integer byte element in register vB. The corresponding byte element in register vD is set to all '1's if the element in register vA is equal to the element in register vB, and is cleared to all '0's otherwise.&#10;&#10;The CR6 is set according to whether all, some, or none of the elements compare equal:&#10; * CR6 = all_equal || 0b0 || none_equal || 0b0&#10;&#10;Note: vcmpequb[.] can be used for unsigned or signed integers."
  3888.            OtherRegs="Condition register (CR6):&#10;   Affected: Bits [0-3]    (if Rc ='1')"
  3889.            Pseudocode="        do i=0 to 127 by 8&#10;          if (vA)[i:i+7] =int (vB)[i:i+7] then &#10;            (vD)[i:i+7] = {8}1&#10;          else &#10;            (vD)[i:i+7] = {8}0&#10;        end&#10;        if Rc=1 then&#10;          t = ((vD) = {128}1)&#10;          f = ((vD) = {128}0)&#10;          CR[24:27] = t || 0b0 || f || 0b0&#10;        end"/>
  3890.         <Mnemonic
  3891.            Form="vcmpequb vD,vA,vB"
  3892.            Notes="Vector compare equal-to unsigned byte."/>
  3893.         <Mnemonic
  3894.            Form="vcmpequb. vD,vA,vB"
  3895.            Notes="Vector compare equal-to unsigned byte and record."/>
  3896.     </Instruction>
  3897.     <Instruction>
  3898.         <Details
  3899.            Name="Vector Compare Equal-to Unsigned Halfword"
  3900.            Description="Each integer halfword element in vA is compared to the corresponding integer halfword element in vB. The corresponding halfword element in vD is set to all '1's if the element in vA is equal to the element in vB, and is cleared to all '0's otherwise.&#10;&#10;The CR6 is set according to whether all, some, or none of the elements compare equal:&#10; * CR6 = all_equal || 0b0 || none_equal || 0b0.&#10;&#10;Note: vcmpequh[.] can be used for unsigned or signed integers."
  3901.            OtherRegs="Condition register (CR6):&#10;    Affected: Bits [0-3]    (if Rc ='1')"
  3902.            Pseudocode="         do i=0 to 127 by 16&#10;           if (vA)[i:i+15] =int (vB)[i:i+15] then &#10;             vD[i:i+15] = {16}1&#10;           else &#10;             vD[i:i+15] = {16}0&#10;         end&#10;         if Rc=1 then&#10;           t = (vD = {128}1)&#10;           f = (vD = {128}0)&#10;           CR[24:27] = t || 0b0 || f || 0b0&#10;         end"/>
  3903.         <Mnemonic
  3904.            Form="vcmpequh vD,vA,vB"
  3905.            Notes="Vector compare equal-to unsigned halfword."/>
  3906.         <Mnemonic
  3907.            Form="vcmpequh. vD,vA,vB"
  3908.            Notes="Vector compare equal-to unsigned halfword and record."/>
  3909.     </Instruction>
  3910.     <Instruction>
  3911.         <Details
  3912.            Name="Vector Compare Equal-to Unsigned Word"
  3913.            Description="Each integer word element in register vA is compared to the corresponding integer word element in register vB. The corresponding element in register vD is set to all '1's if the element in register vA is equal to the element in register vB, and is cleared to all '0's otherwise.&#10;&#10;The CR6 is set according to whether all, some, or none of the elements compare equal:&#10; * CR6 = all_equal || 0b0 || none_equal || 0b0&#10;&#10;Note: vcmpequw[.] can be used for unsigned or signed integers."
  3914.            OtherRegs="Condition register (CR6):&#10;   Affected: Bits [0-3]    (if Rc ='1')"
  3915.            Pseudocode="        do i=0 to 127 by 32&#10;          if (vA)[i:i+31] =int (vB)i:i+31 then &#10;            (vD)[i:i+31] = {32}1&#10;          else &#10;            (vD)[i:i+31] = {32}0&#10;        end&#10;        if Rc=1 then&#10;          t = ((vD) = {128}1)&#10;          f = ((vD) = {128}0)&#10;          CR[24:27] = t || 0b0 || f || 0b0&#10;        end"/>
  3916.         <Mnemonic
  3917.            Form="vcmpequw vD,vA,vB"
  3918.            Notes="Vector compare equal-to unsigned word."/>
  3919.         <Mnemonic
  3920.            Form="vcmpequw. vD,vA,vB"
  3921.            Notes="Vector compare equal-to unsigned word and record."/>
  3922.     </Instruction>
  3923.     <Instruction>
  3924.         <Details
  3925.            Name="Vector Compare Greater-Than-or-Equal-to Floating Point"
  3926.            Description="Each single-precision floating-point word element in register vA is compared to the corresponding single-precision floating-point word element in register vB. The corresponding word element in register vD is set to all '1's if the element in register vA is greater than or equal to the element in register vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 is set as follows:&#10; * CR6 = all_greater_or_equal || 0b0 || none greater_or_equal || 0b0.&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding results will be 0x0000_0000."
  3927.            OtherRegs="Condition register (CR6):&#10;    Affected: Bits [0-3]    (if Rc ='1')"
  3928.            Pseudocode="         do i=0 to 127 by 32&#10;           if (vA)[i:i+31] &gt;=fp (vB)[i:i+31] then &#10;             (vD)[i:i+31] = 0xFFFF_FFFF&#10;           else &#10;             (vD)[i:i+31] = 0x0000_0000&#10;         end&#10;         if Rc=1 then&#10;           t = ((vD) = {128}1)&#10;           f = ((vD) = {128}0)&#10;           CR[24:27] = t || 0b0 || f || 0b0&#10;         end"/>
  3929.         <Mnemonic
  3930.            Form="vcmpgefp vD,vA,vB"
  3931.            Notes="Vector compare greater-than-or-equal-to floating point"/>
  3932.         <Mnemonic
  3933.            Form="vcmpgefp. vD,vA,vB"
  3934.            Notes="Vector compare greater-than-or-equal-to floating point and record."/>
  3935.     </Instruction>
  3936.     <Instruction>
  3937.         <Details
  3938.            Name="Vector Compare Greater-Than Floating-Point"
  3939.            Description="Each single-precision floating-point word element in register vA is compared to the corresponding single-precision floating-point word element in register vB. The corresponding word element in register vD is set to all '1's if the element in register vA is greater than the element in register vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 is set as follows:&#10; * CR6 = all_greater_than || 0b0 || none greater_than || 0b0.&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding results will be 0x0000_0000."
  3940.            OtherRegs="Condition register (CR6):&#10;   Affected: Bits [0-3]    (if Rc ='1')"
  3941.            Pseudocode="        do i=0 to 127 by 32&#10;          if (vA)[i:i+31] &gt;fp (vB)[i:i+31] then &#10;            (vD)[i:i+31] = 0xFFFF_FFFF&#10;          else &#10;            (vD)[i:i+31] = 0x0000_0000&#10;        end&#10;        if Rc=1 then&#10;          t = ((vD) = {128}1)&#10;          f = ((vD) = {128}0)&#10;          CR[24:27] = t || 0b0 || f || 0b0&#10;        end"/>
  3942.         <Mnemonic
  3943.            Form="vcmpgtfp vD,vA,vB"
  3944.            Notes="Vector compare greater-than floating-point."/>
  3945.         <Mnemonic
  3946.            Form="vcmpgtfp. vD,vA,vB"
  3947.            Notes="Vector compare greater-than floating-point and record."/>
  3948.     </Instruction>
  3949.     <Instruction>
  3950.         <Details
  3951.            Name="Vector Compare Greater-Than Signed Byte"
  3952.            Description="Each signed-integer byte element in register vA is compared to the corresponding signed-integer byte element in register vB. The corresponding element in vD is set to all '1's if the element in vA is greater than the element in vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 is set as follows:&#10; * CR6 = all_greater_than || 0b0 || none greater_than || 0b0.&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding results will be 0x0000_0000."
  3953.            OtherRegs="Condition register (CR6):&#10;    Affected: Bits [0-3]    (if Rc ='1')"
  3954.            Pseudocode="         do i=0 to 127 by 8&#10;           if (vA)[i:i+7] &gt;si (vB)[i:i+7] then &#10;             (vD)[i:i+7] = {8}1&#10;           else &#10;             (vD)[i:i+7] = {8}0&#10;         end&#10;         if Rc=1 then&#10;           t = ((vD) = {128}1)&#10;           f = ((vD) = {128}0)&#10;           CR[24:27] = t || 0b0 || f || 0b0&#10;         end"/>
  3955.         <Mnemonic
  3956.            Form="vcmpgtsb vD,vA,vB"
  3957.            Notes="Vector compare greater-than signed byte."/>
  3958.         <Mnemonic
  3959.            Form="vcmpgtsb. vD,vA,vB"
  3960.            Notes="Vector compare greater-than signed byte and record."/>
  3961.     </Instruction>
  3962.     <Instruction>
  3963.         <Details
  3964.            Name="Vector Compare Greater-Than Signed Halfword"
  3965.            Description="Each signed-integer halfword element in register vA is compared to the corresponding signed-integer half-word element in register vB. The corresponding halfword element in register vD is set to all '1's if the element in vA is greater than the element in vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 is set as follows:&#10; * CR6 = all_greater_than || 0b0 || none greater_than || 0b0.&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding results will be 0x0000_0000."
  3966.            OtherRegs="Condition register (CR6):&#10;   Affected: Bits [0-3]    (if Rc ='1')"
  3967.            Pseudocode="        do i=0 to 127 by 16&#10;          if (vA)[i:i+15] &gt;si (vB)[i:i+15] then &#10;            (vD)[i:i+15] = {16}1&#10;          else &#10;            (vD)[i:i+15] = {16}0&#10;        end&#10;        if Rc=1 then&#10;          t = ((vD) = {128}1)&#10;          f = ((vD) = {128}0)&#10;          CR[24:27] = t || 0b0 || f || 0b0&#10;        end"/>
  3968.         <Mnemonic
  3969.            Form="vcmpgtsh vD,vA,vB"
  3970.            Notes="Vector compare greater-than signed halfword."/>
  3971.         <Mnemonic
  3972.            Form="vcmpgtsh. vD,vA,vB"
  3973.            Notes="Vector compare greater-than signed halfword and record."/>
  3974.     </Instruction>
  3975.     <Instruction>
  3976.         <Details
  3977.            Name="Vector Compare Greater-Than Signed Word"
  3978.            Description="Each signed-integer word element in register vA is compared to the corresponding signed-integer word element in register vB. The corresponding word element in register vD is set to all '1's if the element in vA is greater than the element in vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 is set as follows:&#10; * CR6 = all_greater_than || 0b0 || none greater_than || 0b0.&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding results will be 0x0000_0000."
  3979.            OtherRegs="Condition register (CR6):&#10;    Affected: Bits [0-3]    (if Rc ='1')"
  3980.            Pseudocode="         do i=0 to 127 by 32&#10;         if (vA)[i:i+31] &gt;si (vB)[i:i+31]&#10;             then (vD)[i:i+31] = {32}1&#10;             else (vD)[i:i+31] = {32}0&#10;         end&#10;         if Rc=1 then do&#10;           t = ((vD) = {128}1)&#10;           f = ((vD) = {128}0)&#10;           CR[24:27] = t || 0b0 || f || 0b0&#10;         end"/>
  3981.         <Mnemonic
  3982.            Form="vcmpgtsw vD,vA,vB"
  3983.            Notes="Vector compare greater-than signed word"/>
  3984.         <Mnemonic
  3985.            Form="vcmpgtsw. vD,vA,vB"
  3986.            Notes="Vector compare greater-than signed word and record."/>
  3987.     </Instruction>
  3988.     <Instruction>
  3989.         <Details
  3990.            Name="Vector Compare Greater-Than Unsigned Byte"
  3991.            Description="Each unsigned-integer byte element in register vA is compared to the corresponding unsigned-integer byte element in register vB. The corresponding byte element in register vD is set to all '1's if the element in vA is greater than the element in vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 is set as follows:&#10; * CR6 = all_greater_than || 0b0 || none greater_than || 0b0.&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding results will be 0x0000_0000."
  3992.            OtherRegs="Condition register (CR6):&#10;   Affected: Bits [0-3]    (if Rc ='1')"
  3993.            Pseudocode="        do i=0 to 127 by 8&#10;          if (vA)[i:i+7] &gt;ui (vB)[i:i+7] then &#10;            (vD)[i:i+7] = {8}1&#10;          else &#10;            (vD)[i:i+7] = {8}0&#10;        end&#10;        if Rc=1 then&#10;          t = ((vD) = {128}1)&#10;          f = ((vD) = {128}0)&#10;          CR[24-27] = t || 0b0 || f || 0b0&#10;        end"/>
  3994.         <Mnemonic
  3995.            Form="vcmpgtub vD,vA,vB"
  3996.            Notes="Vector compare greater-than unsigned byte."/>
  3997.         <Mnemonic
  3998.            Form="vcmpgtub. vD,vA,vB"
  3999.            Notes="Vector compare greater-than unsigned byte and record."/>
  4000.     </Instruction>
  4001.     <Instruction>
  4002.         <Details
  4003.            Name="Vector Compare Greater-Than Unsigned Halfword"
  4004.            Description="Each unsigned-integer halfword element in register vA is compared to the corresponding unsigned-integer halfword element in register vB. The corresponding halfword element in register vD is set to all '1's if the element in vA is greater than the element in vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 is set as follows:&#10; * CR6 = all_greater_than || 0b0 || none greater_than || 0b0&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding results will be 0x0000_0000."
  4005.            OtherRegs="Condition register (CR6):&#10;    Affected: Bits [0-3]    (if Rc ='1')"
  4006.            Pseudocode="         do i=0 to 127 by 16&#10;           if (vA)[i:i+15] &gt;ui (vB)[i:i+15] then &#10;             (vD)[i:i+15] = {16}1&#10;           else &#10;             (vD)[i:i+15] = {16}0&#10;         end&#10;         if Rc=1 then&#10;           t = ((vD) = {128}1)&#10;           f = ((vD) = {128}0)&#10;           CR[24-27] = t || 0b0 || f || 0b0&#10;         end"/>
  4007.         <Mnemonic
  4008.            Form="vcmpgtuh vD,vA,vB"
  4009.            Notes="Vector compare greater-than unsigned halfword."/>
  4010.         <Mnemonic
  4011.            Form="vcmpgtuh. vD,vA,vB"
  4012.            Notes="Vector compare greater-than unsigned halfword and record."/>
  4013.     </Instruction>
  4014.     <Instruction>
  4015.         <Details
  4016.            Name="Vector Compare Greater-Than Unsigned Word"
  4017.            Description="Each unsigned-integer word element in register vA is compared to the corresponding unsigned-integer word element in register vB. The corresponding word element in register vD is set to all '1's if the element in vA is greater than the element in vB, and is cleared to all '0's otherwise.&#10;&#10;If Rc ='1', CR6 is set as follows:&#10; * CR6 = all_greater_than || 0b0 || none_greater_than || 0b0&#10;&#10;Note: If a vA or vB element is a NaN, the corresponding results will be 0x0000_0000."
  4018.            OtherRegs="Condition register (CR6):&#10;   Affected: Bits [0-3]    (if Rc ='1')"
  4019.            Pseudocode="        do i=0 to 127 by 32&#10;          if (vA)[i:i+31] &gt;ui (vB)[i:i+31] then &#10;            (vD)[i:i+31] = {32}1&#10;          else &#10;            (vD)[i:i+31] = {32}0&#10;        end&#10;        if Rc=1 then do&#10;          t = ((vD) = {128}1)&#10;          f = ((vD) = {128}0)&#10;          CR[24-27] = t || 0b0 || f || 0b0&#10;        end"/>
  4020.         <Mnemonic
  4021.            Form="vcmpgtuw vD,vA,vB"
  4022.            Notes="Vector compare greater-than unsigned word."/>
  4023.         <Mnemonic
  4024.            Form="vcmpgtuw. vD,vA,vB"
  4025.            Notes="Vector compare greater-than unsigned word and record."/>
  4026.     </Instruction>
  4027.     <Instruction>
  4028.         <Details
  4029.            Name="Vector Convert to Signed Fixed-Point Word Saturate"
  4030.            Description="Each single-precision word element in register vB is multiplied by 2^UIMM. The product is converted to a signed integer using the rounding mode, Round toward Zero. If the intermediate result is greater than (2^31-1) it satu- rates to (2^31-1); if it is less than -2^31 it saturates to -2^31. A signed-integer result is placed into the corresponding word element in register vD.&#10;&#10;Fixed-point integers used by the vector convert instructions can be interpreted as consisting of 32-UIMM integer bits followed by UIMM fraction bits. The vector convert to fixed-point word instructions support only the rounding mode, Round toward Zero. A single-precision number can be converted to a fixed-point integer using any of the other three rounding modes by executing the appropriate vector round to floating-point integer instruction before the vector convert to fixed-point word instruction."
  4031.            OtherRegs="Vector status and control register (VSCR):&#10;    Affected: SAT"
  4032.            Pseudocode="         do i=0 to 127 by 32&#10;           if (vB)[i+1:i+8]=255 | (vB)[i+1:i+8] + UIMM &lt;= 254 then&#10;             (vD)[i:i+31] = CnvtFP32ToSI32Sat((vB)[i:i+31] *fp 2^UIMM)&#10;           else&#10;             do&#10;               if (vB)[i]=0 then &#10;                 (vD)[i:i+31] = 0x7FFF_FFFF&#10;               else (vD)[i:i+31] = 0x8000_0000&#10;                 VSCRSAT = 1&#10;             end&#10;         end"/>
  4033.         <Mnemonic
  4034.            Form="vctsxs vD,vB,UIMM"
  4035.            Notes="Vector convert to signed fixed-point word saturate."/>
  4036.     </Instruction>
  4037.     <Instruction>
  4038.         <Details
  4039.            Name="Vector Convert to Unsigned Fixed-Point Word Saturate"
  4040.            Description="Each single-precision floating-point word element in vB is multiplied by 2UIM. The product is converted to an unsigned fixed-point integer using the rounding mode Round toward Zero. If the intermediate result is greater than (2^32-1) it saturates to (2^32-1) and if it is less than '0' it saturates to '0'. The unsigned-integer result is placed into the corresponding word element in register vD."
  4041.            OtherRegs="Vector status and control register (VSCR):&#10;   Affected: SAT"
  4042.            Pseudocode="         do i=0 to 127 by 32&#10;           if (vB)[i+1:i+8]=255 | (vB)[i+1:i+8] + UIMM &lt;= 254 then&#10;             (vD)[i:i+31] = CnvtFP32ToUI32Sat((vB)[i:i+31] *fp 2^UIMM)&#10;           else&#10;             do&#10;               if (vB)[i]=0 then&#10;                 (vD)[i:i+31] = 0xFFFF_FFFF&#10;               else &#10;                 (vD)[i:i+31] = 0x0000_0000&#10;                 VSCRSAT = 1&#10;             end&#10;         end"/>
  4043.         <Mnemonic
  4044.            Form="vctuxs vD,vB,UIMM"
  4045.            Notes="Vector convert to unsigned fixed-point word saturate."/>
  4046.     </Instruction>
  4047.     <Instruction>
  4048.         <Details
  4049.            Name="Vector Two Raised to the Exponent Estimate Floating Point"
  4050.            Description="The single-precision floating-point estimate of 2 raised to the power of each single-precision floating-point element in register vB is placed into the corresponding element in register vD.&#10;&#10;Operation with various special values of the element in vB is summarized below.&#10;Value: Result&#10;-INF: +0&#10;-0: +1&#10;+0: +1&#10;+INF: +INF&#10;NaN: QNaN&#10;&#10;If VSCR[NJ] ='1', every denormalized operand element is truncated to a '0' of the same sign before the operation is carried out, and each denormalized result element truncates to a '0' of the same sign."
  4051.            OtherRegs=""
  4052.            Pseudocode="         do i=0 to 127 by 32&#10;           x = (vB)[i:i+31]&#10;           (vD)[i:i+31] = 2^x&#10;         end"/>
  4053.         <Mnemonic
  4054.            Form="vexptefp vD,vB"
  4055.            Notes="Vector two raised to the exponent estimate floating point."/>
  4056.     </Instruction>
  4057.     <Instruction>
  4058.         <Details
  4059.            Name="Vector Log Two Estimate Floating Point"
  4060.            Description="The single-precision floating-point estimate of the base 2 logarithm of each single-precision floating-point element in register vB is placed into the corresponding element in register vD.&#10;&#10;Operation with various special values of the element in register vB is summarized below.&#10;Value: Result&#10;-INF: QNaN&#10;less than 0: QNaN&#10;+or-0: -INF&#10;+INF: +INF&#10;NaN: QNaN&#10;&#10;If VSCR[NJ] ='1', every denormalized operand element is truncated to a '0' of the same sign before the operation is carried out, and each denormalized result element truncates to a '0' of the same sign."
  4061.            OtherRegs=""
  4062.            Pseudocode="         do i=0 to 127 by 32&#10;           x = (vB)[i:i+31]&#10;           (vD)[i:i+31] = log2(x)&#10;         end"/>
  4063.         <Mnemonic
  4064.            Form="vlogefp vD,vB"
  4065.            Notes="Vector log two estimate floating point."/>
  4066.     </Instruction>
  4067.     <Instruction>
  4068.         <Details
  4069.            Name="Vector Multiply Add Floating Point"
  4070.            Description="Each single-precision floating-point word element in register vA is multiplied by the corresponding single-precision floating-point word element in register vC. The corresponding single-precision floating-point word element in register vB is added to the product. The result is rounded to the nearest single-precision floating-point number and placed into the corresponding word element in register vD.&#10;&#10;Note that a vector multiply floating-point instruction is not provided. The effect of such an instruction can be obtained by using vmaddfp with vB containing the value -0.0 (0x8000_0000) in each of its four single-precision floating-point word elements. (The value must be -0.0, not +0.0, in order to obtain the IEEE-conforming result of -0.0 when the result of the multiplication is -0.)&#10;&#10;If VSCR[NJ] ='1', every denormalized operand element is truncated to a '0' of the same sign before the operation is carried out, and each denormalized result element truncates to a '0' of the same sign."
  4071.            OtherRegs=""
  4072.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = RndToNearFP32(((vA)[i:i+31] *fp (vC)[i:i+31]) +fp (vB)[i:i+31])&#10;         end"/>
  4073.         <Mnemonic
  4074.            Form="vmaddfp vD,vA,vC,vB"
  4075.            Notes="Vector multiply add floating point."/>
  4076.     </Instruction>
  4077.     <Instruction>
  4078.         <Details
  4079.            Name="Vector Maximum Floating Point"
  4080.            Description="Each single-precision floating-point word element in register vA is compared to the corresponding single-precision floating-point word element in register vB. The larger of the two single-precision floating-point values is placed into the corresponding word element in register vD.&#10;&#10;The maximum of +0 and -0 is +0. The maximum of any value and a NaN is a QNaN."
  4081.            OtherRegs=""
  4082.            Pseudocode="        do i=0 to 127 by 32&#10;          if (vA)[i:i+31] &gt;=fp (vB)[i:i+31] then &#10;            (vD)[i:i+31] = (vA)[i:i+31]&#10;          else &#10;            (vD)[i:i+31] = (vB)[i:i+31]&#10;        end"/>
  4083.         <Mnemonic
  4084.            Form="vmaxfp vD,vA,vB"
  4085.            Notes="Vector maximum floating point."/>
  4086.     </Instruction>
  4087.     <Instruction>
  4088.         <Details
  4089.            Name="Vector Maximum Signed Byte"
  4090.            Description="Each signed-integer byte element in register vA is compared to the corresponding signed-integer byte element in register vB. The larger of the two signed-integer values is placed into the corresponding byte element in register vD."
  4091.            OtherRegs=""
  4092.            Pseudocode="         do i=0 to 127 by 8&#10;           if (vA)[i:i+7] &gt;=si (vB)[i:i+7] then &#10;             (vD)[i:i+7] = (vA)[i:i+7]&#10;           else &#10;             (vD)[i:i+7] = (vB)[i:i+7]&#10;         end"/>
  4093.         <Mnemonic
  4094.            Form="vmaxsb vD,vA,vB"
  4095.            Notes="Vector maximum signed byte."/>
  4096.     </Instruction>
  4097.     <Instruction>
  4098.         <Details
  4099.            Name="Vector Maximum Signed Halfword"
  4100.            Description="Each signed-integer halfword element in register vA is compared to the corresponding signed-integer half-word element in register vB. The larger of the two signed-integer values is placed into the corresponding half-word element in register vD."
  4101.            OtherRegs=""
  4102.            Pseudocode="        do i=0 to 127 by 16&#10;          if (vA)[i:i+15] &gt;=si (vB)[i:i+15] then &#10;            (vD)[i:i+15] = (vA)[i:i+15]&#10;          else &#10;            (vD)[i:i+15] = (vB)[i:i+15]&#10;        end"/>
  4103.         <Mnemonic
  4104.            Form="vmaxsh vD,vA,vB"
  4105.            Notes="Vector maximum signed halfword."/>
  4106.     </Instruction>
  4107.     <Instruction>
  4108.         <Details
  4109.            Name="Vector Maximum Signed Word"
  4110.            Description="Each signed-integer word element in register vA is compared to the corresponding signed-integer word element in register vB. The larger of the two signed-integer values is placed into the corresponding word element in register vD."
  4111.            OtherRegs=""
  4112.            Pseudocode="         do i=0 to 127 by 32&#10;           if (vA)[i:i+31] &gt;=si (vB)[i:i+31] then &#10;             (vD)[i:i+31] = (vA)[i:i+31]&#10;           else &#10;             (vD)[i:i+31] = (vB)[i:i+31]&#10;         end"/>
  4113.         <Mnemonic
  4114.            Form="vmaxsw vD,vA,vB"
  4115.            Notes="Vector maximum signed word."/>
  4116.     </Instruction>
  4117.     <Instruction>
  4118.         <Details
  4119.            Name="Vector Maximum Unsigned Byte"
  4120.            Description="Each unsigned-integer byte element in register vA is compared to the corresponding unsigned-integer byte element in register vB. The larger of the two unsigned-integer values is placed into the corresponding byte element in register vD."
  4121.            OtherRegs=""
  4122.            Pseudocode="        do i=0 to 127 by 8&#10;          if (vA)[i:i+7] &gt;=ui (vB)[i:i+7] then &#10;            (vD)[i:i+7] = (vA)[i:i+7]&#10;          else &#10;            (vD)[i:i+7] = (vB)[i:i+7]&#10;        end"/>
  4123.         <Mnemonic
  4124.            Form="vmaxub vD,vA,vB"
  4125.            Notes="Vector maximum unsigned byte."/>
  4126.     </Instruction>
  4127.     <Instruction>
  4128.         <Details
  4129.            Name="Vector Maximum Unsigned Halfword"
  4130.            Description="Each unsigned-integer halfword element in register vA is compared to the corresponding unsigned-integer halfword element in register vB. The larger of the two unsigned-integer values is placed into the corresponding halfword element in register vD."
  4131.            OtherRegs=""
  4132.            Pseudocode="         do i=0 to 127 by 16&#10;           if (vA)[i:i+15] &gt;=ui (vB)[i:i+15] then &#10;             (vD)[i:i+15] = (vA)[i:i+15]&#10;           else &#10;             (vD)[i:i+15] = (vB)[i:i+15]&#10;         end"/>
  4133.         <Mnemonic
  4134.            Form="vmaxuh vD,vA,vB"
  4135.            Notes="Vector maximum unsigned halfword."/>
  4136.     </Instruction>
  4137.     <Instruction>
  4138.         <Details
  4139.            Name="Vector Maximum Unsigned Word"
  4140.            Description="Each unsigned-integer word element in register vA is compared to the corresponding unsigned-integer word element in register vB. The larger of the two unsigned-integer values is placed into the corresponding word element in register vD."
  4141.            OtherRegs=""
  4142.            Pseudocode="        do i=0 to 127 by 32&#10;          if (vA)[i:i+31] &gt;=ui (vB)[i:i+31] then &#10;            (vD)[i:i+31] = (vA)[i:i+31]&#10;          else &#10;            (vD)[i:i+31] = (vB)[i:i+31]&#10;        end"/>
  4143.         <Mnemonic
  4144.            Form="vmaxuw vD,vA,vB"
  4145.            Notes="Vector maximum unsigned word."/>
  4146.     </Instruction>
  4147.     <Instruction>
  4148.         <Details
  4149.            Name="Vector Multiply High and Add Signed Halfword Saturate"
  4150.            Description="Each signed-integer halfword element in register vA is multiplied by the corresponding signed-integer half-word element in register vB, producing a 32-bit signed-integer product. The corresponding signed-integer halfword element in register vC is sign-extended to 17 bits and added to bits [0:16] of the product. If the intermediate result is greater than 2^15-1, it saturates to 2^15-1. If the intermediate result is less than -2^15, it saturates to -2^15. If saturation occurs, the SAT bit is set. The signed-integer result is placed into the corresponding half-word element in register vD."
  4151.            OtherRegs="Vector status and control register (VSCR):&#10;    Affected: SAT"
  4152.            Pseudocode="         do i=0 to 127 by 16&#10;           prod[0:31] = (vA)[i:i+15] *si (vB)[i:i+15]&#10;           temp[0:16] = prod[0:16] +int SignExtend((vC)[i:i+15],17)&#10;           (vD)[i:i+15] = SItoSIsat(temp[0:16],16)&#10;         end"/>
  4153.         <Mnemonic
  4154.            Form="vmhaddshs vD,vA,vB,vC"
  4155.            Notes="Vector multiply high and add signed halfword saturate."/>
  4156.     </Instruction>
  4157.     <Instruction>
  4158.         <Details
  4159.            Name="Vector Multiply High Round and Add Signed Halfword Saturate"
  4160.            Description="Each signed-integer halfword element in register vA is multiplied by the corresponding signed-integer half-word element in register vB, producing a 32-bit signed-integer product. The product is rounded by adding the value 0x0000_4000. The corresponding signed-integer halfword element in register vC is sign-extended to 17 bits and added to bits [0:16] of the rounded product. If the intermediate result is greater than (2^15-1), it saturates to (2^15-1). If the intermediate result is less than (-2^15), it saturates to (-2^15). If saturation occurs, the SAT bit is set. The signed-integer result is placed into the corresponding halfword element of register vD."
  4161.            OtherRegs=""
  4162.            Pseudocode="        do i=0 to 127 by 16&#10;          prod[0:31] = (vA)[i:i+15] *si (vB)[i:i+15]&#10;          prod[0:31] = prod[0:31] +int 0x0000_4000&#10;          temp[0:16] = prod[0:16] +int SignExtend((vC)[i:i+15],17)&#10;          (vD)[i:i+15] = SItoSIsat(temp[0:16],16)&#10;        end"/>
  4163.         <Mnemonic
  4164.            Form="vmhraddshs vD,vA,vB,vC"
  4165.            Notes="Vector multiply high round and add signed halfword saturate."/>
  4166.     </Instruction>
  4167.     <Instruction>
  4168.         <Details
  4169.            Name="Vector Minimum Floating"
  4170.            Description="Each single-precision floating-point word element in register vA is compared to the corresponding single-precision floating-point word element in register vB. The smaller of the two single-precision floating-point values is placed into the corresponding word element of register vD.&#10;&#10;The minimum of + 0.0 and - 0.0 is - 0.0. The minimum of any value and a NaN is a QNaN.&#10;&#10;If VSCR[NJ] ='1', every denormalized operand element is truncated to '0' before the comparison is made."
  4171.            OtherRegs=""
  4172.            Pseudocode="         do i=0 to 127 by 32&#10;           if (vA)[i:i+31] &lt;fp (vB)[i:i+31] then &#10;             (vD)[i:i+31] = (vA)[i:i+31]&#10;           else &#10;             (vD)[i:i+31] = (vB)[i:i+31]&#10;         end"/>
  4173.         <Mnemonic
  4174.            Form="vminfp vD,vA,vB"
  4175.            Notes="Vector minimum floating point."/>
  4176.     </Instruction>
  4177.     <Instruction>
  4178.         <Details
  4179.            Name="Vector Minimum Signed Byte"
  4180.            Description="Each signed-integer byte element in register vA is compared to the corresponding signed-integer byte element in register vB. The larger of the two signed-integer values is placed into the corresponding byte element in register vD."
  4181.            OtherRegs=""
  4182.            Pseudocode="        do i=0 to 127 by 8&#10;          if (vA)[i:i+7] &lt;si (vB)[i:i+7] then &#10;            (vD)[i:i+7] = (vA)[i:i+7]&#10;          else &#10;            (vD)[i:i+7] = (vB)[i:i+7]&#10;        end"/>
  4183.         <Mnemonic
  4184.            Form="vminsb vD,vA,vB"
  4185.            Notes="Vector minimum signed byte."/>
  4186.     </Instruction>
  4187.     <Instruction>
  4188.         <Details
  4189.            Name="Vector Minimum Signed Halfword"
  4190.            Description="Each signed-integer halfword element in register vA is compared to the corresponding signed-integer half-word element in register vB. The larger of the two signed-integer values is placed into the corresponding half-word element in register vD."
  4191.            OtherRegs=""
  4192.            Pseudocode="         do i=0 to 127 by 16&#10;           if (vA)[i:i+15] &lt;si (vB)[i:i+15] then &#10;             (vD)[i:i+15] = (vA)[i:i+15]&#10;           else &#10;             (vD)[i:i+15] = (vB)[i:i+15]&#10;         end"/>
  4193.         <Mnemonic
  4194.            Form="vminsh vD,vA,vB"
  4195.            Notes="Vector minimum signed halfword."/>
  4196.     </Instruction>
  4197.     <Instruction>
  4198.         <Details
  4199.            Name="Vector Minimum Signed Word"
  4200.            Description="Each signed-integer word element in register vA is compared to the corresponding signed-integer word element in register vB. The larger of the two signed-integer values is placed into the corresponding word element in register vD."
  4201.            OtherRegs=""
  4202.            Pseudocode="        do i=0 to 127 by 32&#10;          if (vA)[i:i+31] &lt;si (vB)[i:i+31] then &#10;            (vD)[i:i+31] = (vA)[i:i+31]&#10;          else &#10;            (vD)[i:i+31] = (vB)[i:i+31]&#10;        end"/>
  4203.         <Mnemonic
  4204.            Form="vminsw vD,vA,vB"
  4205.            Notes="Vector minimum signed word."/>
  4206.     </Instruction>
  4207.     <Instruction>
  4208.         <Details
  4209.            Name="Vector Minimum Unsigned Byte"
  4210.            Description="Each unsigned-integer byte element in register vA is compared to the corresponding unsigned-integer byte element in register vB. The larger of the two unsigned-integer values is placed into the corresponding byte element in register vD."
  4211.            OtherRegs=""
  4212.            Pseudocode="         do i=0 to 127 by 8&#10;           if (vA)[i:i+7] &lt;ui (vB)[i:i+7] then &#10;             (vD)[i:i+7] = (vA)[i:i+7]&#10;           else &#10;             (vD)[i:i+7] = (vB)[i:i+7]&#10;         end"/>
  4213.         <Mnemonic
  4214.            Form="vminub vD,vA,vB"
  4215.            Notes="Vector minimum unsigned byte."/>
  4216.     </Instruction>
  4217.     <Instruction>
  4218.         <Details
  4219.            Name="Vector Minimum Unsigned Halfword"
  4220.            Description="Each unsigned-integer halfword element in register vA is compared to the corresponding unsigned-integer halfword element in register vB. The larger of the two unsigned-integer values is placed into the corre- sponding halfword element in register vD."
  4221.            OtherRegs=""
  4222.            Pseudocode="        do i=0 to 127 by 16&#10;          if (vA)[i:i+15] &lt;ui (vB)[i:i+15] then &#10;            (vD)[i:i+15] = (vA)[i:i+15]&#10;          else &#10;            (vD)[i:i+15] = (vB)[i:i+15]&#10;        end"/>
  4223.         <Mnemonic
  4224.            Form="vminuh vD,vA,vB"
  4225.            Notes="Vector minimum unsigned halfword."/>
  4226.     </Instruction>
  4227.     <Instruction>
  4228.         <Details
  4229.            Name="Vector Minimum Unsigned Word"
  4230.            Description="Each unsigned-integer word element in register vA is compared to the corresponding unsigned-integer word element in register vB. The larger of the two unsigned-integer values is placed into the corresponding word element in register vD."
  4231.            OtherRegs=""
  4232.            Pseudocode="         do i=0 to 127 by 32&#10;           if (vA)[i:i+31] &lt;ui (vB)[i:i+31] then &#10;             (vD)[i:i+31] = (vA)[i:i+31]&#10;           else &#10;             (vD)[i:i+31] = (vB)[i:i+31]&#10;         end"/>
  4233.         <Mnemonic
  4234.            Form="vminuw vD,vA,vB"
  4235.            Notes="Vector minimum unsigned word."/>
  4236.     </Instruction>
  4237.     <Instruction>
  4238.         <Details
  4239.            Name="Vector Multiply Low and Add Unsigned Halfword Modulo"
  4240.            Description="Each integer halfword element in register vA is multiplied by the corresponding integer halfword element in register vB, producing a 32-bit integer product. The product is added to the corresponding integer halfword element in register vC. The integer result is placed into the corresponding halfword element in register vD.&#10;&#10;Note: vmladduhm can be used for unsigned or signed integers."
  4241.            OtherRegs=""
  4242.            Pseudocode="        do i=0 to 127 by 16&#10;          prod[0:31] = (vA)[i:i+15] *ui (vB)[i:i+15]&#10;          (vD)[i:i+15] = prod[0:31] +int (vC)[i:i+15]&#10;        end"/>
  4243.         <Mnemonic
  4244.            Form="vmladduhm vD,vA,vB,vC"
  4245.            Notes="Vector multiply low and add unsigned halfword modulo."/>
  4246.     </Instruction>
  4247.     <Instruction>
  4248.         <Details
  4249.            Name="Vector Merge High Byte"
  4250.            Description="The byte elements in the high-order half of register vA are placed, in the same order, into the even-numbered byte elements of register vD. The byte elements in the high-order half of register vB are placed, in the same order, into the odd-numbered byte elements of register vD."
  4251.            OtherRegs=""
  4252.            Pseudocode="         do i=0 to 63 by 8&#10;           (vD)[i*2:(i*2)+15] = (vA)[i:i+7] || (vB)[i:i+7]&#10;         end"/>
  4253.         <Mnemonic
  4254.            Form="vmrghb vD,vA,vB"
  4255.            Notes="Vector merge high byte."/>
  4256.     </Instruction>
  4257.     <Instruction>
  4258.         <Details
  4259.            Name="Vector Merge High Halfword"
  4260.            Description="The halfword elements in the high-order half of register vA are placed, in the same order, into the even-numbered halfword elements of register vD. The halfword elements in the high-order half of register vB are placed, in the same order, into the odd-numbered halfword elements of register vD."
  4261.            OtherRegs=""
  4262.            Pseudocode="        do i=0 to 63 by 16&#10;          (vD)[i*2:(i*2)+31] = (vA)[i:i+15] || (vB)[i:i+15]&#10;        end"/>
  4263.         <Mnemonic
  4264.            Form="vmrghh vD,vA,vB"
  4265.            Notes="Vector merge high halfword."/>
  4266.     </Instruction>
  4267.     <Instruction>
  4268.         <Details
  4269.            Name="Vector Merge High Word"
  4270.            Description="The word elements in the high-order half of register vA are placed, in the same order, into the even-numbered word elements of register vD. The word elements in the high-order half of register vB are placed, in the same order, into the odd-numbered word elements of register vD."
  4271.            OtherRegs=""
  4272.            Pseudocode="         do i=0 to 63 by 32&#10;           (vD)[i*2:(i*2)+63] = (vA)[i:i+31] || (vB)[i:i+31]&#10;         end"/>
  4273.         <Mnemonic
  4274.            Form="vmrghw vD,vA,vB"
  4275.            Notes="Vector merge high word."/>
  4276.     </Instruction>
  4277.     <Instruction>
  4278.         <Details
  4279.            Name="Vector Merge Low Byte"
  4280.            Description="The byte elements in the low-order half of register vA are placed, in the same order, into the even-numbered byte elements of register vD. The byte elements in the low-order half of register vB are placed, in the same order, into the odd-numbered elements of register vD."
  4281.            OtherRegs=""
  4282.            Pseudocode="        do i=0 to 63 by 8&#10;          (vD)[i*2:(i*2)+15] = (vA)[i+64:i+71] || (vB)[i+64:i+71]&#10;        end"/>
  4283.         <Mnemonic
  4284.            Form="vmrglb vD,vA,vB"
  4285.            Notes="Vector merge low byte."/>
  4286.     </Instruction>
  4287.     <Instruction>
  4288.         <Details
  4289.            Name="Vector Merge Low Halfword"
  4290.            Description="The halfword elements in the low-order half of register vA are placed, in the same order, into the even-numbered halfword elements of register vD. The halfword elements in the low-order half of register vB are placed, in the same order, into the odd-numbered halfword elements of register vD."
  4291.            OtherRegs=""
  4292.            Pseudocode="         do i=0 to 63 by 16&#10;           (vD)[i*2:(i*2)+31] = (vA)[i+64:i+79] || (vB)[i+64:i+79]&#10;         end"/>
  4293.         <Mnemonic
  4294.            Form="vmrglh vD,vA,vB"
  4295.            Notes="Vector merge low halfword."/>
  4296.     </Instruction>
  4297.     <Instruction>
  4298.         <Details
  4299.            Name="Vector Merge Low Word"
  4300.            Description="The word elements in the low-order half of register vA are placed, in the same order, into the even-numbered word elements of register vD. The word elements in the low-order half of register vB are placed, in the same order, into the odd-numbered word elements of register vD."
  4301.            OtherRegs=""
  4302.            Pseudocode="        do i=0 to 63 by 32&#10;          (vD)[i*2:(i*2)+63] = (vA)[i+64:i+95] || (vB)[i+64:i+95]&#10;        end"/>
  4303.         <Mnemonic
  4304.            Form="vmrglw vD,vA,vB"
  4305.            Notes="Vector merge low word."/>
  4306.     </Instruction>
  4307.     <Instruction>
  4308.         <Details
  4309.            Name="Vector Multiply Sum Mixed-Sign Byte Modulo"
  4310.            Description="For each word element in register vC the following operations are performed in the order shown.&#10; * Each of the four signed-integer byte elements contained in the corresponding word element of register vA is multiplied by the corresponding unsigned-integer byte element in register vB, producing a signed-integer 16-bit product.&#10; * The signed-integer modulo sum of these four products is added to the signed-integer word element in register vC.&#10; * The signed-integer result is placed into the corresponding word element of register vD."
  4311.            OtherRegs=""
  4312.            Pseudocode="         do i=0 to 127 by 32&#10;           temp[0:31] = (vC)[i:i+31]&#10;           do j=0 to 31 by 8&#10;             prod[0:15] = (vA)[i+j:i+j+7] *sui (vB)[i+j:i+j+7]&#10;             temp[0:31] = temp[0:31] +int SignExtend(prod[0:15],32)&#10;           end&#10;           (vD)[i:i+31] = temp[0:31]&#10;         end"/>
  4313.         <Mnemonic
  4314.            Form="vmsummbm vD,vA,vB,vC"
  4315.            Notes="Vector multiply sum mixed-sign byte modulo."/>
  4316.     </Instruction>
  4317.     <Instruction>
  4318.         <Details
  4319.            Name="Vector Multiply Sum Signed Halfword Modulo"
  4320.            Description="For each word element in register vC the following operations are performed in the order shown:&#10; * Each of the two signed-integer halfword elements contained in the corresponding word element of register vA is multiplied by the corresponding signed-integer halfword element in register vB, producing a signed-integer 32-bit product.&#10; * The signed-integer modulo sum of these two products is added to the signed-integer word element in register vC.&#10; * The signed-integer result is placed into the corresponding word element of register vD."
  4321.            OtherRegs=""
  4322.            Pseudocode="        do i=0 to 127 by 32&#10;          temp[0:31] = (vC)[i:i+31]&#10;          do j=0 to 31 by 16&#10;            prod[0:31] = (vA)[i+j:i+j+15] *si (vB)[i+j:i+j+15]&#10;            temp[0:31] = temp[0:31] +int prod[0:31]&#10;          end&#10;          (vD)[i:i+31] = temp[0:31]&#10;        end"/>
  4323.         <Mnemonic
  4324.            Form="vmsumshm vD,vA,vB,vC"
  4325.            Notes="Vector multiply sum signed halfword modulo."/>
  4326.     </Instruction>
  4327.     <Instruction>
  4328.         <Details
  4329.            Name="Vector Multiply Sum Signed Halfword Saturate"
  4330.            Description="For each word element in register vC the following operations are performed in the order shown:&#10; * Each of the two signed-integer halfword elements in the corresponding word element of register vA is multiplied by the corresponding signed-integer halfword element in register vB, producing a signed-integer 32-bit product.&#10; * The signed-integer sum of these two products is added to the signed-integer word element in register vC.&#10; * If this intermediate result is greater than (2^31-1) it saturates to (2^31-1) and if it is less than (-2^31) it saturates to (-2^31).&#10; * The signed-integer result is placed into the corresponding word element of register vD."
  4331.            OtherRegs="SAT"
  4332.            Pseudocode="         do i=0 to 127 by 32&#10;           temp[0:33] = SignExtend((vC)[i:i+31],34)&#10;           do j=0 to 31 by 16&#10;             prod[0:31] = (vA)[i+j:i+j+15] *si (vB)[i+j:i+j+15]&#10;             temp[0:33] = temp[0:33] +int SignExtend(prod[0:31],34)&#10;           end&#10;           (vD)[i:i+31] = SItoSIsat(temp[0:33],32)&#10;         end"/>
  4333.         <Mnemonic
  4334.            Form="vmsumshs vD,vA,vB,vC"
  4335.            Notes="Vector multiply sum signed halfword saturate."/>
  4336.     </Instruction>
  4337.     <Instruction>
  4338.         <Details
  4339.            Name="Vector Multiply Sum Unsigned Byte Modulo"
  4340.            Description="For each word element in vC the following operations are performed in the order shown:&#10; * Each of the four unsigned-integer byte elements contained in the corresponding word element of register vA is multiplied by the corresponding unsigned-integer byte element in register vB, producing an unsigned-integer 16-bit product.&#10; * The unsigned-integer modulo sum of these four products is added to the unsigned-integer word element in register vC.&#10; * The unsigned-integer result is placed into the corresponding word element of register vD."
  4341.            OtherRegs=""
  4342.            Pseudocode="        do i=0 to 127 by 32&#10;          temp[0:32] = (vC)[i:i+31]&#10;          do j=0 to 31 by 8&#10;            prod[0:15] = (vA)[i+j:i+j+7] *ui (vB)[i+j:i+j+7]&#10;            temp[0:32] = temp[0:32] +int ZeroExtend(prod[0:15],32)&#10;          end&#10;          (vD)[i:i+31] = temp[0:31]&#10;        end"/>
  4343.         <Mnemonic
  4344.            Form="vmsumubm vD,vA,vB,vC"
  4345.            Notes="Vector multiply sum unsigned byte modulo."/>
  4346.     </Instruction>
  4347.     <Instruction>
  4348.         <Details
  4349.            Name="Vector Multiply Sum Unsigned Halfword Modulo"
  4350.            Description="For each word element in vC the following operations are performed in the order shown:&#10; * Each of the two unsigned-integer halfword elements contained in the corresponding word element of register vA is multiplied by the corresponding unsigned-integer halfword element in register vB, producing a unsigned-integer 32-bit product.&#10; * The unsigned-integer sum of these two products is added to the unsigned-integer word element in register vC.&#10; * The unsigned-integer result is placed into the corresponding word element of register vD."
  4351.            OtherRegs=""
  4352.            Pseudocode="         do i=0 to 127 by 32&#10;           temp[0:33] = (vC)[i:i+31]&#10;           do j=0 to 31 by 16&#10;             prod[0:31] = (vA)[i+j:i+j+15] *ui (vB)[i+j:i+j+15]&#10;             temp[0:33] = temp[0:33] +int prod[0:31]&#10;           end&#10;           (vD)[i:i+31] = temp[2:33]&#10;         end"/>
  4353.         <Mnemonic
  4354.            Form="vmsumuhm vD,vA,vB,vC"
  4355.            Notes="Vector multiply sum unsigned halfword modulo"/>
  4356.     </Instruction>
  4357.     <Instruction>
  4358.         <Details
  4359.            Name="Vector Multiply Sum Unsigned Halfword Saturate"
  4360.            Description="* Each of the two unsigned-integer halfword elements contained in the corresponding word element of register vA is multiplied by the corresponding unsigned-integer halfword element in register vB, producing an unsigned-integer 32-bit product.&#10; * The sum of the two 32-bit unsigned-integer products is added to the unsigned-integer word element in register vC.&#10; * If the intermediate result is greater than 2^32 - 1, it saturates to 2^32 - 1. If the intermediate result is less than '0', it saturates to '0'. If saturation occurs, the SAT bit is set.&#10; * The unsigned-integer result is placed into the corresponding word element of register vD."
  4361.            OtherRegs="SAT"
  4362.            Pseudocode="        do i=0 to 127 by 32&#10;          temp[0:33] = ZeroExtend((vC)[i:i+31],34)&#10;          do j=0 to 31 by 16&#10;            prod[0:31] = (vA)[i+j:i+j+15] *ui (vB)[i+j:i+j+15]&#10;            temp[0:33] = temp[0:33] +int ZeroExtend(prod[0:31],34)&#10;          end&#10;          (vD)[i:i+31] = UItoUIsat(temp[0:33],32)&#10;        end&#10;        "/>
  4363.         <Mnemonic
  4364.            Form="vmsumuhs vD,vA,vB,vC"
  4365.            Notes="Vector multiply sum unsigned halfword saturate."/>
  4366.     </Instruction>
  4367.     <Instruction>
  4368.         <Details
  4369.            Name="Vector Multiply Even Signed Byte"
  4370.            Description="Each even-numbered signed-integer byte element in register vA is multiplied by the corresponding signed-integer byte element in register vB. The eight 16-bit signed-integer products are placed, in the same order, into the eight halfwords of register vD."
  4371.            OtherRegs=""
  4372.            Pseudocode="         do i=0 to 127 by 16  &#10;           prod[0:15] = (vA)[i:i+7] *si (vB)[i:i+7]&#10;           (vD)[i:i+15] = prod[0:15]&#10;         end"/>
  4373.         <Mnemonic
  4374.            Form="vmulesb vD,vA,vB"
  4375.            Notes="Vector multiply even signed byte."/>
  4376.     </Instruction>
  4377.     <Instruction>
  4378.         <Details
  4379.            Name="Vector Multiply Even Signed Halfword"
  4380.            Description="Each even-numbered signed-integer halfword element in register vA is multiplied by the corresponding signed-integer halfword element in register vB. The four 32-bit signed-integer products are placed, in the same order, into the four word elements of register vD."
  4381.            OtherRegs=""
  4382.            Pseudocode="        do i=0 to 127 by 32&#10;          prod[0:31] = (vA)[i:i+15] *si (vB)[i:i+15]&#10;          (vD)[i:i+31] = prod[0:31]&#10;        end"/>
  4383.         <Mnemonic
  4384.            Form="vmulesh vD,vA,vB"
  4385.            Notes="Vector multiply even signed halfword."/>
  4386.     </Instruction>
  4387.     <Instruction>
  4388.         <Details
  4389.            Name="Vector Multiply Even Unsigned Byte"
  4390.            Description="Each even-numbered unsigned-integer byte element in register vA is multiplied by the corresponding unsigned-integer byte element in register vB. The eight 16-bit unsigned-integer products are placed, in the same order, into the eight halfword elements of register vD."
  4391.            OtherRegs=""
  4392.            Pseudocode="         do i=0 to 127 by 16&#10;           prod[0:15] = (vA)[i:i+7] *ui (vB)[i:i+7]&#10;           (vD)[i:i+15] = prod[0:15]&#10;         end"/>
  4393.         <Mnemonic
  4394.            Form="vmuleub vD,vA,vB"
  4395.            Notes="Vector multiply even unsigned byte."/>
  4396.     </Instruction>
  4397.     <Instruction>
  4398.         <Details
  4399.            Name="Vector Multiply Even Unsigned Halfword"
  4400.            Description="Each even-numbered unsigned-integer halfword element in register vA is multiplied by the corresponding unsigned-integer halfword element in register vB. The four 32-bit unsigned-integer products are placed, in the same order, into the four word elements of register vD."
  4401.            OtherRegs=""
  4402.            Pseudocode="        do i=0 to 127 by 32&#10;          prod[0:31] = (vA)[i:i+15] *ui (vB)[i:i+15]&#10;          (vD)[i:i+31] = prod[0:31]&#10;        end"/>
  4403.         <Mnemonic
  4404.            Form="vmuleuh vD,vA,vB"
  4405.            Notes="Vector multiply even unsigned halfword."/>
  4406.     </Instruction>
  4407.     <Instruction>
  4408.         <Details
  4409.            Name="Vector Multiply Odd Signed Byte"
  4410.            Description="Each odd-numbered signed-integer byte element in register vA is multiplied by the corresponding signed-integer byte element in register vB. The eight 16-bit signed-integer products are placed, in the same order, into the eight halfword elements in register vD."
  4411.            OtherRegs=""
  4412.            Pseudocode="         do i=0 to 127 by 16&#10;           prod[0:15] = (vA)[i+8:i+15] *si (vB)[i+8:i+15]&#10;           (vD)[i:i+15] = prod[0:15]&#10;         end"/>
  4413.         <Mnemonic
  4414.            Form="vmulosb vD,vA,vB"
  4415.            Notes="Vector multiply odd signed byte."/>
  4416.     </Instruction>
  4417.     <Instruction>
  4418.         <Details
  4419.            Name="Vector Multiply Odd Signed Halfword"
  4420.            Description="Each odd-numbered signed-integer halfword element in register vA is multiplied by the corresponding signed-integer halfword element in register vB. The four 32-bit signed-integer products are placed, in the same order, into the four word elements in register vD."
  4421.            OtherRegs=""
  4422.            Pseudocode="        do i=0 to 127 by 32&#10;          prod[0:31] = (vA)[i+16:i+31] *si (vB)[i+16:i+31]&#10;          (vD)[i:i+31] = prod[0:31]&#10;        end"/>
  4423.         <Mnemonic
  4424.            Form="vmulosh vD,vA,vB"
  4425.            Notes="Vector multiply odd signed halfword."/>
  4426.     </Instruction>
  4427.     <Instruction>
  4428.         <Details
  4429.            Name="Vector Multiply Odd Unsigned Byte"
  4430.            Description="Each odd-numbered unsigned-integer byte element in register vA is multiplied by the corresponding unsigned-integer byte element in register vB. The eight 16-bit unsigned-integer products are placed, in the same order, into the eight halfword elements in register vD."
  4431.            OtherRegs=""
  4432.            Pseudocode="         do i=0 to 127 by 8&#10;           prod[0:15] = (vA)[i+8:i+15] *ui (vB)[i+8:i+15]&#10;           (vD)[i:i+15] = prod[0:15]&#10;         end"/>
  4433.         <Mnemonic
  4434.            Form="vmuloub vD,vA,vB"
  4435.            Notes="Vector multiply odd unsigned byte."/>
  4436.     </Instruction>
  4437.     <Instruction>
  4438.         <Details
  4439.            Name="Vector Multiply Odd Unsigned Halfword"
  4440.            Description="Each odd-numbered unsigned-integer halfword element in register vA is multiplied by the corresponding unsigned-integer halfword element in register vB. The four 32-bit unsigned-integer products are placed, in the same order, into the four word elements in register vD."
  4441.            OtherRegs=""
  4442.            Pseudocode="        do i=0 to 127 by 16&#10;          prod[0:31] = (vA)[i+16:i+31] *ui (vB)[i+16:i+31]&#10;          (vD)[i:i+31] = prod[0:31]&#10;        end"/>
  4443.         <Mnemonic
  4444.            Form="vmulouh vD,vA,vB"
  4445.            Notes="Vector multiply odd unsigned halfword."/>
  4446.     </Instruction>
  4447.     <Instruction>
  4448.         <Details
  4449.            Name="Vector Negative Multiply-Subtract Floating Point"
  4450.            Description="Each single-precision floating-point word element in register vA is multiplied by the corresponding single-precision floating-point word element in register vC. The corresponding single-precision floating-point word element in register vB is subtracted from the product. The sign of the difference is inverted. The result is rounded to the nearest single-precision floating-point number and placed into the corresponding word element in register vD.&#10;&#10;Note: Only one rounding occurs in this operation. Also note that a QNaN result is not negated."
  4451.            OtherRegs=""
  4452.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = -RndToNearFP32(((vA)[i:i+31] *fp (vC)[i:i+31]) -fp (vB)[i:i+31])&#10;         end"/>
  4453.         <Mnemonic
  4454.            Form="vnmsubfp vD,vA,vC,vB"
  4455.            Notes="Vector negative multiply-subtract floating point."/>
  4456.     </Instruction>
  4457.     <Instruction>
  4458.         <Details
  4459.            Name="Vector Logical NOR"
  4460.            Description="The contents of vA are bitwise ORed with the contents of register vB and the complemented result is placed into register vD."
  4461.            OtherRegs=""
  4462.            Pseudocode=""/>
  4463.         <Mnemonic
  4464.            Form="vnor vD,vA,vB"
  4465.            Notes="Vector logical NOR."/>
  4466.     </Instruction>
  4467.     <Instruction>
  4468.         <Details
  4469.            Name="Vector Logical OR"
  4470.            Description="The contents of register vA are ORed with the contents of register vB and the result is placed into register vD."
  4471.            OtherRegs=""
  4472.            Pseudocode=""/>
  4473.         <Mnemonic
  4474.            Form="vor vD,vA,vB"
  4475.            Notes="Vector logical OR."/>
  4476.     </Instruction>
  4477.     <Instruction>
  4478.         <Details
  4479.            Name="Vector Permute"
  4480.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB. For each integer i in the range 0-15, the contents of the byte element in the source vector specified in bits [3-7] of byte element i in vC are placed into byte element i of register vD."
  4481.            OtherRegs=""
  4482.            Pseudocode="        temp[0:255] = (vA) || (vB)&#10;        do i=0 to 127 by 8&#10;          b = (vC)[i+3:i+7] || 0b000&#10;          (vD)[i:i+7] = temp[b:b+7]&#10;        end"/>
  4483.         <Mnemonic
  4484.            Form="vperm vD,vA,vB,vC"
  4485.            Notes="Vector permute."/>
  4486.     </Instruction>
  4487.     <Instruction>
  4488.         <Details
  4489.            Name="Vector Pack"
  4490.            Description="The source vector is the concatenation of the contents of register vA followed by the contents of register vB.  Each word element in the source vector is packed to produce a 16-bit value as described below and placed into the corresponding halfword element of vD. A word is packed to 16 bits by concatenating, in order, the following bits.&#10; * bit [7] of the first byte (bit [7] of the word)&#10; * bits [0-4] of the second byte (bits [8-12] of the word)&#10; * bits [0-4] of the third byte (bits [16-20] of the word)&#10; * bits [0-4] of the fourth byte (bits [24-28] of the word)&#10;&#10;Programming note: Each source word can be considered to be a 32-bit pixel consisting of four 8-bit channels. Each target halfword can be considered to be a 16-bit pixel consisting of one 1-bit channel and three 5-bit channels. A channel can be used to specify the intensity of a particular color, such as red, green, or blue, or to provide other information needed by the application."
  4491.            OtherRegs=""
  4492.            Pseudocode="         do i=0 to 63 by 16&#10;           (vD)[i]         = (vA)[i*2+7]&#10;           (vD)[i+1:i+5]   = (vA)[(i*2)+8:(i*2)+12]&#10;           (vD)[i+6:i+10]  = (vA)[(i*2)+16:(i*2)+20]&#10;           (vD)[i+11:i+15] = (vA)[(i*2)+24:(i*2)+28]&#10;           (vD)[i+64]      = (vB)[(i*2)+7]&#10;           (vD)[i+65:i+69] = (vB)[(i*2)+8:(i*2)+12]&#10;           (vD)[i+70:i+74] = (vB)[(i*2)+16:(i*2)+20]&#10;           (vD)[i+75:i+79] = (vB)[(i*2)+24:(i*2)+28]&#10;         end"/>
  4493.         <Mnemonic
  4494.            Form="vpkpx vD,vA,vB"
  4495.            Notes="Vector pack pixel32."/>
  4496.     </Instruction>
  4497.     <Instruction>
  4498.         <Details
  4499.            Name="Vector Pack Signed Halfword Signed Saturate"
  4500.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB.&#10;&#10;Each signed integer halfword element in the source vector is converted to an 8-bit signed integer. If the value of the element is greater than (2^7 - 1) it saturates to (2^7 - 1) and if the value is less than (-2^7) it saturates to (-2^7). If saturation occurs, the SAT bit is set. The result is placed into the corresponding byte element of register vD."
  4501.            OtherRegs="SAT"
  4502.            Pseudocode="        do i=0 to 63 by 8&#10;          (vD)[i:i+7]     = SItoSIsat((vA)[i*2:(i*2)+15],8)&#10;          (vD)[i+64:i+71] = SItoSIsat((vB)[i*2:(i*2)+15],8)&#10;        end"/>
  4503.         <Mnemonic
  4504.            Form="vpkshss vD,vA,vB"
  4505.            Notes="Vector pack signed halfword signed saturate."/>
  4506.     </Instruction>
  4507.     <Instruction>
  4508.         <Details
  4509.            Name="Vector Pack Signed Halfword Unsigned Saturate"
  4510.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB.&#10;&#10;Each signed integer halfword element in the source vector is converted to an 8-bit unsigned integer. If the value of the element is greater than (2^8 - 1) it saturates to (2^8 - 1) and if the value is less than '0' the result saturates to '0'. If saturation occurs, the SAT bit is set. The result is placed into the corresponding byte element of register vD."
  4511.            OtherRegs="SAT"
  4512.            Pseudocode="         do i=0 to 63 by 8&#10;           (vD)[i:i+7]     = SItoUIsat((vA)i*2:(i*2)+15,8)&#10;           (vD)[i+64:i+71] = SItoUIsat((vB)i*2:(i*2)+15,8)&#10;         end"/>
  4513.         <Mnemonic
  4514.            Form="vpkshus vD,vA,vB"
  4515.            Notes="Vector pack signed halfword unsigned saturate."/>
  4516.     </Instruction>
  4517.     <Instruction>
  4518.         <Details
  4519.            Name="Vector Pack Signed Word Signed Saturate"
  4520.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB.&#10;&#10;Each signed integer word element in the source vector is converted to a 16-bit signed integer halfword. If the value of the element is greater than (2^15 - 1) the result saturates to (2^15 - 1) and if the value is less than (-2^15) the result saturates to (-2^15). If saturation occurs, the SAT bit is set. The result is placed into the corresponding halfword element of register vD."
  4521.            OtherRegs="SAT"
  4522.            Pseudocode="        do i=0 to 63 by 16&#10;          (vD)[i:i+15] = SItoSIsat((vA)[i*2:(i*2)+31],16)&#10;          (vD)[i+64:i+79] = SItoSIsat((vB)[i*2:(i*2)+31],16)&#10;        end"/>
  4523.         <Mnemonic
  4524.            Form="vpkswss vD,vA,vB"
  4525.            Notes="Vector pack signed word signed saturate."/>
  4526.     </Instruction>
  4527.     <Instruction>
  4528.         <Details
  4529.            Name="Vector Pack Signed Word Unsigned Saturate"
  4530.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB.&#10;&#10;Each signed integer word element in the source vector is converted to a 16-bit unsigned integer. If the value of the element is greater than (2^16 - 1) the result saturates to (2^16 - 1) and if the value is less than '0' the result saturates to '0'. If saturation occurs, the SAT bit is set. The result is placed into the corresponding halfword element of register vD."
  4531.            OtherRegs="SAT"
  4532.            Pseudocode="         do i=0 to 63 by 16&#10;           (vD)[i:i+15] = SItoUIsat((vA)[i*2:(i*2)+31],16)&#10;           (vD)[i+64:i+79] = SItoUIsat((vB)[i*2:(i*2)+31],16)&#10;         end"/>
  4533.         <Mnemonic
  4534.            Form="vpkswus vD,vA,vB"
  4535.            Notes="Vector pack signed word unsigned saturate."/>
  4536.     </Instruction>
  4537.     <Instruction>
  4538.         <Details
  4539.            Name="Vector Pack Unsigned Halfword Unsigned Modulo"
  4540.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB.&#10;&#10;The low-order byte of each halfword element in the source vector is placed into the corresponding byte element of register vD."
  4541.            OtherRegs=""
  4542.            Pseudocode="        do i=0 to 63 by 8&#10;          (vD)[i:i+7] = (vA)[(i*2)+8:(i*2)+15]&#10;          (vD)[i+64:i+71] = (vB)[(i*2)+8:(i*2)+15]&#10;        end"/>
  4543.         <Mnemonic
  4544.            Form="vpkuhum vD,vA,vB"
  4545.            Notes="Vector pack unsigned halfword unsigned modulo."/>
  4546.     </Instruction>
  4547.     <Instruction>
  4548.         <Details
  4549.            Name="Vector Pack Unsigned Halfword Unsigned Saturate"
  4550.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB.&#10;&#10;Each unsigned integer halfword element in the source vector is converted to an 8-bit unsigned integer. If the value of the element is greater than (28 - 1) the result saturates to (28 - 1). If saturation occurs, the SAT bit is set. The result is placed into the corresponding byte element of register vD."
  4551.            OtherRegs="SAT"
  4552.            Pseudocode="         do i=0 to 63 by 8&#10;           (vD)[i:i+7] = UItoUIsat((vA)[i*2:(i*2)+15],8)&#10;           (vD)[i+64:i+71] = UItoUIsat((vB)[i*2:(i*2)+15],8)&#10;         end"/>
  4553.         <Mnemonic
  4554.            Form="vpkuhus vD,vA,vB"
  4555.            Notes="Vector pack unsigned halfword unsigned saturate."/>
  4556.     </Instruction>
  4557.     <Instruction>
  4558.         <Details
  4559.            Name="Vector Pack Unsigned Word Unsigned Modulo"
  4560.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB.&#10;&#10;The low-order halfword of each word element in the source vector is placed into the corresponding halfword element of register vD."
  4561.            OtherRegs=""
  4562.            Pseudocode="        do i=0 to 63 by 16&#10;          (vD)[i:i+15] = (vA)[(i*2)+16:(i*2)+31]&#10;          (vD)[i+64:i+79] = (vB)[(i*2)+16:(i*2)+31]&#10;        end"/>
  4563.         <Mnemonic
  4564.            Form="vpkuwum vD,vA,vB"
  4565.            Notes="Vector pack unsigned word unsigned modulo."/>
  4566.     </Instruction>
  4567.     <Instruction>
  4568.         <Details
  4569.            Name="Vector Pack Unsigned Word Unsigned Saturate"
  4570.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB.&#10;&#10;Each unsigned integer word element in the source vector is converted to a 16-bit unsigned integer. If the value of the element is greater than (2^16 - 1) the result saturates to (2^16 - 1). If saturation occurs, the SAT bit is set. The result is placed into the corresponding halfword element of register vD."
  4571.            OtherRegs="SAT"
  4572.            Pseudocode="         do i=0 to 63 by 16&#10;           (vD)[i:i+15] = UItoUIsat((vA)[i*2:(i*2)+31],16)&#10;           (vD)[i+64:i+79] = UItoUIsat((vB)[i*2:(i*2)+31],16)&#10;         end"/>
  4573.         <Mnemonic
  4574.            Form="vpkuwus vD,vA,vB"
  4575.            Notes="Vector pack unsigned word unsigned saturate."/>
  4576.     </Instruction>
  4577.     <Instruction>
  4578.         <Details
  4579.            Name="Vector Reciprocal Estimate Floating Point"
  4580.            Description="The single-precision floating-point estimate of the reciprocal of each single-precision floating-point element in register vB is placed into the corresponding element of register vD.&#10;&#10;Operation with various special values of the element in vB is summarized below.&#10;Value: Result&#10;-INF: -0&#10;-0: -INF&#10;+0: +INF&#10;+INF: +0&#10;NaN: QNaN&#10;&#10;If VSCR[NJ] ='1', every denormalized operand element is truncated to a '0' of the same sign before the operation is carried out, and each denormalized result element truncates to a '0' of the same sign."
  4581.            OtherRegs=""
  4582.            Pseudocode="        do i=0 to 127 by 32&#10;          x = (vB)[i:i+31]&#10;          (vD)[i:i+31] = 1/x&#10;        end"/>
  4583.         <Mnemonic
  4584.            Form="vrefp vD,vB"
  4585.            Notes="Vector reciprocal estimate floating point."/>
  4586.     </Instruction>
  4587.     <Instruction>
  4588.         <Details
  4589.            Name="Vector Round to Floating-Point Integer toward Minus Infinity"
  4590.            Description="Each single-precision floating-point word element in register vB is rounded to a single-precision floating-point integer, using the rounding mode Round toward -Infinity, and placed into the corresponding word element of register vD."
  4591.            OtherRegs=""
  4592.            Pseudocode="        do i=0 to 127 by 32&#10;          (vD)[i:i+31] = RndToFPInt32Floor((vB)[i:i+31])&#10;        end"/>
  4593.         <Mnemonic
  4594.            Form="vrfim vD,vB"
  4595.            Notes="Vector round to floating-point integer toward minus infinity."/>
  4596.     </Instruction>
  4597.     <Instruction>
  4598.         <Details
  4599.            Name="Vector Round to Floating-Point Integer Nearest"
  4600.            Description="Each single-precision floating-point word element in register vB is rounded to a single-precision floating-point integer, using the rounding mode Round to Nearest, and placed into the corresponding word element of register vD.&#10;&#10;Note: The result is independent of VSCR[NJ]."
  4601.            OtherRegs=""
  4602.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = RndToFPInt32Near((vB)[i:i+31])&#10;         end"/>
  4603.         <Mnemonic
  4604.            Form="vrfin vD,vB"
  4605.            Notes="Vector round to floating-point integer nearest."/>
  4606.     </Instruction>
  4607.     <Instruction>
  4608.         <Details
  4609.            Name="Vector Round to Floating-Point Integer toward Plus Infinity"
  4610.            Description="Each single-precision floating-point word element in vB is rounded to a single-precision floating-point integer, using the rounding mode Round toward +Infinity, and placed into the corresponding word element of vD. If VSCR[NJ] ='1', every denormalized operand element is truncated to '0' before the comparison is made."
  4611.            OtherRegs=""
  4612.            Pseudocode="        do i=0 to 127 by 32&#10;          (vD)[i:i+31] = RndToFPInt32Ceil((vB)[i:i+31])&#10;        end"/>
  4613.         <Mnemonic
  4614.            Form="vrfip vD,vB"
  4615.            Notes="Vector round to floating-point integer toward plus infinity."/>
  4616.     </Instruction>
  4617.     <Instruction>
  4618.         <Details
  4619.            Name="Vector Round to Floating-Point Integer toward Zero"
  4620.            Description="Each single-precision floating-point word element in register vB is rounded to a single-precision floating-point integer, using the rounding mode Round toward Zero, and placed into the corresponding word element of register vD.&#10;&#10;Note: The result is independent of VSCR[NJ]."
  4621.            OtherRegs=""
  4622.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = RndToFPInt32Trunc((vB)[i:i+31])&#10;         end"/>
  4623.         <Mnemonic
  4624.            Form="vrfiz vD,vB"
  4625.            Notes="Vector round to floating-point integer toward zero."/>
  4626.     </Instruction>
  4627.     <Instruction>
  4628.         <Details
  4629.            Name="Vector Rotate Left Integer Byte"
  4630.            Description="Each element is a byte. Each byte element in register vA is rotated left by the number of bits specified in the low-order 3 bits of the corresponding byte element in register vB. The result is placed into the corresponding byte element of register vD."
  4631.            OtherRegs=""
  4632.            Pseudocode="        do i=0 to 127 by 8&#10;          sh = (vB)[i+5:i+7]&#10;          (vD)[i:i+7] = ROTL((vA)[i:i+7],sh)&#10;        end"/>
  4633.         <Mnemonic
  4634.            Form="vrlb vD,vA,vB"
  4635.            Notes="Vector rotate left integer byte."/>
  4636.     </Instruction>
  4637.     <Instruction>
  4638.         <Details
  4639.            Name="Vector Rotate Left Integer Halfword"
  4640.            Description="Each element is a halfword. Each halfword element in register vA is rotated left by the number of bits specified in the low-order 4 bits of the corresponding halfword element in register vB. The result is placed into the corresponding halfword element of register vD."
  4641.            OtherRegs=""
  4642.            Pseudocode="         do i=0 to 127 by 16&#10;           sh = (vB)[i+12:i+15]&#10;           (vD)[i:i+15] = ROTL((vA)[i:i+15],sh)&#10;         end"/>
  4643.         <Mnemonic
  4644.            Form="vrlh vD,vA,vB"
  4645.            Notes="Vector rotate left integer halfword."/>
  4646.     </Instruction>
  4647.     <Instruction>
  4648.         <Details
  4649.            Name="Vector Rotate Left Integer Word"
  4650.            Description="Each element is a word. Each word element in register vA is rotated left by the number of bits specified in the low-order 5 bits of the corresponding word element in register vB. The result is placed into the corresponding word element of register vD."
  4651.            OtherRegs=""
  4652.            Pseudocode="        do i=0 to 127 by 32&#10;          sh = (vB)[i+27:i+31]&#10;          (vD)[i:i+31] = ROTL((vA)[i:i+31],sh)&#10;        end"/>
  4653.         <Mnemonic
  4654.            Form="vrlw vD,vA,vB"
  4655.            Notes="Vector rotate left integer word."/>
  4656.     </Instruction>
  4657.     <Instruction>
  4658.         <Details
  4659.            Name="Vector Reciprocal Square Root Estimate Floating Point"
  4660.            Description="The single-precision estimate of the reciprocal of the square root of each single-precision element in register vB is placed into the corresponding word element of register vD. &#10;&#10;Operation with various special values of the element in register vB is summarized below.&#10;Value: Result&#10;-INF: QNaN&#10;less than 0: QNaN&#10;-0: -INF&#10;+0: +INF&#10;+INF: +0&#10;NaN: QNaN"
  4661.            OtherRegs=""
  4662.            Pseudocode="         do i=0 to 127 by 32&#10;           x = (vB)[i:i+31]&#10;           (vD)[i:i+31] = 1/(sqrt(x))&#10;         end"/>
  4663.         <Mnemonic
  4664.            Form="vrsqrtefp vD,vB"
  4665.            Notes="Vector reciprocal square root estimate floating point."/>
  4666.     </Instruction>
  4667.     <Instruction>
  4668.         <Details
  4669.            Name="Vector Conditional Select"
  4670.            Description="For each bit in register vC that contains the value '0', the corresponding bit in register vA is placed into the corresponding bit of register vD. For each bit in register vC that contains the value '1', the corresponding bit in register vB is placed into the corresponding bit of register vD."
  4671.            OtherRegs=""
  4672.            Pseudocode="        do i=0 to 127&#10;          if (vC)[i]=0 then &#10;            (vD)[i] = (vA)[i]&#10;          else &#10;            (vD)[i] = (vB)[i]&#10;        end"/>
  4673.         <Mnemonic
  4674.            Form="vsel vD,vA,vB,vC"
  4675.            Notes="Vector conditional select."/>
  4676.     </Instruction>
  4677.     <Instruction>
  4678.         <Details
  4679.            Name="Vector Shift Left"
  4680.            Description="Let sh be equal to the contents of bits [125-127] of register vB; sh is the shift count in bits (0&lt;=sh&lt;=7).&#10;&#10;The contents of register vA are shifted left by sh bits. Bits shifted out of bit [0] are lost. Zeros are supplied to the vacated bits on the right. The result is placed into register vD.&#10;&#10;The contents of the low-order three bits of all byte elements in register vB must be identical to vB[125-127]; otherwise the value placed into register vD is undefined."
  4681.            OtherRegs=""
  4682.            Pseudocode="         sh = (vB)125:127&#10;         t = 1&#10;         do i = 0 to 127 by 8&#10;           t = t &amp; ((vB)[i+5:i+7] = sh)&#10;         end&#10;         if t = 1 then &#10;           (vD) = (vA) &lt;&lt;ui sh&#10;         else &#10;           (vD) = undefined"/>
  4683.         <Mnemonic
  4684.            Form="vsl vD,vA,vB"
  4685.            Notes="Vector shift left."/>
  4686.     </Instruction>
  4687.     <Instruction>
  4688.         <Details
  4689.            Name="Vector Shift Left Integer Byte"
  4690.            Description="Each element is a byte. Each byte element in register vA is shifted left by the number of bits specified in the low-order 3 bits of the corresponding element in register vB. Bits shifted out of bit [0] of the byte element are lost. Zeros are supplied to the vacated bits on the right. The result is placed into the corresponding byte element of register vD."
  4691.            OtherRegs=""
  4692.            Pseudocode="        do i=0 to 127 by 8&#10;          sh = (vB)[i+5:i+7]&#10;          (vD)[i:i+7] = (vA)[i:i+7] &lt;&lt;ui sh&#10;        end"/>
  4693.         <Mnemonic
  4694.            Form="vslb vD,vA,vB"
  4695.            Notes="Vector shift left integer byte."/>
  4696.     </Instruction>
  4697.     <Instruction>
  4698.         <Details
  4699.            Name="Vector Shift Left Double by Octet Immediate"
  4700.            Description="Let the source vector be the concatenation of the contents of register vA followed by the contents of register vB. Bytes SHB:SHB+15 of the source vector are placed into register vD."
  4701.            OtherRegs=""
  4702.            Pseudocode=""/>
  4703.         <Mnemonic
  4704.            Form="vsldoi vD,"
  4705.            Notes="Vector shift left double by octet immediate."/>
  4706.     </Instruction>
  4707.     <Instruction>
  4708.         <Details
  4709.            Name="Vector Shift Left Integer Halfword"
  4710.            Description="Each element is a halfword. Each halfword element in register vA is shifted left by the number of bits specified in the low-order 4 bits of the corresponding halfword element in register vB. Bits shifted out of bit [0] of the halfword element are lost. Zeros are supplied to the vacated bits on the right. The result is placed into the corresponding halfword element of register vD."
  4711.            OtherRegs=""
  4712.            Pseudocode="        do i=0 to 127 by 16&#10;          sh = (vB)[i+12:i+15]&#10;          (vD)[i:i+15] = (vA)[i:i+15] &lt;&lt;ui sh&#10;        end"/>
  4713.         <Mnemonic
  4714.            Form="vslh vD,vA,vB"
  4715.            Notes="Vector shift left integer halfword."/>
  4716.     </Instruction>
  4717.     <Instruction>
  4718.         <Details
  4719.            Name="Vector Shift Left by Octet"
  4720.            Description="The contents of register vA are shifted left by the number of bytes specified in vB[121-124]. Bytes shifted out of byte [0] are lost. Zeros are supplied to the vacated bytes on the right. The result is placed into register vD."
  4721.            OtherRegs=""
  4722.            Pseudocode="         shb = (vB)[121:124]&#10;         (vD) = (vA) &lt;&lt;ui (shb || 0b000)"/>
  4723.         <Mnemonic
  4724.            Form="vslo vD,vA,vB"
  4725.            Notes="Vector shift left by octet."/>
  4726.     </Instruction>
  4727.     <Instruction>
  4728.         <Details
  4729.            Name="Vector Shift Left Integer Word"
  4730.            Description="Each element is a word. Each word element in register vA is shifted left by the number of bits specified in the low-order 5 bits of the corresponding word element in register vB. Bits shifted out of bit [0] of the word element are lost. Zeros are supplied to the vacated bits on the right. The result is placed into the corresponding word element of register vD."
  4731.            OtherRegs=""
  4732.            Pseudocode="        do i=0 to 127 by 32&#10;          sh = (vB)[i+27:i+31]&#10;          (vD)[i:i+31] = (vA)[i:i+31] &lt;&lt;ui sh&#10;        end"/>
  4733.         <Mnemonic
  4734.            Form="vslw vD,vA,vB"
  4735.            Notes="Vector shift left integer word."/>
  4736.     </Instruction>
  4737.     <Instruction>
  4738.         <Details
  4739.            Name="Vector Splat Byte"
  4740.            Description="The contents of byte element UIMM in register vB are replicated into each byte element of vD.&#10;&#10;Programming note: The vector splat instructions can be used in preparation for performing arithmetic for which one source vector is to consist of elements that all have the same value (for example, multiplying all elements of a vector register by a constant)."
  4741.            OtherRegs=""
  4742.            Pseudocode="         b = UIMM*8&#10;         do i=0 to 127 by 8&#10;           (vD)[i:i+7] = (vB)[b:b+7]&#10;         end"/>
  4743.         <Mnemonic
  4744.            Form="vspltb vD,vB,UIMM"
  4745.            Notes="Vector splat byte."/>
  4746.     </Instruction>
  4747.     <Instruction>
  4748.         <Details
  4749.            Name="Vector Splat Halfword"
  4750.            Description="The contents of halfword element UIMM in register vB are replicated into each halfword element of register&#10;vD.&#10;&#10;Programming note: The vector splat instructions can be used in preparation for performing arithmetic for which one source vector is to consist of elements that all have the same value (for example, multiplying all elements of a vector register by a constant)."
  4751.            OtherRegs=""
  4752.            Pseudocode="         b = UIMM*16&#10;         do i=0 to 127 by 16&#10;           (vD)[i:i+15] = (vB)[b:b+15]&#10;         end"/>
  4753.         <Mnemonic
  4754.            Form="vsplth vD,vB,UIMM"
  4755.            Notes="Vector splat halfword."/>
  4756.     </Instruction>
  4757.     <Instruction>
  4758.         <Details
  4759.            Name="Vector Splat Immediate Signed Byte"
  4760.            Description="Each element of vspltisb is a byte. The value of the SIMM field, sign-extended to 8 bits, is replicated into each byte element of register vD."
  4761.            OtherRegs=""
  4762.            Pseudocode="         do i=0 to 127 by 8&#10;           (vD)[i:i+7] = SignExtend(SIMM,8)&#10;         end"/>
  4763.         <Mnemonic
  4764.            Form="vspltisb vD,SIMM"
  4765.            Notes="Vector splat immediate signed byte."/>
  4766.     </Instruction>
  4767.     <Instruction>
  4768.         <Details
  4769.            Name="Vector Splat Immediate Signed Halfword"
  4770.            Description="Each element of vspltish is a halfword. The value of the SIMM field, sign-extended to 16 bits, is replicated into each halfword element of register vD."
  4771.            OtherRegs=""
  4772.            Pseudocode="        do i=0 to 127 by 16&#10;          (vD)[i:i+15] = SignExtend(SIMM,16)&#10;        end"/>
  4773.         <Mnemonic
  4774.            Form="vspltish vD,SIMM"
  4775.            Notes="Vector splat immediate signed halfword."/>
  4776.     </Instruction>
  4777.     <Instruction>
  4778.         <Details
  4779.            Name="Vector Splat Immediate Signed Word"
  4780.            Description="Each element of vspltisw is a word. The value of the SIMM field, sign-extended to 32 bits, is replicated into each element of register vD."
  4781.            OtherRegs=""
  4782.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = SignExtend(SIMM,32)&#10;         end"/>
  4783.         <Mnemonic
  4784.            Form="vspltisw vD,SIMM"
  4785.            Notes="Vector splat immediate signed word."/>
  4786.     </Instruction>
  4787.     <Instruction>
  4788.         <Details
  4789.            Name="Vector Splat Word"
  4790.            Description="Each element of vspltw is a word. The contents of element UIMM in register vB are replicated into each word element of register vD.&#10;&#10;Programming note: The Vector Splat instructions can be used in preparation for performing arithmetic for which one source vector is to consist of elements that all have the same value (for example, multiplying all elements of a Vector Register by a constant)."
  4791.            OtherRegs=""
  4792.            Pseudocode="         b = UIMM*32&#10;         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = (vB)[b:b+31]&#10;         end"/>
  4793.         <Mnemonic
  4794.            Form="vspltw vD,vB,UIMM"
  4795.            Notes="Vector splat word."/>
  4796.     </Instruction>
  4797.     <Instruction>
  4798.         <Details
  4799.            Name="Vector Shift Right"
  4800.            Description="Let sh be equal to the contents of bits [125-127] of register vB; sh is the shift count in bits (0&lt;=sh&lt;=7). The contents of register vA are shifted right by sh bits. Bits shifted out of bit [127] are lost. Zeros are supplied to the vacated bits on the left. The result is placed into register vD.&#10;&#10;The contents of the low-order three bits of all byte elements in register vB must be identical to vB[125-127]; otherwise the value placed into register vD is undefined."
  4801.            OtherRegs=""
  4802.            Pseudocode="         sh = (vB)125:127&#10;         t = 1&#10;         do i = 0 to 127 by 8&#10;           t = t &amp; ((vB)i+5:i+7 = sh)&#10;         end&#10;         if t = 1 then &#10;           (vD) = (vA) &gt;&gt;ui sh&#10;         else&#10;           (vD) = undefined"/>
  4803.         <Mnemonic
  4804.            Form="vsr vD,vA,vB"
  4805.            Notes="Vector shift right."/>
  4806.     </Instruction>
  4807.     <Instruction>
  4808.         <Details
  4809.            Name="Vector Shift Right Algebraic Byte"
  4810.            Description="Each element is a byte. Each byte element in register vA is shifted right by the number of bits specified in the low-order 3 bits of the corresponding byte element in register vB. Bits shifted out of bit [n-1] of the element are lost. Bit [0] of the element is replicated to fill the vacated bits on the left. The result is placed into the corresponding byte element of register vD."
  4811.            OtherRegs=""
  4812.            Pseudocode="         do i=0 to 127 by 8&#10;           sh = (vB)[i+2:i+7]&#10;           (vD)[i:i+7] = (vA)[i:i+7] &gt;&gt;si sh&#10;         end"/>
  4813.         <Mnemonic
  4814.            Form="vsrab vD,vA,vB"
  4815.            Notes="Vector shift right algebraic byte."/>
  4816.     </Instruction>
  4817.     <Instruction>
  4818.         <Details
  4819.            Name="Vector Shift Right Algebraic Halfword"
  4820.            Description="Each halfword element in register vA is shifted right by the number of bits specified in the low-order 4 bits of the corresponding halfword element in register vB. Bits shifted out of bit [15] of the halfword element are lost.  Bit [0] of the halfword element is replicated to fill the vacated bits on the left. The result is placed into the corresponding halfword element of register vD."
  4821.            OtherRegs=""
  4822.            Pseudocode="        do i=0 to 127 by 16&#10;          sh = (vB)[i+12:i+15]&#10;          (vD)[i:i+15] = (vA)[i:i+15] &gt;&gt;si sh&#10;        end"/>
  4823.         <Mnemonic
  4824.            Form="vsrah vD,vA,vB"
  4825.            Notes="Vector shift right algebraic halfword."/>
  4826.     </Instruction>
  4827.     <Instruction>
  4828.         <Details
  4829.            Name="Vector Shift Right Algebraic Word"
  4830.            Description="Each element is a word. Each element in register vA is shifted right by the number of bits specified in the low-order 5 bits of the corresponding element in register vB. Bits shifted out of bit [31] of the element are lost. Bit [0] of the element is replicated to fill the vacated bits on the left. The result is placed into the corresponding element of register vD."
  4831.            OtherRegs=""
  4832.            Pseudocode="         do i=0 to 127 by 32&#10;           sh = (vB)[i+27:i+31]&#10;           (vD)[i:i+31] = (vA)[i:i+31] &gt;&gt;si sh&#10;         end"/>
  4833.         <Mnemonic
  4834.            Form="vsraw vD,vA,vB"
  4835.            Notes="Vector shift right algebraic word."/>
  4836.     </Instruction>
  4837.     <Instruction>
  4838.         <Details
  4839.            Name="Vector Shift Right Byte"
  4840.            Description="Each element is a byte. Each element in register vA is shifted right by the number of bits specified in the low-order 3 bits of the corresponding element in register vB. Bits shifted out of bit [7] of the element are lost. Zeros are supplied to the vacated bits on the left. The result is placed into the corresponding element of register vD."
  4841.            OtherRegs=""
  4842.            Pseudocode="        do i=0 to 127 by 8&#10;          sh = (vB)[i+5:i+7]&#10;          (vD)[i:i+7] = (vA)[i:i+7] &gt;&gt;ui sh&#10;        end"/>
  4843.         <Mnemonic
  4844.            Form="vsrb vD,vA,vB"
  4845.            Notes="Vector shift right byte."/>
  4846.     </Instruction>
  4847.     <Instruction>
  4848.         <Details
  4849.            Name="Vector Shift Right Halfword"
  4850.            Description="Each element is a halfword. Each element in register vA is shifted right by the number of bits specified in the low-order 4 bits of the corresponding element in register vB. Bits shifted out of bit [15] of the element are lost. Zeros are supplied to the vacated bits on the left. The result is placed into the corresponding element of register vD."
  4851.            OtherRegs=""
  4852.            Pseudocode="         do i=0 to 127 by 16&#10;           sh = (vB)[i+12:i+15]&#10;           (vD)[i:i+15] = (vA)[i:i+15] &gt;&gt;ui sh&#10;         end"/>
  4853.         <Mnemonic
  4854.            Form="vsrh vD,vA,vB"
  4855.            Notes="Vector shift right halfword."/>
  4856.     </Instruction>
  4857.     <Instruction>
  4858.         <Details
  4859.            Name="Vector Shift Right by Octet"
  4860.            Description="The contents of vA are shifted right by the number of bytes specified in vB[121-124]. Bytes shifted out of register vA are lost. Zeros are supplied to the vacated bytes on the left. The result is placed into register vD."
  4861.            OtherRegs=""
  4862.            Pseudocode="        shb = (vB)[121:124]&#10;        (vD) = (vA) &gt;&gt;ui (shb || 0b000)"/>
  4863.         <Mnemonic
  4864.            Form="vsro vD,vA,vB"
  4865.            Notes="Vector shift right by octet."/>
  4866.     </Instruction>
  4867.     <Instruction>
  4868.         <Details
  4869.            Name="Vector Shift Right Word"
  4870.            Description="Each element is a word. Each element in register vA is shifted right by the number of bits specified in the low-order 5 bits of the corresponding element in register vB. Bits shifted out of bit [31] of the element are lost. Zeros are supplied to the vacated bits on the left. The result is placed into the corresponding element of register vD."
  4871.            OtherRegs=""
  4872.            Pseudocode="         do i=0 to 127 by 32&#10;           sh = (vB)[i+27:i+31]&#10;           (vD)[i:i+31] = (vA)[i:i+31] &gt;&gt;ui sh&#10;         end"/>
  4873.         <Mnemonic
  4874.            Form="vsrw vD,vA,vB"
  4875.            Notes="Vector shift right word."/>
  4876.     </Instruction>
  4877.     <Instruction>
  4878.         <Details
  4879.            Name="Vector Subtract Carryout Unsigned Word"
  4880.            Description="Each unsigned-integer word element in register vB is subtracted from the corresponding unsigned-integer word element in register vA. The complement of the borrow out of bit [0] of the 32-bit difference is zero-extended to 32 bits and placed into the corresponding word element of register vD."
  4881.            OtherRegs=""
  4882.            Pseudocode="        do i=0 to 127 by 32&#10;          aop[0:32] = ZeroExtend((vA)i:i+31,33)&#10;          bop[0:32] = ZeroExtend((vB)i:i+31,33)&#10;          temp[0:32] = aop[0:32] +int -bop[0:32] +int 1&#10;          (vD)[i:i+31] = ZeroExtend(temp[0],32)&#10;        end"/>
  4883.         <Mnemonic
  4884.            Form="vsubcuw vD,vA,vB"
  4885.            Notes="Vector subtract carryout unsigned word."/>
  4886.     </Instruction>
  4887.     <Instruction>
  4888.         <Details
  4889.            Name="Vector Subtract Floating Point"
  4890.            Description="Each single-precision floating-point word element in register vB is subtracted from the corresponding single-precision floating-point word element in register vA. The result is rounded to the nearest single-precision floating-point number and placed into the corresponding word element of register vD.&#10;&#10;If VSCR[NJ] ='1', every denormalized operand element is truncated to a '0' of the same sign before the operation is carried out, and each denormalized result element truncates to a '0' of the same sign."
  4891.            OtherRegs=""
  4892.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = RndToNearFP32((vA)[i:i+31] -fp (vB)[i:i+31])&#10;         end"/>
  4893.         <Mnemonic
  4894.            Form="vsubfp vD,vA,vB"
  4895.            Notes="Vector subtract floating point."/>
  4896.     </Instruction>
  4897.     <Instruction>
  4898.         <Details
  4899.            Name="Vector Subtract Signed Byte Saturate"
  4900.            Description="Each element is a byte. Each signed-integer element in register vB is subtracted from the corresponding signed-integer element in register vA. If the intermediate result is greater than (2^7-1) it saturates to (2^7-1) and if the intermediate result is less than (-2^7), it saturates to (-2^7). If saturation occurs, the SAT bit is set. The signed-integer result is placed into the corresponding element of register vD."
  4901.            OtherRegs="SAT"
  4902.            Pseudocode="        do i=0 to 127 by 8&#10;          aop[0:8] = SignExtend((vA)[i:i+7],9)&#10;          bop[0:8] = SignExtend((vB)[i:i+7],9)&#10;          temp[0:8] = aop[0:8] +int -bop[0:8] +int 1&#10;          (vD)[i:i+7] = SItoSIsat(temp[0:8],8)&#10;        end"/>
  4903.         <Mnemonic
  4904.            Form="vsubsbs vD,vA,vB"
  4905.            Notes="Vector subtract signed byte saturate."/>
  4906.     </Instruction>
  4907.     <Instruction>
  4908.         <Details
  4909.            Name="Vector Subtract Signed Halfword Saturate"
  4910.            Description="Each element is a halfword. Each signed-integer element in register vB is subtracted from the corresponding signed-integer element in register vA. If the intermediate result is greater than (2^15-1) it saturates to (2^15-1) and if the intermediate result is less than (-2^15) it saturates to (-2^15). If saturation occurs, the SAT bit is set. The signed-integer result is placed into the corresponding element of register vD."
  4911.            OtherRegs="SAT"
  4912.            Pseudocode="         do i=0 to 127 by 16&#10;           aop[0:16] = SignExtend((vA)[i:i+15],17)&#10;           bop[0:16] = SignExtend((vB)[i:i+15],17)&#10;           temp[0:16] = aop[0:16] +int -bop[0:16] +int 1&#10;           (vD)[i:i+15] = SItoSIsat(temp[0:16],16)&#10;         end"/>
  4913.         <Mnemonic
  4914.            Form="vsubshs vD,vA,vB"
  4915.            Notes="Vector subtract signed halfword saturate."/>
  4916.     </Instruction>
  4917.     <Instruction>
  4918.         <Details
  4919.            Name="Vector Subtract Signed Word Saturate"
  4920.            Description="Each element is a word. Each signed-integer element in register vB is subtracted from the corresponding signed-integer element in register vA. If the intermediate result is greater than (2^31-1) it saturates to (2^31-1) and if the intermediate result is less than (-2^31) it saturates to (-2^31). If saturation occurs, the SAT bit is set. The signed-integer result is placed into the corresponding element of register vD."
  4921.            OtherRegs="SAT"
  4922.            Pseudocode="        do i=0 to 127 by 32&#10;          aop[0:32] = SignExtend((vA)[i:i+31],33)&#10;          bop[0:32] = SignExtend((vB)[i:i+31],33)&#10;          temp[0:32] = aop[0:32] +int -bop[0:32] +int 1&#10;          (vD)[i:i+31] = SItoSIsat(temp[0:32],32)&#10;        end"/>
  4923.         <Mnemonic
  4924.            Form="vsubsws vD,vA,vB"
  4925.            Notes="Vector subtract signed word saturate."/>
  4926.     </Instruction>
  4927.     <Instruction>
  4928.         <Details
  4929.            Name="Vector Subtract Unsigned Byte Modulo"
  4930.            Description="Each element of vsububm is a byte. Each integer element in register vB is subtracted from the corresponding integer element in register vA. The integer result is placed into the corresponding element of register vD.&#10;&#10;Note the vsububm instruction can be used for unsigned or signed integers."
  4931.            OtherRegs=""
  4932.            Pseudocode="         do i=0 to 127 by 8&#10;           (vD)[i:i+7] = (vA)[i:i+7] +int -(vB)[i:i+7]&#10;         end"/>
  4933.         <Mnemonic
  4934.            Form="vsububm vD,vA,vB"
  4935.            Notes="Vector subtract unsigned byte modulo."/>
  4936.     </Instruction>
  4937.     <Instruction>
  4938.         <Details
  4939.            Name="Vector Subtract Unsigned Byte Saturate"
  4940.            Description="Each element is a byte. Each unsigned-integer element in register vB is subtracted from the corresponding unsigned-integer element in register vA. If the intermediate result is less than '0' it saturates to '0'. If saturation occurs, the SAT bit is set. The unsigned-integer result is placed into the corresponding element of register vD."
  4941.            OtherRegs="SAT"
  4942.            Pseudocode="        do i=0 to 127 by 8&#10;          aop[0:8] = ZeroExtend((vA)[i:i+7],9)&#10;          bop[0:8] = ZeroExtend((vB)[i:i+7],9)&#10;          temp[0:8] = aop[0:8] +int -bop[0:8] +int 1&#10;          (vD)[i:i+7] = SItoUIsat(temp[0:8],8)&#10;        end"/>
  4943.         <Mnemonic
  4944.            Form="vsububs vD,vA,vB"
  4945.            Notes="Vector subtract unsigned byte saturate."/>
  4946.     </Instruction>
  4947.     <Instruction>
  4948.         <Details
  4949.            Name="Vector Subtract Signed Halfword Modulo"
  4950.            Description="Each element is a halfword. Each integer element in register vB is subtracted from the corresponding integer element in register vA. The integer result is placed into the corresponding element of register vD.&#10;&#10;Notes: vsubuhm instruction can be used for unsigned or signed integers."
  4951.            OtherRegs=""
  4952.            Pseudocode="         do i=0 to 127 by 16&#10;           (vD)[i:i+15] = (vA)[i:i+15] +int -(vB)[i:i+15]&#10;         end"/>
  4953.         <Mnemonic
  4954.            Form="vsubuhm vD,vA,vB"
  4955.            Notes="Vector subtract signed halfword modulo."/>
  4956.     </Instruction>
  4957.     <Instruction>
  4958.         <Details
  4959.            Name="Vector Subtract Signed Halfword Saturate"
  4960.            Description="Each element is a halfword. Each unsigned-integer element in register vB is subtracted from the corresponding unsigned-integer element in register vA. If the intermediate result is less than '0' it saturates to '0'. If saturation occurs, the SAT bit is set. The unsigned-integer result is placed into the corresponding element of register vD."
  4961.            OtherRegs="SAT"
  4962.            Pseudocode="        do i=0 to 127 by 16&#10;          aop[0:16] = ZeroExtend((vA)[i:i+15],17)&#10;          bop[0:16] = ZeroExtend((vB)[i:i+15],17)&#10;          temp[0:16] = aop[0:16] +int -bop[0:16] +int 1&#10;          (vD)[i:i+15] = SItoUIsat(temp[0:16],16)&#10;        end"/>
  4963.         <Mnemonic
  4964.            Form="vsubuhs vD,vA,vB"
  4965.            Notes="Vector subtract signed halfword saturate."/>
  4966.     </Instruction>
  4967.     <Instruction>
  4968.         <Details
  4969.            Name="Vector Subtract Unsigned Word Modulo"
  4970.            Description="Each element of vsubuwm is a word. Each integer element in register vB is subtracted from the corresponding integer element in register vA. The integer result is placed into the corresponding element of register vD.&#10;&#10;Note: The vsubuwm instruction can be used for unsigned or signed integers."
  4971.            OtherRegs=""
  4972.            Pseudocode="         do i=0 to 127 by 32&#10;           (vD)[i:i+31] = (vA)[i:i+31] +int -(vB)[i:i+31]&#10;         end"/>
  4973.         <Mnemonic
  4974.            Form="vsubuwm vD,vA,vB"
  4975.            Notes="Vector subtract unsigned word modulo."/>
  4976.     </Instruction>
  4977.     <Instruction>
  4978.         <Details
  4979.            Name="Vector Subtract Unsigned Word Saturate"
  4980.            Description="Each element is a word. Each unsigned-integer element in register vB is subtracted from the corresponding unsigned-integer element in register vA. If the intermediate result is less than '0' it saturates to '0'. If saturation occurs, the SAT bit is set.The unsigned-integer result is placed into the corresponding element of register vD."
  4981.            OtherRegs="SAT"
  4982.            Pseudocode="        do i=0 to 127 by 32&#10;          aop[0:32] = ZeroExtend((vA)[i:i+31],33)&#10;          bop[0:32] = ZeroExtend((vB)[i:i+31],33)&#10;          temp[0:32] = aop[0:32] +int -bop[0:32] +int 1&#10;          (vD)[i:i+31] = SItoUIsat(temp[0:32],32)&#10;        end"/>
  4983.         <Mnemonic
  4984.            Form="vsubuws vD,vA,vB"
  4985.            Notes="Vector subtract unsigned word saturate."/>
  4986.     </Instruction>
  4987.     <Instruction>
  4988.         <Details
  4989.            Name="Vector Sum Across Signed Word Saturate"
  4990.            Description="The signed-integer sum of the four signed-integer word elements in register vA is added to the signed-integer word element in bits of vB[96-127]. If the intermediate result is greater than (2^31-1) it saturates to (2^31-1) and if it is less than (-2^31) it saturates to (-2^31). If saturation occurs, the SAT bit is set. The signed-integer result is placed into bits vD[96-127]. Bits vD[0-95] are cleared."
  4991.            OtherRegs="SAT"
  4992.            Pseudocode="         temp[0:34] = SignExtend((vB)[96:127],35)&#10;         do i=0 to 127 by 32&#10;           temp[0:34] = temp[0:34] +int SignExtend((vA)[i:i+31],35)&#10;           (vD) = {96}0 || SItoSIsat(temp[0:34],32)&#10;         end"/>
  4993.         <Mnemonic
  4994.            Form="vsumsws vD,vA,vB"
  4995.            Notes="Vector sum across signed word saturate."/>
  4996.     </Instruction>
  4997.     <Instruction>
  4998.         <Details
  4999.            Name="Vector Sum Across Half Partial Signed Word Saturate"
  5000.            Description="The signed-integer sum of the first two signed-integer word elements in register vA is added to the signed-integer word element in vB[32-63]. If the intermediate result is greater than (2^31-1) it saturates to (2^31-1) and if the intermediate result is less than (-2^31) it saturates to (-2^31). If saturation occurs, the SAT bit is set. The signed-integer result is placed into vD[32-63].&#10;&#10;The signed-integer sum of the last two signed-integer word elements in register vA is added to the signed-integer word element in vB[96-127]. If the intermediate result is greater than (2^31-1) it saturates to (2^31-1) and if it is less than (-2^31) it saturates to (-2^31). If saturation occurs, the SAT bit is set. The signed-integer result is placed into vD[96-127]. The bits vD[0-31,64-95] are cleared to '0'."
  5001.            OtherRegs="SAT"
  5002.            Pseudocode="        do i=0 to 127 by 64&#10;          temp[0:33] = SignExtend((vB)[i+32:i+63],34)&#10;          do j=0 to 63 by 32&#10;            temp[0:33] = temp[0:33] +int SignExtend((vA)[i+j:i+j+31],34)&#10;          end&#10;          (vD)[i:i+63] = {32}0 || SItoSIsat(temp[0:33],32)&#10;        end"/>
  5003.         <Mnemonic
  5004.            Form="vsum2sws vD,vA,vB"
  5005.            Notes="Vector sum across half partial signed word saturate."/>
  5006.     </Instruction>
  5007.     <Instruction>
  5008.         <Details
  5009.            Name="Vector Sum Across Quarter Partial"
  5010.            Description="For each word element in register vB the following operations are performed in the order shown:&#10; * The signed-integer sum of the four signed-integer byte elements contained in the corresponding word element of register vA is added to the signed-integer word element in register vB.&#10; * If the intermediate result is greater than (2^31-1) it saturates to (2^31-1) and if it is less than (-2^31) it saturates to (-2^31). If saturation occurs, the SAT bit is set.&#10; * The signed-integer result is placed into the corresponding word element of register vD."
  5011.            OtherRegs="SAT"
  5012.            Pseudocode="         do i=0 to 127 by 32&#10;          temp[0:32] = SignExtend((vB)[i:i+31],33)&#10;           do j=0 to 31 by 8&#10;             temp[0:32] = temp[0:32] +int SignExtend((vA)[i+j:i+j+7],33)&#10;           end&#10;           (vD)[i:i+31] = SItoSIsat(temp[0:32],32)&#10;         end"/>
  5013.         <Mnemonic
  5014.            Form="vsum4sbs vD,vA,vB"
  5015.            Notes="Vector sum across quarter partial (1/4) signed byte saturate."/>
  5016.     </Instruction>
  5017.     <Instruction>
  5018.         <Details
  5019.            Name="Vector Sum Across Quarter Partial Signed Halfword Saturate"
  5020.            Description="For each word element in register vB the following operations are performed, in the order shown:&#10; * The signed-integer sum of the two signed-integer halfword elements contained in the corresponding word element of register vA is added to the signed-integer word element in vB.&#10; * If the intermediate result is greater than (2^31-1) it saturates to (2^31-1) and if it is less than -2^31 it saturates to -2^31. If saturation occurs, the SAT bit is set.&#10; * The signed-integer result is placed into the corresponding word element of register vD."
  5021.            OtherRegs="SAT"
  5022.            Pseudocode="        do i=0 to 127 by 32&#10;          temp[0:32] = SignExtend((vB)[i:i+31],33)&#10;          do j=0 to 31 by 16&#10;            temp[0:32] = temp[0:32] +int SignExtend((vA)[i+j:i+j+15],33)&#10;          end&#10;          (vD)[i:i+31] = SItoSIsat(temp[0:32],32)&#10;        end"/>
  5023.         <Mnemonic
  5024.            Form="vsum4shs vD,vA,vB"
  5025.            Notes="Vector sum across quarter partial signed halfword saturate."/>
  5026.     </Instruction>
  5027.     <Instruction>
  5028.         <Details
  5029.            Name="Vector Sum Across Quarter Partial Unsigned Byte Saturate"
  5030.            Description="For each word element in vB the following operations are performed in the order shown:&#10; * The unsigned-integer sum of the four unsigned-integer byte elements contained in the corresponding word element of register vA is added to the unsigned-integer word element in register vB.&#10; * If the intermediate result is greater than (2^32-1) it saturates to (2^32-1). If saturation occurs, the SAT bit is set.&#10; * The unsigned-integer result is placed into the corresponding word element of vD."
  5031.            OtherRegs="SAT"
  5032.            Pseudocode="         do i=0 to 127 by 32&#10;           temp[0:32] = ZeroExtend((vB)[i:i+31],33)&#10;           do j=0 to 31 by 8&#10;             temp[0:32] = temp[0:32] +int ZeroExtend((vA)[i+j:i+j+7],33)&#10;           end&#10;           (vD)[i:i+31] = UItoUIsat(temp[0:32],32)&#10;         end"/>
  5033.         <Mnemonic
  5034.            Form="vsum4ubs vD,vA,vB"
  5035.            Notes="Vector sum across quarter partial unsigned byte saturate."/>
  5036.     </Instruction>
  5037.     <Instruction>
  5038.         <Details
  5039.            Name="Vector Unpack High"
  5040.            Description="Each halfword element in the high-order half of register vB is unpacked to produce a 32-bit value as described below and placed, in the same order, into the four words of register vD.&#10;&#10;A halfword is unpacked to 32 bits by concatenating, in order, the results of the following operations.&#10; * sign-extend bit [0] of the halfword to 8 bits&#10; * zero-extend bits [1-5] of the halfword to 8 bits&#10; * zero-extend bits [6-10] of the halfword to 8 bits&#10; * zero-extend bits [11-15] of the halfword to 8 bits"
  5041.            OtherRegs=""
  5042.            Pseudocode="        do i=0 to 63 by 16&#10;          (vD)[i*2:(i*2)+7] = SignExtend((vB)[i],8)                   &#10;          (vD)[(i*2)+8:(i*2)+15] = ZeroExtend((vB)[i+1:i+5],8)&#10;          (vD)[(i*2)+16:(i*2)+23] = ZeroExtend((vB)[i+6:i+10],8)&#10;          (vD)[(i*2)+24:(i*2)+31] = ZeroExtend((vB)[i+11:i+15],8)&#10;        end"/>
  5043.         <Mnemonic
  5044.            Form="vupkhpx vD,vB"
  5045.            Notes="Vector unpack high pixel16."/>
  5046.     </Instruction>
  5047.     <Instruction>
  5048.         <Details
  5049.            Name="Vector Unpack High Signed Byte"
  5050.            Description="Each signed integer byte element in the high-order half of register vB is sign-extended to produce a 16-bit signed integer and placed, in the same order, into the eight halfwords of register vD."
  5051.            OtherRegs=""
  5052.            Pseudocode="         do i=0 to 63 by 8&#10;           (vD)[i*2:(i*2)+15] = SignExtend((vB)[i:i+7],16)&#10;         end"/>
  5053.         <Mnemonic
  5054.            Form="vupkhsb vD,vB"
  5055.            Notes="Vector unpack high signed byte."/>
  5056.     </Instruction>
  5057.     <Instruction>
  5058.         <Details
  5059.            Name="Vector Unpack High Signed Halfword"
  5060.            Description="Each signed integer halfword element in the high-order half of register vB is sign-extended to produce a 32-bit signed integer and placed, in the same order, into the four words of register vD."
  5061.            OtherRegs=""
  5062.            Pseudocode="        do i=0 to 63 by 16&#10;          (vD)[i*2:(i*2)+31] = SignExtend((vB)[i:i+15],32)&#10;        end"/>
  5063.         <Mnemonic
  5064.            Form="vupkhsh vD,vB"
  5065.            Notes="Vector unpack high signed halfword."/>
  5066.     </Instruction>
  5067.     <Instruction>
  5068.         <Details
  5069.            Name="Vector Unpack Low"
  5070.            Description="Each halfword element in the low-order half of register vB is unpacked to produce a 32-bit value as described below and placed, in the same order, into the four words of register vD.&#10;&#10;A halfword is unpacked to 32 bits by concatenating, in order, the results of the following operations:&#10; * sign-extend bit [0] of the halfword to 8 bits&#10; * zero-extend bits [1-5] of the halfword to 8 bits&#10; * zero-extend bits [6-10] of the halfword to 8 bits&#10; * zero-extend bits [11-15] of the halfword to 8 bits&#10;&#10;Programming note: Notice that the unpacking done by the Vector Unpack Pixel instructions does not reverse the packing done by the Vector Pack Pixel instruction. Specifically, if a 16-bit pixel is unpacked to a 32-bit pixel which is then packed to a 16-bit pixel, the resulting 16-bit pixel will not, in general, be equal to the original 16-bit pixel (because, for each channel except the first, Vector Unpack Pixel inserts high-order bits while Vector Pack Pixel discards low-order bits)."
  5071.            OtherRegs=""
  5072.            Pseudocode="         do i=0 to 63 by 16&#10;           (vD)[i*2:(i*2)+7] = SignExtend((vB)[i+64],8)&#10;           (vD)[(i*2)+8:(i*2)+15] = ZeroExtend((vB)[i+65:i+69],8)&#10;           (vD)[(i*2)+16:(i*2)+23] = ZeroExtend((vB)[i+70:i+74],8)&#10;           (vD)[(i*2)+24:(i*2)+31] = ZeroExtend((vB)[i+75:i+79],8)&#10;         end"/>
  5073.         <Mnemonic
  5074.            Form="vupklpx vD,vB"
  5075.            Notes="Vector unpack low pixel16."/>
  5076.     </Instruction>
  5077.     <Instruction>
  5078.         <Details
  5079.            Name="Vector Unpack Low Signed Byte"
  5080.            Description="Each signed integer byte element in the low-order half of register vB is sign-extended to produce a 16-bit signed integer and placed, in the same order, into the eight halfwords of register vD."
  5081.            OtherRegs=""
  5082.            Pseudocode="        do i=0 to 63 by 8&#10;          (vD)[i*2:(i*2)+15] = SignExtend((vB)[i+64:i+71],16)&#10;        end"/>
  5083.         <Mnemonic
  5084.            Form="vupklsb vD,vB"
  5085.            Notes="Vector unpack low signed byte."/>
  5086.     </Instruction>
  5087.     <Instruction>
  5088.         <Details
  5089.            Name="Vector Unpack Low Signed Halfword"
  5090.            Description="Each signed integer halfword element in the low-order half of register vB is sign-extended to produce a 32-bit signed integer and placed, in the same order, into the four words of register vD."
  5091.            OtherRegs=""
  5092.            Pseudocode="         do i=0 to 63 by 16&#10;           (vD)[i*2:(i*2)+31] = SignExtend((vB)[i+64:i+79],32)&#10;         end"/>
  5093.         <Mnemonic
  5094.            Form="vupklsh vD,vB"
  5095.            Notes="Vector unpack low signed halfword."/>
  5096.     </Instruction>
  5097.     <Instruction>
  5098.         <Details
  5099.            Name="Vector Logical XOR"
  5100.            Description="The contents of register vA are XORed with the contents of register vB and the result is placed into register vD."
  5101.            OtherRegs=""
  5102.            Pseudocode=""/>
  5103.         <Mnemonic
  5104.            Form="vxor vD,vA,vB"
  5105.            Notes="Vector logical XOR."/>
  5106.     </Instruction>
  5107.     <Instruction>
  5108.         <Details
  5109.            Name="Load Vector Left Indexed"
  5110.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB.&#10;&#10;Let eb be the value of bits [60-63] of EA.&#10;&#10;The 16-eb bytes in memory addressed by EA are loaded into the left-most 16-eb byte elements of register vD. The right-most eb byte elements of register vD are set to 0.&#10;&#10;This instruction is not supported in little-endian mode, and an attempt to execute this instruction in little-endian mode will cause an alignment exception.&#10;&#10;Note: lvlx is supported only on the Cell Broadband Engine Processor and is not portable to other implementations of the vector/SIMD multimedia extension technology."
  5111.            OtherRegs=""
  5112.            Pseudocode="        if rA=0 then &#10;          base = 0&#10;        else&#10;          base = (rA)&#10;        EA = (base + (rB))&#10;        eb = EA[60:63]&#10;        (vD) = MEM(EA,16-eb) || {eb*8} (0)"/>
  5113.         <Mnemonic
  5114.            Form="lvlx vD,rA,rB"
  5115.            Notes="Load vector left. The addressing mode is register indirect with index."/>
  5116.     </Instruction>
  5117.     <Instruction>
  5118.         <Details
  5119.            Name="Load Vector Left Indexed Last"
  5120.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB.&#10;&#10;Let eb be the value of bits [60-63] of EA.&#10;&#10;The (16-eb) bytes in memory addressed by EA are loaded into the left-most (16-eb) byte elements of register vD. The right-most eb byte elements of register vD are set to '0'.&#10;&#10;This instruction provides a hint that the quadword in memory accessed by EA will probably not be needed again by the program in the near future.&#10;&#10;This instruction is not supported in little-endian mode, and an attempt to execute this instruction in little-endian mode will cause an alignment exception.&#10;&#10;Note: lvlxl is supported only on the Cell Broadband Engine Processor and is not portable to other implementations of the vector/SIMD multimedia extension technology."
  5121.            OtherRegs=""
  5122.            Pseudocode="         if rA=0 then &#10;           base = 0&#10;         else&#10;           base = (rA)&#10;         EA = (base + (rB))&#10;         eb = EA[60:63]&#10;         (vD) = MEM(EA,16-eb) || {eb*8} (0)&#10;         mark_cache_block_as_not_likely_to_be_needed_again_anytime_soon(EA)"/>
  5123.         <Mnemonic
  5124.            Form="lvlxl vD,rA,rB"
  5125.            Notes="Load vector left. The addressing mode is register indirect with index. The quadword at the effective address will probably not be used in future."/>
  5126.     </Instruction>
  5127.     <Instruction>
  5128.         <Details
  5129.            Name="Load Vector Right Indexed"
  5130.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB.&#10;&#10;Let eb be the value of bits [60-63] of EA.&#10;&#10;If eb is not equal to '0' (for example, EA is not quadword-aligned), then eb bytes in memory addressed by (EA-eb) are loaded into the right-most eb byte elements of vD and the left-most (16-eb) byte elements of register vD are set to '0'.&#10;&#10;If eb is equal to '0' (for example, EA is quadword-aligned), then the contents of register vD are set to '0'.&#10;&#10;This instruction is not supported in little-endian mode, and an attempt to execute this instruction in little-endian mode will cause an alignment exception.&#10;&#10;Note: lvrx is supported only on the Cell Broadband Engine Processor and is not portable to other implementations of the vector/SIMD multimedia extension technology."
  5131.            OtherRegs=""
  5132.            Pseudocode="        if rA=0 then &#10;          base = 0&#10;        else&#10;          base = (rA)&#10;        EA = (base + (rB))&#10;        eb = EA[60:63]&#10;        (vD) = {(16-eb)*8} (0) || MEM(EA-eb,eb)"/>
  5133.         <Mnemonic
  5134.            Form="lvrx vD,rA,rB"
  5135.            Notes="Load vector right. The addressing mode is register indirect with index."/>
  5136.     </Instruction>
  5137.     <Instruction>
  5138.         <Details
  5139.            Name="Load Vector Right Indexed Last"
  5140.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB.&#10;&#10;Let eb be the value of bits [60-63] of EA.&#10;&#10;If eb is not equal to '0' (for example, EA is not quadword-aligned), then eb bytes in memory addressed by (EA-eb) are loaded into the right-most eb byte elements of vD and the left-most (16-eb) byte elements of register vD are set to '0'.&#10;&#10;If eb is equal to '0' (for example, EA is quadword-aligned), then the contents of register vD are set to '0'.&#10;&#10;This instruction provides a hint that the quadword in memory accessed by EA will probably not be needed again by the program in the near future.&#10;&#10;This instruction is not supported in little-endian mode, and an attempt to execute this instruction in little-endian mode will cause an alignment exception.&#10;&#10;Note: lvrxl is supported only on the Cell Broadband Engine Processor and is not portable to other implementations of the vector/SIMD multimedia extension technology."
  5141.            OtherRegs=""
  5142.            Pseudocode="         if rA=0 then &#10;           base = 0&#10;         else&#10;           base = (rA)&#10;         EA = (base + (rB))&#10;         eb = EA60:63&#10;         (vD) = {(16-eb)*8}(0) || MEM(EA-eb,eb)&#10;         mark_cache_block_as_not_likely_to_be_needed_again_anytime_soon(EA)"/>
  5143.         <Mnemonic
  5144.            Form="lvrxl vD,rA,rB"
  5145.            Notes="Load vector right. The addressing mode is register indirect with index. The quadword at the effective address will probably not be used in future."/>
  5146.     </Instruction>
  5147.     <Instruction>
  5148.         <Details
  5149.            Name="Store Vector Left Indexed"
  5150.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB.&#10;&#10;Let eb be the value of bits [60-63] of EA.&#10;&#10;The contents of the left-most 16-eb byte elements of register vS are stored into the 16-eb bytes of memory addressed by EA.&#10;&#10;This instruction is not supported in little-endian mode, and an attempt to execute this instruction in little-endian mode will cause an alignment exception.&#10;&#10;Note: stvlx is supported only on the Cell Broadband Engine Processor and is not portable to other implementations of the vector/SIMD multimedia extension technology."
  5151.            OtherRegs=""
  5152.            Pseudocode="        if rA=0 then &#10;          b = 0   &#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        eb = EA[60:63]&#10;        MEM(EA,16-eb) = (vS)[0:127-(eb*8)]"/>
  5153.         <Mnemonic
  5154.            Form="stvlx vS,rA,rB"
  5155.            Notes="Store vector left. The addressing mode is register indirect with index."/>
  5156.     </Instruction>
  5157.     <Instruction>
  5158.         <Details
  5159.            Name="Store Vector Left Indexed Last"
  5160.            Description="Let the effective address EA be the sum of the contents of register rA, or the value 0 if rA is equal to 0, and the contents of register rB.&#10;&#10;Let eb be the value of bits [60-63] of EA.&#10;&#10;The contents of the left-most 16-eb byte elements of register vS are stored into the 16-eb bytes of memory addressed by EA.&#10;&#10;This instruction provides a hint that the quadword in memory accessed by EA will probably not be needed again by the program in the near future.&#10;&#10;This instruction is not supported in little-endian mode, and an attempt to execute this instruction in little-endian mode will cause an alignment exception.&#10;&#10;Note: stvlxl is supported only on the Cell Broadband Engine Processor and is not portable to other implementations of the vector/SIMD multimedia extension technology."
  5161.            OtherRegs=""
  5162.            Pseudocode="         if rA=0 then &#10;           b = 0&#10;         else&#10;           b = (rA)&#10;         EA = b + (rB)&#10;         eb = EA[60:63]&#10;         MEM(EA,16-eb) = (vS)[0:127-(eb*8)]&#10;         mark_cache_block_as_not_likely_to_be_needed_again_anytime_soon(EA)"/>
  5163.         <Mnemonic
  5164.            Form="stvlxl vS,rA,rB"
  5165.            Notes="Store vector left. The addressing mode is register indirect with index. The quadword at the effective address will probably not be used in future."/>
  5166.     </Instruction>
  5167.     <Instruction>
  5168.         <Details
  5169.            Name="Store Vector Right Indexed"
  5170.            Description="Let the effective address EA be the sum of the contents of register rA, or the value 0 if rA is equal to 0, and the contents of register rB.&#10;&#10;Let eb be the value of bits [60-63] of EA.&#10;&#10;If eb is not equal to '0' (for example, EA is not quadword-aligned), then the contents of the right-most eb byte elements of register vS are stored into the eb bytes of memory addressed by (EA-eb).&#10;&#10;If eb is equal to '0' (for example, EA is quadword-aligned), then memory is not altered by this instruction.&#10;&#10;This instruction is not supported in little-endian mode, and an attempt to execute this instruction in little-endian mode will cause an alignment exception.&#10;&#10;Note: stvrx is supported only on the Cell Broadband Engine Processor and is not portable to other implementations of the vector/SIMD multimedia extension technology."
  5171.            OtherRegs=""
  5172.            Pseudocode="        if rA=0 then &#10;          b = 0&#10;        else&#10;          b = (rA)&#10;        EA = b + (rB)&#10;        eb = EA[60:63]&#10;        if eb!=0 then&#10;           MEM(EA-eb,eb) = (vS)[128-(eb*8):127]"/>
  5173.         <Mnemonic
  5174.            Form="stvrx vS,rA,rB"
  5175.            Notes="Store vector right. The addressing mode is register indirect with index."/>
  5176.     </Instruction>
  5177.     <Instruction>
  5178.         <Details
  5179.            Name="Store Vector Right Indexed Last"
  5180.            Description="Let the effective address EA be the sum of the contents of register rA, or the value '0' if rA is equal to '0', and the contents of register rB.&#10;&#10;Let eb be the value of bits [60-63] of EA.&#10;&#10;If eb is not equal to '0' (for example, EA is not quadword-aligned), then the contents of the right-most eb byte elements of register vS are stored into the eb bytes of memory addressed by (EA-eb).&#10;&#10;If eb is equal to '0' (for example, EA is quadword-aligned), then memory is not altered by this instruction.&#10;&#10;This instruction provides a hint that the quadword in memory accessed by EA will probably not be needed again by the program in the near future.&#10;&#10;This instruction is not supported in little-endian mode, and an attempt to execute this instruction in little-endian mode will cause an alignment exception.&#10;&#10;Note: stvrxl is supported only on the Cell Broadband Engine Processor and is not portable to other implementations of the vector/SIMD multimedia extension technology."
  5181.            OtherRegs=""
  5182.            Pseudocode="         if rA=0 then &#10;           b = 0&#10;         else &#10;           b = (rA)&#10;         EA = b + (rB)&#10;         eb = EA[60:63]&#10;         if eb!=0 then&#10;            MEM(EA-eb,eb) = (vS)[128-(eb*8):127]&#10;            mark_cache_block_as_not_likely_to_be_needed_again_anytime_soon(EA)"/>
  5183.         <Mnemonic
  5184.            Form="stvrxl vS,rA,rB"
  5185.            Notes="Store vector right. The addressing mode is register indirect with index. The quadword at the effective address will probably not be used in future."/>
  5186.     </Instruction>
  5187. </InstructionHelp>
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