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- LIBRARY ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- entity RAM is
- port (
- r_reset :in std_logic;
- r_ready :in std_logic;
- clk : in std_logic;
- r_CPU_cs : in std_logic;
- r_CPU_data_in : in std_logic_vector (0 to 63);
- r_CPU_address : in std_logic_vector (0 to 15);
- r_DMA_cs : in std_logic;
- r_DMA_data_in : in std_logic_vector (0 to 63);
- r_DMA_command : in std_logic_vector (0 to 1);
- r_DMA_address : in std_logic_vector (0 to 15);
- r_DMA_data_out : out std_logic_vector (0 to 63));
- end RAM;
- architecture behave of RAM is
- type ram_64k_x64 is array (0 to 65536) of std_logic_vector(0 to 63);
- signal r_memory_Ram : ram_64k_x64 := (
- 15 => x"000000000000001A",
- 16 => x"C000000000000014",
- 17 => x"000000000000001A",
- 18 => x"A000000C0000000A",
- 19 => x"0000000000001213",
- 20 => x"C000000000000000",
- 21 => x"0AAAAAAAAAAA0001",
- 300 => x"D000000000003456",
- 301 => x"000000000000001A",
- 302 => x"C0000000000000A0",
- 303 => x"0000000000000001",
- 304 => x"C0000000000000DD",
- others => x"0000000000000000"
- );
- -- pragma sythesis_off
- -- pragma sythesis_on
- begin
- process(clk) -- cs - выборка кристала, если cs = 1 - zzzz
- begin
- If r_reset = '1' then
- r_DMA_data_out <= x"0000000000000000";
- elsif (rising_edge(clk)) then
- IF (r_CPU_cs = '0') then
- r_memory_Ram(to_integer (unsigned(r_CPU_address))) <= r_CPU_data_in;
- r_DMA_data_out <= x"0000000000000000";
- elsif (r_DMA_cs = '1' ) then -- спящий режим
- r_DMA_data_out <= x"0000000000000000";
- elsif (r_ready ='0') then
- if (r_DMA_command = "01") then -- команда чтения
- r_DMA_data_out <= r_memory_Ram(to_integer (unsigned(r_DMA_address)));
- elsif (r_DMA_command = "10") then -- команда записи
- r_memory_Ram(to_integer (unsigned(r_DMA_address))) <= r_DMA_data_in;
- r_DMA_data_out <= x"0000000000000000";
- end if;
- end if;
- end if;
- end process;
- end behave;
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