mux_7_seg_w_bin2bcd

----------------------------------------------------------------------------------
-- Company: UnB
-- Aluno: Felipe R. Sobrinho
-- Matrícula: 17/0141764
-- Disciplina: Prática de Eetrônica 2 - 2019/1
-- Professor: Gilmar Beserra

----------------------------------------------------------------------------------



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity mux7seg is
    Port ( clk : in STD_LOGIC;
           dig : in STD_LOGIC_VECTOR(15 downto 0);
           seg : out STD_LOGIC_VECTOR (6 downto 0);
           an : out STD_LOGIC_VECTOR (3 downto 0));
end mux7seg;

architecture Behavioral of mux7seg is
    signal count : STD_LOGIC_VECTOR (1 downto 0) := "00";
    signal number: STD_LOGIC_VECTOR (3 downto 0) := "0000";
    signal dig_aux: STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
    signal in_binary: STD_LOGIC_VECTOR (7 downto 0);
    signal digit_0  : STD_LOGIC_VECTOR (3 downto 0);
    signal digit_1  : STD_LOGIC_VECTOR (3 downto 0);
    signal digit_2  : STD_LOGIC_VECTOR (3 downto 0);
    signal clk_7_segs: STD_LOGIC;


begin

process(clk)
variable counter: integer range 0 to 200000;
begin
    if rising_edge(clk)then
    if counter=200000 then
        clk_7_segs<=not(clk_7_segs);
        counter:=0;
    else
        counter:= counter+1;
    end if;
    end if;
end process;


    process(in_binary)
        variable s_digit_0 : unsigned( 3 downto 0);
        variable s_digit_1 : unsigned( 3 downto 0);
        variable s_digit_2 : unsigned( 3 downto 0);

        begin
            s_digit_2 := "0000";
            s_digit_1 := "0000";
            s_digit_0 := "0000";

            for i in 7 downto 0 loop
              if (s_digit_2 >= 5) then s_digit_2 := s_digit_2 + 3; end if;
              if (s_digit_1 >= 5) then s_digit_1 := s_digit_1 + 3; end if;
              if (s_digit_0 >= 5) then s_digit_0 := s_digit_0 + 3; end if;
              s_digit_2 := s_digit_2 sll 1; s_digit_2(0) := s_digit_1(3);
              s_digit_1 := s_digit_1 sll 1; s_digit_1(0) := s_digit_0(3);
              s_digit_0 := s_digit_0 sll 1; s_digit_0(0) := in_binary(i);
            end loop;

            digit_0 <=  std_logic_vector(s_digit_0);
            digit_1 <=  std_logic_vector(s_digit_1);
            digit_2 <=  std_logic_vector(s_digit_2);
      end process;



dig_aux <= dig (15 downto 0);

anodo_process: process (clk_7_segs)
    begin
        if rising_edge (clk) then
            count <= count +'1';
            case count is
                when "00" =>
                    an <= "1110";
                    number <= digit_0;

                when "01" =>
                    an <= "1101";
                    number <= digit_1;

                when "10" =>
                    an <= "1011";
                    number <= digit_2;

                when "11" =>
                    an <= "0111";
                    number <= "0000";
                    count <= "00";
                when others =>
                    an <= "1111";
                    count <= "00";
           end case;
       end if;
    end process;


    with number select --gfedcba
      seg <=  "1000000" when "0000",
              "1111001" when "0001",
              "0100100" when "0010",
              "0110000" when "0011",
              "0011001" when "0100",
              "0010010" when "0101",
              "0000010" when "0110",
              "1111000" when "0111",
              "0000000" when "1000",
              "0010000" when "1001",
              "0100000" when "1010",
              "0000011" when "1011",
              "1000110" when "1100",
              "0100001" when "1101",
              "0000110" when "1110",
              "0001110" when "1111",
               (others=>'1') when others;
end Behavioral;