mux7seg

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-- Company:
-- Engineer:
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-- Create Date: 05/17/2019 08:11:16 PM
-- Design Name:
-- Module Name: mux7seg - Behavioral
-- Project Name:
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-- Tool Versions:
-- Description:
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-- Dependencies:
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-- Revision:
-- Revision 0.01 - File Created
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux7seg is
    Port (clk   : in STD_LOGIC;
          porta : in STD_LOGIC;
          AA    : in STD_LOGIC_VECTOR (1 downto 0);
          seg   : out STD_LOGIC_VECTOR (6 downto 0);
          an    : out STD_LOGIC_VECTOR (3 downto 0));
end mux7seg;

architecture Behavioral of mux7seg is
    signal count : STD_LOGIC_VECTOR (1 downto 0);
begin

anodo_process: process (clk)
    begin
        if rising_edge (clk) then
            count <= count +'1';
            case count is
                when "00" =>
                    an <= "1110";
                        if porta = '0' and AA = "00" then
                            seg <= "1100010";
                        elsif porta = '1' and AA = "00" then
                            seg <= "1101011";
                        else
                            seg <= "0001000";
                        end if;

                when "01" =>
                    an <= "1101";
                    if porta = '0' and AA = "01" then
                            seg <= "1100010";
                        elsif porta = '1' and AA = "01" then
                            seg <= "1101011";
                        else
                            seg <= "0001000";
                        end if;

                when "10" =>
                    an <= "1011";
                    if porta = '0' and AA = "10" then
                            seg <= "1100010";
                        elsif porta = '1' and AA = "10" then
                            seg <= "1101011";
                        else
                            seg <= "0001000";
                        end if;

                when "11" =>
                    an <= "0111";
                    if porta = '0' and AA = "11" then
                            seg <= "1100010";
                        elsif porta = '1' and AA = "11" then
                            seg <= "1101011";
                        else
                            seg <= "0001000";
                        end if;
                    count <= "00";
                when others =>
                    an <= "1111";
                    count <= "00";
           end case;
       end if;
    end process;



end Behavioral;