----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:    12:45:29 11/16/2012
-- Design Name:
-- Module Name:    zad11 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity zad11 is
    Port ( iCLK : in  STD_LOGIC;
           iRESET : in  STD_LOGIC;
           iW : in  STD_LOGIC_vector(1 downto 0);
           oZ : out  STD_LOGIC);
end zad11;

architecture Behavioral of zad11 is
    type tStanje is (S0, S1, S2);
    signal sStanje, sSledece_Stanje : tStanje;
    signal sZ : std_logic;
begin
process (iW, sStanje) begin
    case sStanje is
        when S0 =>
            case iW is
                when "00" => sSledece_Stanje <= S1; sZ <= '0';
                when "01" => sSledece_Stanje <= S1; sZ <= '0';
                when "10" => sSledece_Stanje <= S2; sZ <= '1';
                when others => sSledece_Stanje <= S1; sZ <= '0';
            end case;
        when S1 =>
            case iW is
                when "00" => sSledece_Stanje <= S2; sZ <= '0';
                when "01" => sSledece_Stanje <= S1; sZ <= '0';
                when "10" => sSledece_Stanje <= S2; sZ <= '0';
                when others => sSledece_Stanje <= S1; sZ <= '0';
            end case;
        when S2 =>
            case iW is
                when "00" => sSledece_Stanje <= S0; sZ <= '1';
                when "01" => sSledece_Stanje <= S0; sZ <= '0';
                when "10" => sSledece_Stanje <= S2; sZ <= '0';
                when others => sSledece_Stanje <= S1; sZ <= '0';
            end case;
    end case;
end process;

process (iCLK) begin
    if(iRESET = '1') then
        sStanje <= S1;
        oZ <= '0';
    elsif(iCLK'event and iCLK = '1') then
        sStanje <= sSledece_Stanje;
        oZ <= sZ;
    end if;
end process;



end Behavioral;

-- TESTBENCH
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date:   12:53:33 11/16/2012
-- Design Name:
-- Module Name:   C:/FAX/LPRS/zad112011/zad11_tb.vhd
-- Project Name:  zad112011
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: zad11
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY zad11_tb IS
END zad11_tb;

ARCHITECTURE behavior OF zad11_tb IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT zad11
    PORT(
         iCLK : IN  std_logic;
         iRESET : IN  std_logic;
         iW : IN  std_logic_vector(1 downto 0);
         oZ : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal iCLK : std_logic := '0';
   signal iRESET : std_logic := '0';
   signal iW : std_logic_vector(1 downto 0) := (others => '0');

    --Outputs
   signal oZ : std_logic;

   -- Clock period definitions
   constant iCLK_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: zad11 PORT MAP (
          iCLK => iCLK,
          iRESET => iRESET,
          iW => iW,
          oZ => oZ
        );

   -- Clock process definitions
   iCLK_process :process
   begin
        iCLK <= '0';
        wait for iCLK_period/2;
        iCLK <= '1';
        wait for iCLK_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      iRESET <= '1';
        wait for iCLK_period*3;
        iRESET <= '0';

        iW <= "00";
        wait for iCLK_period;

        iW <= "01";
        wait for iCLK_period*4;

        iW <= "10";
        wait for iCLK_period;

        iW <= "01";
        wait for iCLK_period;

        iW <= "10";
        wait for iCLK_period;

        iW <= "00";
        wait for iCLK_period;

      -- insert stimulus here

      wait;
   end process;

END;