new NES mapper design

1024KB PRG ROM
1024KB PRG RAM
32KB or 128KB CHR RAM
four screen mirroring
scanline interrupts

$4800 - Same as register $0f (IRQ)
$5000 - Port address ($00-$0f)
$5800 - Port data ($00-$ff)

If $8000-$ffff is write protected:
$8000-$9fff - Port address
$a000-$bfff - Port data

Like with MMC3 and FME-7, writing to Port Address selects a register to write to, and Port Data writes to the selected register.

$00: CHR slot A
$01: CHR slot B
$02: CHR slot C
$03: CHR slot D
$04: CHR slot E
$05: CHR slot F
$06: CHR slot G
$07: CHR slot H
32KB:
 ..nn nnnn .5K bank
 ...n nnnn  1K bank
 ...n nnn.  2K bank
 ...n nn..  4K bank
256KB:
 nnnn nnnn .5K bank (first 128KB only)
 nnnn nnnn  1K bank
 nnnn nnn.  2K bank
 nnnn nn..  4K bank

PRG banks:
 rbbb bbbb
 |+++-++++- 8kb PRG bank
 +--------- 0=ROM, 1=RAM
$08: PRG bank at $6000-$7fff
$09: PRG bank at $8000-$9fff
$0a: PRG bank at $a000-$bfff
$0b: PRG bank at $c000-$dfff
$0e: PRG bank at $e000-$ffff
Loss of M2 oscillation (caused by resets) causes register $0d to revert to a value of $7F, mapping the last ROM bank in the cart into $E000-$FFFF.

$0c: Mirroring and CHR mode
 .wcc sfmm
  ||| ||++- mirroring mode
  ||| |+--- four-screen from CHR RAM $7000-$7fff, ignores mm if on
  ||| +---- swap $0xxx with $1xxx
  |++------ CHR mode
  +-------- if 0, $8000-$ffff is write protected and $8000/$a000 work for address/data

Mirroring (same as FME-7):
 0: vertical mirroring (horizontal arrangement) from CIRAM
 1: horizontal mirroring (vertical arrangement) from CIRAM
 2: One-screen, lower bank of CIRAM
 3: One-screen, upper bank of CIRAM
When combined with sprite 0 or the optional IRQ feature, this allows four-screen mirroring and a status bar at the same time, as the playfield is in CHR RAM and the status bar is in CIRAM.

CHR mode: (A through H are assigned in order)
    $0xxx          | $1xxx
 0: 1K, 1K, 1K, 1K | 1K,  1K,  1K,  1K
 1: 2K, 1K, 1K     | 2K, .5K, .5K, .5K, .5K
 2: 2K, 2K         | 1K,  1K, .5K, .5K, .5K, .5K
 3: 4K             | 1K, .5K, .5K, .5K, .5K, .5K, .5K

$0f: Set IRQ count
At the start of each scanline, the PPU freezes for a few cycles, and PPU A13 stays high for at least three consecutive cycles of PPU /RD. The mapper detects this and subtracts 1 from the value in $0e unless the value is $F0-$FF. While the value is 0, /IRQ is pulled low.
Programming tip: Reading from the nametables or palette during vertical or forced blanking will cause counts unless you write $FF to port $0e.
Some implementations may count M2 cycles (1.8 MHz) instead of PPU /RD cycles (2.7 MHz) to save a pin. Cost-reduced versions may lack IRQ logic entirely.

$0d: Unused