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- module drawfinish(
- input clk, // Input clock signal
- input [1:0] state_transition, // State transition input
- input [10:0] draw_x, // X-coordinate input
- input [9:0] draw_y, // Y-coordinate input
- input [3:0] p1wr, p1wg, p1wb, // Player 1 color inputs
- input [3:0] p2wr, p2wg, p2wb, // Player 2 color inputs
- output [3:0] out_r, out_g, out_b, // RGB output
- output reg [1:0] rd_enp1win, // Player 1 window read enable
- output reg [1:0] rd_enp2win // Player 2 window read enable
- );
- reg [3:0] r, g, b; // RGB values for output
- reg [3:0] pic_r, pic_g, pic_b; // Player 1 window color
- reg [3:0] p2_r, p2_g, p2_b; // Player 2 window color
- wire rd_enp1win; // Player 1 window read enable (wire)
- wire rd_enp2win; // Player 2 window read enable (wire)
- // Player 1 window read enable logic
- assign rd_enp1win = ((draw_x >= 240) && (draw_x <= 1039) && (draw_y >= 175) && (draw_y <= 624));
- // Player 2 window read enable logic
- assign rd_enp2win = ((draw_x >= 240) && (draw_x <= 1039) && (draw_y >= 175) && (draw_y <= 624));
- // Player 1 window color logic
- always @(posedge clk) begin
- if (rd_enp1win == 1'd1 && p1wb > 4'd0000) begin
- pic_r <= 4'b1111;
- pic_g <= 4'b1111; // pic
- pic_b <= 4'b1111;
- end
- else begin
- pic_r = 4'b1111;
- pic_g = 4'b1111; // pic
- pic_b = 4'b1111;
- end
- end
- // Player 2 window color logic
- always @(posedge clk) begin
- if (rd_enp2win == 1'd1 && p2wb > 4'd0000) begin
- p2_r <= 4'b1111;
- p2_g <= 4'b1111; // pic
- p2_b <= 4'b1111;
- end
- else begin
- p2_r = 4'b1111;
- p2_g = 4'b1111; // pic
- p2_b = 4'b1111;
- end
- end
- // Output color logic based on state transition
- always @* begin
- if (state_transition == 1) // Player 1 wins
- if (rd_enp1win == 1'd1) begin
- // If block color is non-zero, assign it to the RGB outputs
- r = pic_b;
- g = pic_b;
- b = pic_b;
- end
- else begin
- r = 4'b1111;
- g = 4'b1111;
- b = 4'b1111;
- end
- else begin
- if (rd_enp2win == 1'd1) begin // Player 2 wins
- // If block color is non-zero, assign it to the RGB outputs
- r = p2_b;
- g = p2_b;
- b = p2_b;
- end
- else begin
- r = 4'b1111;
- g = 4'b1111;
- b = 4'b1111;
- end
- end
- end
- // Assign output values
- assign out_r = r;
- assign out_g = g;
- assign out_b = b;
- endmodule
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