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AlexanderAntonov

Untitled

Oct 17th, 2022
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  1. module ram_2rw
  2.   #(
  3.     parameter dat_width=32, adr_width=32, mem_size=1024
  4.   )
  5.   (
  6.     input [dat_width-1:0]      dat0_i,
  7.     input [adr_width-1:0]      adr0_i,
  8.     input          we0_i,
  9.     output reg [dat_width-1:0] dat0_o,
  10.  
  11.     input [dat_width-1:0]      dat1_i,
  12.     input [adr_width-1:0]      adr1_i,
  13.     input          we1_i,
  14.     output reg [dat_width-1:0] dat1_o,
  15.  
  16.     input          clk
  17.   );
  18.  
  19. reg [dat_width-1:0] ram [0:mem_size - 1] ;
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