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  1. rm -fr lib work *.json *.svf *.config *-report.txt
  2. mkdir lib
  3. ghdl -i --workdir=lib/ --work=ecp5um ../../library/ecp5u/components.vhdl
  4. yosys -m ghdl -p \
  5. "ghdl -Plib -gCLK_FREQUENCY=25000000 versa_ecp5_top.vhdl pll_mac.vhd soc_iomap_pkg.vhdl uart.vhdl uart_tx.vhdl uart_rx.vhdl fifobuf.vhdl -e versa_ecp5_top; \
  6. read_verilog ../../library/wrapper/primitives.v ../../library/wrapper/bram.v; \
  7. synth_ecp5 \
  8. -top versa_ecp5_top -json versa_ecp5_top.json" 2>&1 | tee versa_ecp5_top-report.txt
  9.  
  10. /----------------------------------------------------------------------------\
  11. | |
  12. | yosys -- Yosys Open SYnthesis Suite |
  13. | |
  14. | Copyright (C) 2012 - 2020 Claire Xenia Wolf <claire@yosyshq.com> |
  15. | |
  16. | Permission to use, copy, modify, and/or distribute this software for any |
  17. | purpose with or without fee is hereby granted, provided that the above |
  18. | copyright notice and this permission notice appear in all copies. |
  19. | |
  20. | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
  21. | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
  22. | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
  23. | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
  24. | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
  25. | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
  26. | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
  27. | |
  28. \----------------------------------------------------------------------------/
  29.  
  30. Yosys 0.28+1 (git sha1 a9c792dce, clang 14.0.0-1ubuntu1 -fPIC -Os)
  31.  
  32.  
  33. -- Running command `ghdl -Plib -gCLK_FREQUENCY=25000000 versa_ecp5_top.vhdl pll_mac.vhd soc_iomap_pkg.vhdl uart.vhdl uart_tx.vhdl uart_rx.vhdl fifobuf.vhdl -e versa_ecp5_top; read_verilog ../../library/wrapper/primitives.v ../../library/wrapper/bram.v; synth_ecp5 -top versa_ecp5_top -json versa_ecp5_top.json' --
  34.  
  35. 1. Executing GHDL.
  36. pll_mac.vhd:53:5:warning: instance "scuba_vhi_inst" of component "vhi" is not bound [-Wbinding]
  37. scuba_vhi_inst: VHI
  38. ^
  39. pll_mac.vhd:22:14:warning: (in default configuration of pll_mac(structure))
  40. pll_mac.vhd:56:5:warning: instance "scuba_vlo_inst" of component "vlo" is not bound [-Wbinding]
  41. scuba_vlo_inst: VLO
  42. ^
  43. pll_mac.vhd:22:14:warning: (in default configuration of pll_mac(structure))
  44. pll_mac.vhd:59:5:warning: instance "pllinst_0" of component "ehxplll" is not bound [-Wbinding]
  45. PLLInst_0: EHXPLLL
  46. ^
  47. pll_mac.vhd:22:14:warning: (in default configuration of pll_mac(structure))
  48. fifobuf.vhdl:160:1:warning: instance "ram" of component "bram_2psync" is not bound [-Wbinding]
  49. ram:
  50. ^
  51. fifobuf.vhdl:34:14:warning: (in default configuration of fifobuffer(behaviour))
  52. pll_mac.vhd:49:15:warning: attribute "ngd_drc_mask" for architecture "structure" of "pll_mac" is not kept in the netlist [-Wunkept-attribute]
  53. attribute NGD_DRC_MASK of Structure : architecture is 1;
  54. ^
  55. pll_mac.vhd:49:15:warning: unhandled attribute "ngd_drc_mask" [-Wunhandled-attribute]
  56. attribute NGD_DRC_MASK of Structure : architecture is 1;
  57. ^
  58. pll_mac.vhd:46:15:warning: unhandled attribute "lpf_resistor" [-Wunhandled-attribute]
  59. attribute LPF_RESISTOR of PLLInst_0 : label is "16";
  60. ^
  61. pll_mac.vhd:45:15:warning: unhandled attribute "icp_current" [-Wunhandled-attribute]
  62. attribute ICP_CURRENT of PLLInst_0 : label is "7";
  63. ^
  64. pll_mac.vhd:44:15:warning: unhandled attribute "frequency_pin_clki" [-Wunhandled-attribute]
  65. attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "100.000000";
  66. ^
  67. pll_mac.vhd:43:15:warning: unhandled attribute "frequency_pin_clkop" [-Wunhandled-attribute]
  68. attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000";
  69. ^
  70. pll_mac.vhd:42:15:warning: unhandled attribute "frequency_pin_clkos" [-Wunhandled-attribute]
  71. attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "25.000000";
  72. ^
  73. pll_mac.vhd:41:15:warning: unhandled attribute "frequency_pin_clkos2" [-Wunhandled-attribute]
  74. attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "50.000000";
  75. ^
  76. pll_mac.vhd:40:15:warning: unhandled attribute "frequency_pin_clkos3" [-Wunhandled-attribute]
  77. attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "75.000000";
  78. ^
  79. Importing module versa_ecp5_top.
  80. Importing module pll_mac.
  81. Importing module uart_core_6_c575f3e383df5c81fb057f50806caf1436554d70.
  82. Importing module VHI.
  83. Importing module VLO.
  84. Importing module EHXPLLL.
  85. Importing module uartrx_3.
  86. Importing module uarttx.
  87. Importing module fifobuffer_6_8_904fcba6bac2ff7d8e3cafd7c89647b407aa349b.
  88. Importing module bram_2psync.
  89.  
  90. 2. Executing Verilog-2005 frontend: ../../library/wrapper/primitives.v
  91. Parsing Verilog input from `../../library/wrapper/primitives.v' to AST representation.
  92. Generating RTLIL representation for module `\vhi'.
  93. Generating RTLIL representation for module `\vlo'.
  94. Successfully finished Verilog frontend.
  95.  
  96. 3. Executing Verilog-2005 frontend: ../../library/wrapper/bram.v
  97. Parsing Verilog input from `../../library/wrapper/bram.v' to AST representation.
  98. Replacing existing blackbox module `\bram_2psync' at ../../library/wrapper/bram.v:4.1-46.10.
  99. Generating RTLIL representation for module `\bram_2psync'.
  100. Warning: reg '\a_read' is assigned in a continuous assignment at ../../library/wrapper/bram.v:30.8-30.28.
  101. Successfully finished Verilog frontend.
  102.  
  103. 4. Executing SYNTH_ECP5 pass.
  104.  
  105. 4.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_sim.v
  106. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_sim.v' to AST representation.
  107. Generating RTLIL representation for module `\LUT4'.
  108. Generating RTLIL representation for module `\$__ABC9_LUT5'.
  109. Generating RTLIL representation for module `\$__ABC9_LUT6'.
  110. Generating RTLIL representation for module `\$__ABC9_LUT7'.
  111. Generating RTLIL representation for module `\L6MUX21'.
  112. Generating RTLIL representation for module `\CCU2C'.
  113. Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
  114. Generating RTLIL representation for module `\PFUMX'.
  115. Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
  116. Generating RTLIL representation for module `\DPR16X4C'.
  117. Generating RTLIL representation for module `\LUT2'.
  118. Generating RTLIL representation for module `\TRELLIS_FF'.
  119. Generating RTLIL representation for module `\TRELLIS_IO'.
  120. Generating RTLIL representation for module `\INV'.
  121. Generating RTLIL representation for module `\TRELLIS_COMB'.
  122. Generating RTLIL representation for module `\DP16KD'.
  123. Generating RTLIL representation for module `\FD1P3AX'.
  124. Generating RTLIL representation for module `\FD1P3AY'.
  125. Generating RTLIL representation for module `\FD1P3BX'.
  126. Generating RTLIL representation for module `\FD1P3DX'.
  127. Generating RTLIL representation for module `\FD1P3IX'.
  128. Generating RTLIL representation for module `\FD1P3JX'.
  129. Generating RTLIL representation for module `\FD1S3AX'.
  130. Generating RTLIL representation for module `\FD1S3AY'.
  131. Generating RTLIL representation for module `\FD1S3BX'.
  132. Generating RTLIL representation for module `\FD1S3DX'.
  133. Generating RTLIL representation for module `\FD1S3IX'.
  134. Generating RTLIL representation for module `\FD1S3JX'.
  135. Generating RTLIL representation for module `\IFS1P3BX'.
  136. Generating RTLIL representation for module `\IFS1P3DX'.
  137. Generating RTLIL representation for module `\IFS1P3IX'.
  138. Generating RTLIL representation for module `\IFS1P3JX'.
  139. Generating RTLIL representation for module `\OFS1P3BX'.
  140. Generating RTLIL representation for module `\OFS1P3DX'.
  141. Generating RTLIL representation for module `\OFS1P3IX'.
  142. Generating RTLIL representation for module `\OFS1P3JX'.
  143. Generating RTLIL representation for module `\IB'.
  144. Generating RTLIL representation for module `\IBPU'.
  145. Generating RTLIL representation for module `\IBPD'.
  146. Generating RTLIL representation for module `\OB'.
  147. Generating RTLIL representation for module `\OBZ'.
  148. Generating RTLIL representation for module `\OBZPU'.
  149. Generating RTLIL representation for module `\OBZPD'.
  150. Generating RTLIL representation for module `\OBCO'.
  151. Generating RTLIL representation for module `\BB'.
  152. Generating RTLIL representation for module `\BBPU'.
  153. Generating RTLIL representation for module `\BBPD'.
  154. Generating RTLIL representation for module `\ILVDS'.
  155. Generating RTLIL representation for module `\OLVDS'.
  156. Successfully finished Verilog frontend.
  157.  
  158. 4.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_bb.v
  159. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_bb.v' to AST representation.
  160. Generating RTLIL representation for module `\MULT18X18D'.
  161. Generating RTLIL representation for module `\ALU54B'.
  162. Replacing existing blackbox module `\EHXPLLL' at /usr/local/bin/../share/yosys/ecp5/cells_bb.v:120.1-165.10.
  163. Generating RTLIL representation for module `\EHXPLLL'.
  164. Generating RTLIL representation for module `\DTR'.
  165. Generating RTLIL representation for module `\OSCG'.
  166. Generating RTLIL representation for module `\USRMCLK'.
  167. Generating RTLIL representation for module `\JTAGG'.
  168. Generating RTLIL representation for module `\DELAYF'.
  169. Generating RTLIL representation for module `\DELAYG'.
  170. Generating RTLIL representation for module `\IDDRX1F'.
  171. Generating RTLIL representation for module `\IDDRX2F'.
  172. Generating RTLIL representation for module `\IDDR71B'.
  173. Generating RTLIL representation for module `\IDDRX2DQA'.
  174. Generating RTLIL representation for module `\ODDRX1F'.
  175. Generating RTLIL representation for module `\ODDRX2F'.
  176. Generating RTLIL representation for module `\ODDR71B'.
  177. Generating RTLIL representation for module `\OSHX2A'.
  178. Generating RTLIL representation for module `\ODDRX2DQA'.
  179. Generating RTLIL representation for module `\ODDRX2DQSB'.
  180. Generating RTLIL representation for module `\TSHX2DQA'.
  181. Generating RTLIL representation for module `\TSHX2DQSA'.
  182. Generating RTLIL representation for module `\DQSBUFM'.
  183. Generating RTLIL representation for module `\DDRDLLA'.
  184. Generating RTLIL representation for module `\DLLDELD'.
  185. Generating RTLIL representation for module `\CLKDIVF'.
  186. Generating RTLIL representation for module `\ECLKSYNCB'.
  187. Generating RTLIL representation for module `\ECLKBRIDGECS'.
  188. Generating RTLIL representation for module `\DCCA'.
  189. Generating RTLIL representation for module `\DCSC'.
  190. Generating RTLIL representation for module `\DCUA'.
  191. Generating RTLIL representation for module `\EXTREFB'.
  192. Generating RTLIL representation for module `\PCSCLKDIV'.
  193. Generating RTLIL representation for module `\PUR'.
  194. Generating RTLIL representation for module `\GSR'.
  195. Generating RTLIL representation for module `\SGSR'.
  196. Generating RTLIL representation for module `\PDPW16KD'.
  197. Successfully finished Verilog frontend.
  198.  
  199. 4.3. Executing HIERARCHY pass (managing design hierarchy).
  200.  
  201. 4.3.1. Analyzing design hierarchy..
  202. Top module: \versa_ecp5_top
  203. Used module: \uart_core_6_c575f3e383df5c81fb057f50806caf1436554d70
  204. Used module: \fifobuffer_6_8_904fcba6bac2ff7d8e3cafd7c89647b407aa349b
  205. Used module: \bram_2psync
  206. Used module: \uarttx
  207. Used module: \uartrx_3
  208. Used module: \pll_mac
  209. Parameter \DATA = 31'0000000000000000000000000001000
  210. Parameter \ADDR = 31'0000000000000000000000000000110
  211.  
  212. 4.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\bram_2psync'.
  213. Parameter \DATA = 31'0000000000000000000000000001000
  214. Parameter \ADDR = 31'0000000000000000000000000000110
  215. Generating RTLIL representation for module `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync'.
  216. Warning: reg '\a_read' is assigned in a continuous assignment at ../../library/wrapper/bram.v:30.8-30.28.
  217.  
  218. 4.3.3. Analyzing design hierarchy..
  219. Top module: \versa_ecp5_top
  220. Used module: \uart_core_6_c575f3e383df5c81fb057f50806caf1436554d70
  221. Used module: \fifobuffer_6_8_904fcba6bac2ff7d8e3cafd7c89647b407aa349b
  222. Used module: $paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync
  223. Used module: \uarttx
  224. Used module: \uartrx_3
  225. Used module: \pll_mac
  226.  
  227. 4.3.4. Analyzing design hierarchy..
  228. Top module: \versa_ecp5_top
  229. Used module: \uart_core_6_c575f3e383df5c81fb057f50806caf1436554d70
  230. Used module: \fifobuffer_6_8_904fcba6bac2ff7d8e3cafd7c89647b407aa349b
  231. Used module: $paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync
  232. Used module: \uarttx
  233. Used module: \uartrx_3
  234. Used module: \pll_mac
  235. Removing unused module `\bram_2psync'.
  236. Removing unused module `\vhi'.
  237. Removing unused module `\vlo'.
  238. Removed 3 unused modules.
  239.  
  240. 4.4. Executing PROC pass (convert processes to netlists).
  241.  
  242. 4.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
  243. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$340'.
  244. Cleaned up 1 empty switch.
  245.  
  246. 4.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
  247. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$447 in module TRELLIS_FF.
  248. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$399 in module DPR16X4C.
  249. Marked 1 switch rules as full_case in process $proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$341 in module TRELLIS_DPR16X4.
  250. Marked 1 switch rules as full_case in process $proc$../../library/wrapper/bram.v:38$452 in module $paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.
  251. Removed a total of 0 dead cases.
  252.  
  253. 4.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
  254. Removed 0 redundant assignments.
  255. Promoted 47 assignments to connections.
  256.  
  257. 4.4.4. Executing PROC_INIT pass (extract init attributes).
  258. Found init rule in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$448'.
  259. Set init value: \Q = 1'0
  260.  
  261. 4.4.5. Executing PROC_ARST pass (detect async resets in processes).
  262.  
  263. 4.4.6. Executing PROC_ROM pass (convert switches to ROMs).
  264. Converted 0 switches.
  265. <suppressed ~5 debug messages>
  266.  
  267. 4.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
  268. Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$448'.
  269. Creating decoders for process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$447'.
  270. 1/1: $0\Q[0:0]
  271. Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  272. Creating decoders for process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$399'.
  273. 1/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$398_EN[3:0]$405
  274. 2/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$398_DATA[3:0]$404
  275. 3/3: $1$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$398_ADDR[3:0]$403
  276. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  277. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$341'.
  278. 1/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$339_EN[3:0]$347
  279. 2/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$339_DATA[3:0]$346
  280. 3/3: $1$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$339_ADDR[3:0]$345
  281. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$340'.
  282. Creating decoders for process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:38$452'.
  283. 1/3: $1$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$458
  284. 2/3: $1$memwr$\mem$../../library/wrapper/bram.v:41$449_DATA[7:0]$457
  285. 3/3: $1$memwr$\mem$../../library/wrapper/bram.v:41$449_ADDR[5:0]$456
  286. Creating decoders for process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:33$451'.
  287.  
  288. 4.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
  289.  
  290. 4.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
  291. Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$447'.
  292. created $dff cell `$procdff$491' with positive edge clock.
  293. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  294. created direct connection (no actual register cell created).
  295. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$383_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  296. created direct connection (no actual register cell created).
  297. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$384_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  298. created direct connection (no actual register cell created).
  299. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$385_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  300. created direct connection (no actual register cell created).
  301. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$386_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  302. created direct connection (no actual register cell created).
  303. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$387_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  304. created direct connection (no actual register cell created).
  305. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$388_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  306. created direct connection (no actual register cell created).
  307. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$389_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  308. created direct connection (no actual register cell created).
  309. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$390_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  310. created direct connection (no actual register cell created).
  311. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$391_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  312. created direct connection (no actual register cell created).
  313. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$392_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  314. created direct connection (no actual register cell created).
  315. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$393_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  316. created direct connection (no actual register cell created).
  317. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$394_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  318. created direct connection (no actual register cell created).
  319. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$395_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  320. created direct connection (no actual register cell created).
  321. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$396_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  322. created direct connection (no actual register cell created).
  323. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:281$397_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  324. created direct connection (no actual register cell created).
  325. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$398_ADDR' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$399'.
  326. created $dff cell `$procdff$492' with positive edge clock.
  327. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$398_DATA' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$399'.
  328. created $dff cell `$procdff$493' with positive edge clock.
  329. Creating register for signal `\DPR16X4C.$memwr$\ram$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:287$398_EN' using process `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$399'.
  330. created $dff cell `$procdff$494' with positive edge clock.
  331. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  332. created direct connection (no actual register cell created).
  333. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$323_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  334. created direct connection (no actual register cell created).
  335. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$324_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  336. created direct connection (no actual register cell created).
  337. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$325_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  338. created direct connection (no actual register cell created).
  339. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$326_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  340. created direct connection (no actual register cell created).
  341. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$327_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  342. created direct connection (no actual register cell created).
  343. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$328_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  344. created direct connection (no actual register cell created).
  345. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$329_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  346. created direct connection (no actual register cell created).
  347. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$330_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  348. created direct connection (no actual register cell created).
  349. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$331_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  350. created direct connection (no actual register cell created).
  351. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$332_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  352. created direct connection (no actual register cell created).
  353. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$333_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  354. created direct connection (no actual register cell created).
  355. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$334_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  356. created direct connection (no actual register cell created).
  357. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$335_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  358. created direct connection (no actual register cell created).
  359. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$336_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  360. created direct connection (no actual register cell created).
  361. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$337_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  362. created direct connection (no actual register cell created).
  363. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:207$338_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  364. created direct connection (no actual register cell created).
  365. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$339_ADDR' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$341'.
  366. created $dff cell `$procdff$495' with positive edge clock.
  367. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$339_DATA' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$341'.
  368. created $dff cell `$procdff$496' with positive edge clock.
  369. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:223$339_EN' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$341'.
  370. created $dff cell `$procdff$497' with positive edge clock.
  371. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$340'.
  372. created direct connection (no actual register cell created).
  373. Creating register for signal `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.\addr_b' using process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:38$452'.
  374. created $dff cell `$procdff$498' with positive edge clock.
  375. Creating register for signal `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$memwr$\mem$../../library/wrapper/bram.v:41$449_ADDR' using process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:38$452'.
  376. created $dff cell `$procdff$499' with positive edge clock.
  377. Creating register for signal `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$memwr$\mem$../../library/wrapper/bram.v:41$449_DATA' using process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:38$452'.
  378. created $dff cell `$procdff$500' with positive edge clock.
  379. Creating register for signal `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$memwr$\mem$../../library/wrapper/bram.v:41$449_EN' using process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:38$452'.
  380. created $dff cell `$procdff$501' with positive edge clock.
  381. Creating register for signal `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.\addr_a' using process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:33$451'.
  382. created $dff cell `$procdff$502' with positive edge clock.
  383.  
  384. 4.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
  385.  
  386. 4.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
  387. Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$448'.
  388. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$447'.
  389. Removing empty process `TRELLIS_FF.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:350$447'.
  390. Removing empty process `DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$422'.
  391. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:285$399'.
  392. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:0$365'.
  393. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:221$341'.
  394. Removing empty process `TRELLIS_DPR16X4.$proc$/usr/local/bin/../share/yosys/ecp5/cells_sim.v:213$340'.
  395. Found and cleaned up 1 empty switch in `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:38$452'.
  396. Removing empty process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:38$452'.
  397. Removing empty process `$paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.$proc$../../library/wrapper/bram.v:33$451'.
  398. Cleaned up 5 empty switches.
  399.  
  400. 4.4.12. Executing OPT_EXPR pass (perform const folding).
  401. Optimizing module $paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.
  402. Optimizing module fifobuffer_6_8_904fcba6bac2ff7d8e3cafd7c89647b407aa349b.
  403. <suppressed ~2 debug messages>
  404. Optimizing module uarttx.
  405. <suppressed ~3 debug messages>
  406. Optimizing module uartrx_3.
  407. <suppressed ~2 debug messages>
  408. Optimizing module uart_core_6_c575f3e383df5c81fb057f50806caf1436554d70.
  409. Optimizing module pll_mac.
  410. Optimizing module versa_ecp5_top.
  411. <suppressed ~1 debug messages>
  412.  
  413. 4.5. Executing FLATTEN pass (flatten design).
  414. Deleting now unused module $paramod$3692047ea82e69e8d302bfe6cd77aeb89ef9392c\bram_2psync.
  415. Deleting now unused module fifobuffer_6_8_904fcba6bac2ff7d8e3cafd7c89647b407aa349b.
  416. Deleting now unused module uarttx.
  417. Deleting now unused module uartrx_3.
  418. Deleting now unused module uart_core_6_c575f3e383df5c81fb057f50806caf1436554d70.
  419. Deleting now unused module pll_mac.
  420. <suppressed ~7 debug messages>
  421.  
  422. 4.6. Executing TRIBUF pass.
  423.  
  424. 4.7. Executing DEMINOUT pass (demote inout ports to input or output).
  425.  
  426. 4.8. Executing OPT_EXPR pass (perform const folding).
  427. Optimizing module versa_ecp5_top.
  428. <suppressed ~1 debug messages>
  429.  
  430. 4.9. Executing OPT_CLEAN pass (remove unused cells and wires).
  431. Finding unused cells or wires in module \versa_ecp5_top..
  432. Removed 28 unused cells and 161 unused wires.
  433. <suppressed ~48 debug messages>
  434.  
  435. 4.10. Executing CHECK pass (checking for obvious problems).
  436. Checking module versa_ecp5_top...
  437. Found and reported 0 problems.
  438.  
  439. 4.11. Executing OPT pass (performing simple optimizations).
  440.  
  441. 4.11.1. Executing OPT_EXPR pass (perform const folding).
  442. Optimizing module versa_ecp5_top.
  443.  
  444. 4.11.2. Executing OPT_MERGE pass (detect identical cells).
  445. Finding identical cells in module `\versa_ecp5_top'.
  446. <suppressed ~39 debug messages>
  447. Removed a total of 13 cells.
  448.  
  449. 4.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  450. Running muxtree optimizer on module \versa_ecp5_top..
  451. Creating internal representation of mux trees.
  452. Evaluating internal representation of mux trees.
  453. Replacing known input bits on port A of cell \59: \uart_idle -> 1'0
  454. Analyzing evaluation results.
  455. Removed 0 multiplexer ports.
  456. <suppressed ~42 debug messages>
  457.  
  458. 4.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  459. Optimizing cells in module \versa_ecp5_top.
  460. Consolidated identical input bits for $mux cell $flatten\uart_inst.\rxfifo.\ram.$procmux$483:
  461. Old ports: A=8'00000000, B=8'11111111, Y=$flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455
  462. New ports: A=1'0, B=1'1, Y=$flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0]
  463. New connections: $flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [7:1] = { $flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\rxfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] }
  464. New ctrl vector for $pmux cell \uart_inst.uart_rx.238: $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$92
  465. Consolidated identical input bits for $mux cell $flatten\uart_inst.\txfifo.\ram.$procmux$483:
  466. Old ports: A=8'00000000, B=8'11111111, Y=$flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455
  467. New ports: A=1'0, B=1'1, Y=$flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0]
  468. New connections: $flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [7:1] = { $flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] $flatten\uart_inst.\txfifo.\ram.$0$memwr$\mem$../../library/wrapper/bram.v:41$449_EN[7:0]$455 [0] }
  469. New ctrl vector for $pmux cell \uart_inst.uart_rx.312: $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$108
  470. New ctrl vector for $pmux cell \uart_inst.uart_tx.388: $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$151
  471. New ctrl vector for $pmux cell \uart_inst.uart_tx.405: $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$148
  472. Optimizing cells in module \versa_ecp5_top.
  473. Performed a total of 6 changes.
  474.  
  475. 4.11.5. Executing OPT_MERGE pass (detect identical cells).
  476. Finding identical cells in module `\versa_ecp5_top'.
  477. <suppressed ~6 debug messages>
  478. Removed a total of 2 cells.
  479.  
  480. 4.11.6. Executing OPT_DFF pass (perform DFF optimizations).
  481.  
  482. 4.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  483. Finding unused cells or wires in module \versa_ecp5_top..
  484. Removed 0 unused cells and 15 unused wires.
  485. <suppressed ~1 debug messages>
  486.  
  487. 4.11.8. Executing OPT_EXPR pass (perform const folding).
  488. Optimizing module versa_ecp5_top.
  489.  
  490. 4.11.9. Rerunning OPT passes. (Maybe there is more to do..)
  491.  
  492. 4.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  493. Running muxtree optimizer on module \versa_ecp5_top..
  494. Creating internal representation of mux trees.
  495. Evaluating internal representation of mux trees.
  496. Analyzing evaluation results.
  497. Removed 0 multiplexer ports.
  498. <suppressed ~43 debug messages>
  499.  
  500. 4.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  501. Optimizing cells in module \versa_ecp5_top.
  502. New ctrl vector for $pmux cell \uart_inst.uart_tx.379: { $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$151 $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$148 $auto$opt_reduce.cc:134:opt_pmux$505 }
  503. Optimizing cells in module \versa_ecp5_top.
  504. Performed a total of 1 changes.
  505.  
  506. 4.11.12. Executing OPT_MERGE pass (detect identical cells).
  507. Finding identical cells in module `\versa_ecp5_top'.
  508. Removed a total of 0 cells.
  509.  
  510. 4.11.13. Executing OPT_DFF pass (perform DFF optimizations).
  511.  
  512. 4.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
  513. Finding unused cells or wires in module \versa_ecp5_top..
  514.  
  515. 4.11.15. Executing OPT_EXPR pass (perform const folding).
  516. Optimizing module versa_ecp5_top.
  517.  
  518. 4.11.16. Rerunning OPT passes. (Maybe there is more to do..)
  519.  
  520. 4.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  521. Running muxtree optimizer on module \versa_ecp5_top..
  522. Creating internal representation of mux trees.
  523. Evaluating internal representation of mux trees.
  524. Analyzing evaluation results.
  525. Removed 0 multiplexer ports.
  526. <suppressed ~43 debug messages>
  527.  
  528. 4.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  529. Optimizing cells in module \versa_ecp5_top.
  530. Performed a total of 0 changes.
  531.  
  532. 4.11.19. Executing OPT_MERGE pass (detect identical cells).
  533. Finding identical cells in module `\versa_ecp5_top'.
  534. Removed a total of 0 cells.
  535.  
  536. 4.11.20. Executing OPT_DFF pass (perform DFF optimizations).
  537.  
  538. 4.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
  539. Finding unused cells or wires in module \versa_ecp5_top..
  540.  
  541. 4.11.22. Executing OPT_EXPR pass (perform const folding).
  542. Optimizing module versa_ecp5_top.
  543.  
  544. 4.11.23. Finished OPT passes. (There is nothing left to do.)
  545.  
  546. 4.12. Executing FSM pass (extract and optimize FSM).
  547.  
  548. 4.12.1. Executing FSM_DETECT pass (finding FSMs in design).
  549. Not marking versa_ecp5_top.uart_inst.rxfifo.state as FSM state register:
  550. Register has an initialization value.
  551. Not marking versa_ecp5_top.uart_inst.txfifo.state as FSM state register:
  552. Register has an initialization value.
  553. Not marking versa_ecp5_top.uart_inst.uart_rx.state as FSM state register:
  554. Register has an initialization value.
  555. Not marking versa_ecp5_top.uart_inst.uart_tx.state as FSM state register:
  556. Register has an initialization value.
  557.  
  558. 4.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
  559.  
  560. 4.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
  561.  
  562. 4.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  563. Finding unused cells or wires in module \versa_ecp5_top..
  564.  
  565. 4.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
  566.  
  567. 4.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
  568.  
  569. 4.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
  570.  
  571. 4.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
  572.  
  573. 4.13. Executing OPT pass (performing simple optimizations).
  574.  
  575. 4.13.1. Executing OPT_EXPR pass (perform const folding).
  576. Optimizing module versa_ecp5_top.
  577.  
  578. 4.13.2. Executing OPT_MERGE pass (detect identical cells).
  579. Finding identical cells in module `\versa_ecp5_top'.
  580. Removed a total of 0 cells.
  581.  
  582. 4.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  583. Running muxtree optimizer on module \versa_ecp5_top..
  584. Creating internal representation of mux trees.
  585. Evaluating internal representation of mux trees.
  586. Analyzing evaluation results.
  587. Removed 0 multiplexer ports.
  588. <suppressed ~43 debug messages>
  589.  
  590. 4.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  591. Optimizing cells in module \versa_ecp5_top.
  592. Performed a total of 0 changes.
  593.  
  594. 4.13.5. Executing OPT_MERGE pass (detect identical cells).
  595. Finding identical cells in module `\versa_ecp5_top'.
  596. Removed a total of 0 cells.
  597.  
  598. 4.13.6. Executing OPT_DFF pass (perform DFF optimizations).
  599. Adding EN signal on uart_inst.uart_tx.432 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$159, Q = \txd_uart).
  600. Adding SRST signal on uart_inst.uart_tx.430 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$158, Q = \uart_inst.txfifo.int_rden, rval = 1'0).
  601. Adding EN signal on uart_inst.uart_tx.429 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$155, Q = \uart_inst.uart_tx.bitcount).
  602. Adding SRST signal on $auto$ff.cc:266:slice$508 ($dffe) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$153, Q = \uart_inst.uart_tx.bitcount, rval = 3'000).
  603. Adding EN signal on uart_inst.uart_tx.427 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$160, Q = \uart_inst.uart_tx.dsr).
  604. Adding EN signal on uart_inst.uart_tx.425 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$143, Q = \uart_inst.uart_tx.state).
  605. Adding SRST signal on $auto$ff.cc:266:slice$515 ($dffe) from module versa_ecp5_top (D = \uart_inst.uart_tx.nextstate, Q = \uart_inst.uart_tx.state, rval = 2'00).
  606. Adding EN signal on uart_inst.uart_rx.341 ($dff) from module versa_ecp5_top (D = { \rxd_uart \uart_inst.uart_rx.dsr [7:1] }, Q = \uart_inst.uart_rx.dsr).
  607. Adding EN signal on uart_inst.uart_rx.339 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$94, Q = \uart_inst.uart_rx.count).
  608. Adding SRST signal on $auto$ff.cc:266:slice$518 ($dffe) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$93, Q = \uart_inst.uart_rx.count, rval = 4'0000).
  609. Adding EN signal on uart_inst.uart_rx.337 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$122, Q = \uart_inst.uart_rx.bitcount).
  610. Adding SRST signal on $auto$ff.cc:266:slice$520 ($dffe) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$120, Q = \uart_inst.uart_rx.bitcount, rval = 3'000).
  611. Adding EN signal on uart_inst.uart_rx.334 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$91, Q = \uart_inst.uart_rx.rxtrigger).
  612. Adding EN signal on uart_inst.uart_rx.331 ($dff) from module versa_ecp5_top (D = \rxd_uart, Q = \uart_inst.uart_rx.rxd).
  613. Adding SRST signal on uart_inst.uart_rx.329 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$110, Q = \uart_inst.uart_rx.state, rval = 2'00).
  614. Adding EN signal on $auto$ff.cc:266:slice$524 ($sdff) from module versa_ecp5_top (D = $flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$109, Q = \uart_inst.uart_rx.state).
  615. Adding SRST signal on uart_inst.txfifo.526 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$202, Q = \uart_inst.txfifo.state, rval = 2'00).
  616. Adding EN signal on $auto$ff.cc:266:slice$532 ($sdff) from module versa_ecp5_top (D = $flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$202, Q = \uart_inst.txfifo.state).
  617. Adding SRST signal on uart_inst.txfifo.525 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$174, Q = \uart_inst.txfifo.optr, rval = 6'000000).
  618. Adding EN signal on $auto$ff.cc:266:slice$542 ($sdff) from module versa_ecp5_top (D = \uart_inst.txfifo.next_optr, Q = \uart_inst.txfifo.optr).
  619. Adding SRST signal on uart_inst.txfifo.524 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$173, Q = \uart_inst.txfifo.iptr, rval = 6'000000).
  620. Adding EN signal on $auto$ff.cc:266:slice$544 ($sdff) from module versa_ecp5_top (D = \uart_inst.txfifo.next_iptr, Q = \uart_inst.txfifo.iptr).
  621. Adding SRST signal on uart_inst.rxfifo.526 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$202, Q = \uart_inst.rxfifo.state, rval = 2'00).
  622. Adding EN signal on $auto$ff.cc:266:slice$546 ($sdff) from module versa_ecp5_top (D = $flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$202, Q = \uart_inst.rxfifo.state).
  623. Adding SRST signal on uart_inst.rxfifo.525 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$174, Q = \uart_inst.rxfifo.optr, rval = 6'000000).
  624. Adding EN signal on $auto$ff.cc:266:slice$556 ($sdff) from module versa_ecp5_top (D = \uart_inst.rxfifo.next_optr, Q = \uart_inst.rxfifo.optr).
  625. Adding SRST signal on uart_inst.rxfifo.524 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$173, Q = \uart_inst.rxfifo.iptr, rval = 6'000000).
  626. Adding EN signal on $auto$ff.cc:266:slice$558 ($sdff) from module versa_ecp5_top (D = \uart_inst.rxfifo.next_iptr, Q = \uart_inst.rxfifo.iptr).
  627. Adding SRST signal on uart_inst.211 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.$auto$ghdl.cc:806:import_module$59, Q = \uart_inst.uart_tx.txclken, rval = 1'0).
  628. Adding SRST signal on uart_inst.210 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.$auto$ghdl.cc:806:import_module$63, Q = \uart_inst.uart_rx.clk16en, rval = 1'0).
  629. Adding SRST signal on uart_inst.209 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.$auto$ghdl.cc:806:import_module$60, Q = \uart_inst.counter, rval = 16'0000000000000000).
  630. Adding EN signal on uart_inst.208 ($dff) from module versa_ecp5_top (D = $flatten\uart_inst.$auto$ghdl.cc:806:import_module$57, Q = \uart_inst.count16).
  631. Adding SRST signal on \98 ($dff) from module versa_ecp5_top (D = { $auto$ghdl.cc:806:import_module$19 $auto$ghdl.cc:806:import_module$20 }, Q = { \uart_inst.txfifo.wren \uart_inst.ctrl.select_uart_rxr }, rval = 2'00).
  632. Adding EN signal on \98 ($dff) from module versa_ecp5_top (D = $auto$ghdl.cc:806:import_module$17, Q = \uart_inst.txfifo.ram.b_write).
  633. Adding SRST signal on $auto$ff.cc:266:slice$576 ($dffe) from module versa_ecp5_top (D = { \uart_data [7] \uart_data [5] }, Q = { \uart_inst.txfifo.ram.b_write [7] \uart_inst.txfifo.ram.b_write [5] }, rval = 2'00).
  634. Adding EN signal on \97 ($dff) from module versa_ecp5_top (D = $auto$ghdl.cc:806:import_module$6, Q = \toggle_led).
  635. Adding SRST signal on \95 ($dff) from module versa_ecp5_top (D = $auto$ghdl.cc:806:import_module$4 [23:0], Q = \counter, rval = 24'000000000000000000000000).
  636. Adding EN signal on \102 ($dff) from module versa_ecp5_top (D = \uart_inst.rxfifo.odata, Q = \uart_data).
  637. Adding SRST signal on \100 ($dff) from module versa_ecp5_top (D = $auto$ghdl.cc:806:import_module$20, Q = \uart_idle, rval = 1'0).
  638.  
  639. 4.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  640. Finding unused cells or wires in module \versa_ecp5_top..
  641. Removed 40 unused cells and 40 unused wires.
  642. <suppressed ~41 debug messages>
  643.  
  644. 4.13.8. Executing OPT_EXPR pass (perform const folding).
  645. Optimizing module versa_ecp5_top.
  646. <suppressed ~3 debug messages>
  647.  
  648. 4.13.9. Rerunning OPT passes. (Maybe there is more to do..)
  649.  
  650. 4.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  651. Running muxtree optimizer on module \versa_ecp5_top..
  652. Creating internal representation of mux trees.
  653. Evaluating internal representation of mux trees.
  654. Analyzing evaluation results.
  655. Removed 0 multiplexer ports.
  656. <suppressed ~28 debug messages>
  657.  
  658. 4.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  659. Optimizing cells in module \versa_ecp5_top.
  660. New ctrl vector for $pmux cell \uart_inst.rxfifo.505: { $flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$184 $flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$183 $flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$188 }
  661. New ctrl vector for $pmux cell \uart_inst.txfifo.505: { $flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$184 $flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$183 $flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$188 }
  662. Optimizing cells in module \versa_ecp5_top.
  663. Performed a total of 2 changes.
  664.  
  665. 4.13.12. Executing OPT_MERGE pass (detect identical cells).
  666. Finding identical cells in module `\versa_ecp5_top'.
  667. <suppressed ~3 debug messages>
  668. Removed a total of 1 cells.
  669.  
  670. 4.13.13. Executing OPT_DFF pass (perform DFF optimizations).
  671.  
  672. 4.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
  673. Finding unused cells or wires in module \versa_ecp5_top..
  674. Removed 0 unused cells and 1 unused wires.
  675. <suppressed ~1 debug messages>
  676.  
  677. 4.13.15. Executing OPT_EXPR pass (perform const folding).
  678. Optimizing module versa_ecp5_top.
  679.  
  680. 4.13.16. Rerunning OPT passes. (Maybe there is more to do..)
  681.  
  682. 4.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  683. Running muxtree optimizer on module \versa_ecp5_top..
  684. Creating internal representation of mux trees.
  685. Evaluating internal representation of mux trees.
  686. Analyzing evaluation results.
  687. Removed 0 multiplexer ports.
  688. <suppressed ~28 debug messages>
  689.  
  690. 4.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  691. Optimizing cells in module \versa_ecp5_top.
  692. Performed a total of 0 changes.
  693.  
  694. 4.13.19. Executing OPT_MERGE pass (detect identical cells).
  695. Finding identical cells in module `\versa_ecp5_top'.
  696. Removed a total of 0 cells.
  697.  
  698. 4.13.20. Executing OPT_DFF pass (perform DFF optimizations).
  699.  
  700. 4.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
  701. Finding unused cells or wires in module \versa_ecp5_top..
  702.  
  703. 4.13.22. Executing OPT_EXPR pass (perform const folding).
  704. Optimizing module versa_ecp5_top.
  705.  
  706. 4.13.23. Finished OPT passes. (There is nothing left to do.)
  707.  
  708. 4.14. Executing WREDUCE pass (reducing word size of cells).
  709. Removed top 8 bits (of 32) from port A of cell versa_ecp5_top.\19 ($add).
  710. Removed top 31 bits (of 32) from port B of cell versa_ecp5_top.\19 ($add).
  711. Removed top 8 bits (of 32) from port Y of cell versa_ecp5_top.\19 ($add).
  712. Removed top 1 bits (of 8) from port B of cell versa_ecp5_top.\43 ($gt).
  713. Removed cell versa_ecp5_top.\49 ($mux).
  714. Removed top 1 bits (of 3) from port B of cell versa_ecp5_top.$auto$opt_dff.cc:195:make_patterns_logic$537 ($ne).
  715. Removed top 1 bits (of 3) from port B of cell versa_ecp5_top.$auto$opt_dff.cc:195:make_patterns_logic$535 ($ne).
  716. Removed top 5 bits (of 6) from port B of cell versa_ecp5_top.uart_inst.txfifo.455 ($add).
  717. Removed top 5 bits (of 6) from port B of cell versa_ecp5_top.uart_inst.txfifo.457 ($add).
  718. Removed top 1 bits (of 2) from port B of cell versa_ecp5_top.uart_inst.txfifo.468 ($eq).
  719. Removed top 1 bits (of 2) from mux cell versa_ecp5_top.uart_inst.txfifo.478 ($mux).
  720. Removed top 1 bits (of 2) from mux cell versa_ecp5_top.uart_inst.txfifo.494 ($mux).
  721. Removed top 5 bits (of 6) from port B of cell versa_ecp5_top.uart_inst.rxfifo.455 ($add).
  722. Removed top 5 bits (of 6) from port B of cell versa_ecp5_top.uart_inst.rxfifo.457 ($add).
  723. Removed top 1 bits (of 2) from port B of cell versa_ecp5_top.uart_inst.rxfifo.468 ($eq).
  724. Removed top 1 bits (of 2) from mux cell versa_ecp5_top.uart_inst.rxfifo.478 ($mux).
  725. Removed top 1 bits (of 2) from mux cell versa_ecp5_top.uart_inst.rxfifo.494 ($mux).
  726. Removed top 1 bits (of 2) from mux cell versa_ecp5_top.uart_inst.uart_tx.359 ($mux).
  727. Removed top 1 bits (of 2) from port B of cell versa_ecp5_top.uart_inst.uart_tx.368 ($eq).
  728. Removed top 1 bits (of 2) from mux cell versa_ecp5_top.uart_inst.uart_tx.373 ($mux).
  729. Removed top 2 bits (of 3) from port B of cell versa_ecp5_top.uart_inst.uart_tx.384 ($add).
  730. Removed top 3 bits (of 4) from port B of cell versa_ecp5_top.uart_inst.uart_rx.236 ($add).
  731. Removed top 1 bits (of 4) from port B of cell versa_ecp5_top.uart_inst.uart_rx.249 ($eq).
  732. Removed top 1 bits (of 2) from mux cell versa_ecp5_top.uart_inst.uart_rx.256 ($mux).
  733. Removed top 1 bits (of 2) from port B of cell versa_ecp5_top.uart_inst.uart_rx.265 ($eq).
  734. Removed top 1 bits (of 3) from port B of cell versa_ecp5_top.$auto$opt_dff.cc:195:make_patterns_logic$549 ($ne).
  735. Removed top 2 bits (of 3) from port B of cell versa_ecp5_top.uart_inst.uart_rx.308 ($add).
  736. Removed top 1 bits (of 3) from port B of cell versa_ecp5_top.$auto$opt_dff.cc:195:make_patterns_logic$551 ($ne).
  737. Removed top 15 bits (of 16) from port B of cell versa_ecp5_top.uart_inst.145 ($add).
  738. Removed top 3 bits (of 4) from port B of cell versa_ecp5_top.uart_inst.138 ($add).
  739. Removed top 12 bits (of 16) from port B of cell versa_ecp5_top.uart_inst.136 ($eq).
  740. Removed top 1 bits (of 8) from wire versa_ecp5_top.$auto$ghdl.cc:806:import_module$17.
  741. Removed top 8 bits (of 32) from wire versa_ecp5_top.$auto$ghdl.cc:806:import_module$4.
  742. Removed top 1 bits (of 2) from wire versa_ecp5_top.$flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$187.
  743. Removed top 1 bits (of 2) from wire versa_ecp5_top.$flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$197.
  744. Removed top 1 bits (of 2) from wire versa_ecp5_top.$flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$187.
  745. Removed top 1 bits (of 2) from wire versa_ecp5_top.$flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$197.
  746. Removed top 1 bits (of 2) from wire versa_ecp5_top.$flatten\uart_inst.\uart_rx.$auto$ghdl.cc:806:import_module$99.
  747. Removed top 1 bits (of 2) from wire versa_ecp5_top.$flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$144.
  748. Removed top 1 bits (of 2) from wire versa_ecp5_top.$flatten\uart_inst.\uart_tx.$auto$ghdl.cc:806:import_module$150.
  749.  
  750. 4.15. Executing PEEPOPT pass (run peephole optimizers).
  751.  
  752. 4.16. Executing OPT_CLEAN pass (remove unused cells and wires).
  753. Finding unused cells or wires in module \versa_ecp5_top..
  754. Removed 0 unused cells and 10 unused wires.
  755. <suppressed ~1 debug messages>
  756.  
  757. 4.17. Executing SHARE pass (SAT-based resource sharing).
  758.  
  759. 4.18. Executing TECHMAP pass (map to technology primitives).
  760.  
  761. 4.18.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/cmp2lut.v
  762. Parsing Verilog input from `/usr/local/bin/../share/yosys/cmp2lut.v' to AST representation.
  763. Generating RTLIL representation for module `\_90_lut_cmp_'.
  764. Successfully finished Verilog frontend.
  765.  
  766. 4.18.2. Continuing TECHMAP pass.
  767. No more expansions possible.
  768. <suppressed ~62 debug messages>
  769.  
  770. 4.19. Executing OPT_EXPR pass (perform const folding).
  771. Optimizing module versa_ecp5_top.
  772.  
  773. 4.20. Executing OPT_CLEAN pass (remove unused cells and wires).
  774. Finding unused cells or wires in module \versa_ecp5_top..
  775.  
  776. 4.21. Executing TECHMAP pass (map to technology primitives).
  777.  
  778. 4.21.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/mul2dsp.v
  779. Parsing Verilog input from `/usr/local/bin/../share/yosys/mul2dsp.v' to AST representation.
  780. Generating RTLIL representation for module `\_80_mul'.
  781. Generating RTLIL representation for module `\_90_soft_mul'.
  782. Successfully finished Verilog frontend.
  783.  
  784. 4.21.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/dsp_map.v
  785. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/dsp_map.v' to AST representation.
  786. Generating RTLIL representation for module `\$__MUL18X18'.
  787. Successfully finished Verilog frontend.
  788.  
  789. 4.21.3. Continuing TECHMAP pass.
  790. No more expansions possible.
  791. <suppressed ~5 debug messages>
  792.  
  793. 4.22. Executing ALUMACC pass (create $alu and $macc cells).
  794. Extracting $alu and $macc cells in module versa_ecp5_top:
  795. creating $macc model for \19 ($add).
  796. creating $macc model for uart_inst.138 ($add).
  797. creating $macc model for uart_inst.145 ($add).
  798. creating $macc model for uart_inst.rxfifo.455 ($add).
  799. creating $macc model for uart_inst.rxfifo.457 ($add).
  800. creating $macc model for uart_inst.txfifo.455 ($add).
  801. creating $macc model for uart_inst.txfifo.457 ($add).
  802. creating $macc model for uart_inst.uart_rx.236 ($add).
  803. creating $macc model for uart_inst.uart_rx.308 ($add).
  804. creating $macc model for uart_inst.uart_tx.384 ($add).
  805. creating $alu model for $macc uart_inst.uart_tx.384.
  806. creating $alu model for $macc uart_inst.uart_rx.308.
  807. creating $alu model for $macc uart_inst.uart_rx.236.
  808. creating $alu model for $macc uart_inst.txfifo.457.
  809. creating $alu model for $macc uart_inst.txfifo.455.
  810. creating $alu model for $macc uart_inst.rxfifo.457.
  811. creating $alu model for $macc uart_inst.rxfifo.455.
  812. creating $alu model for $macc uart_inst.145.
  813. creating $alu model for $macc uart_inst.138.
  814. creating $alu model for $macc \19.
  815. creating $alu model for \43 ($gt): new $alu
  816. creating $alu model for \45 ($lt): new $alu
  817. creating $alu cell for \45: $auto$alumacc.cc:485:replace_alu$603
  818. creating $alu cell for \43: $auto$alumacc.cc:485:replace_alu$608
  819. creating $alu cell for \19: $auto$alumacc.cc:485:replace_alu$613
  820. creating $alu cell for uart_inst.138: $auto$alumacc.cc:485:replace_alu$616
  821. creating $alu cell for uart_inst.145: $auto$alumacc.cc:485:replace_alu$619
  822. creating $alu cell for uart_inst.rxfifo.455: $auto$alumacc.cc:485:replace_alu$622
  823. creating $alu cell for uart_inst.rxfifo.457: $auto$alumacc.cc:485:replace_alu$625
  824. creating $alu cell for uart_inst.txfifo.455: $auto$alumacc.cc:485:replace_alu$628
  825. creating $alu cell for uart_inst.txfifo.457: $auto$alumacc.cc:485:replace_alu$631
  826. creating $alu cell for uart_inst.uart_rx.236: $auto$alumacc.cc:485:replace_alu$634
  827. creating $alu cell for uart_inst.uart_rx.308: $auto$alumacc.cc:485:replace_alu$637
  828. creating $alu cell for uart_inst.uart_tx.384: $auto$alumacc.cc:485:replace_alu$640
  829. created 12 $alu and 0 $macc cells.
  830.  
  831. 4.23. Executing OPT pass (performing simple optimizations).
  832.  
  833. 4.23.1. Executing OPT_EXPR pass (perform const folding).
  834. Optimizing module versa_ecp5_top.
  835.  
  836. 4.23.2. Executing OPT_MERGE pass (detect identical cells).
  837. Finding identical cells in module `\versa_ecp5_top'.
  838. Removed a total of 0 cells.
  839.  
  840. 4.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  841. Running muxtree optimizer on module \versa_ecp5_top..
  842. Creating internal representation of mux trees.
  843. Evaluating internal representation of mux trees.
  844. Analyzing evaluation results.
  845. Removed 0 multiplexer ports.
  846. <suppressed ~27 debug messages>
  847.  
  848. 4.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  849. Optimizing cells in module \versa_ecp5_top.
  850. Performed a total of 0 changes.
  851.  
  852. 4.23.5. Executing OPT_MERGE pass (detect identical cells).
  853. Finding identical cells in module `\versa_ecp5_top'.
  854. <suppressed ~6 debug messages>
  855. Removed a total of 2 cells.
  856.  
  857. 4.23.6. Executing OPT_DFF pass (perform DFF optimizations).
  858.  
  859. 4.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  860. Finding unused cells or wires in module \versa_ecp5_top..
  861. Removed 0 unused cells and 4 unused wires.
  862. <suppressed ~1 debug messages>
  863.  
  864. 4.23.8. Executing OPT_EXPR pass (perform const folding).
  865. Optimizing module versa_ecp5_top.
  866.  
  867. 4.23.9. Rerunning OPT passes. (Maybe there is more to do..)
  868.  
  869. 4.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  870. Running muxtree optimizer on module \versa_ecp5_top..
  871. Creating internal representation of mux trees.
  872. Evaluating internal representation of mux trees.
  873. Analyzing evaluation results.
  874. Removed 0 multiplexer ports.
  875. <suppressed ~27 debug messages>
  876.  
  877. 4.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  878. Optimizing cells in module \versa_ecp5_top.
  879. Performed a total of 0 changes.
  880.  
  881. 4.23.12. Executing OPT_MERGE pass (detect identical cells).
  882. Finding identical cells in module `\versa_ecp5_top'.
  883. Removed a total of 0 cells.
  884.  
  885. 4.23.13. Executing OPT_DFF pass (perform DFF optimizations).
  886.  
  887. 4.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
  888. Finding unused cells or wires in module \versa_ecp5_top..
  889.  
  890. 4.23.15. Executing OPT_EXPR pass (perform const folding).
  891. Optimizing module versa_ecp5_top.
  892.  
  893. 4.23.16. Finished OPT passes. (There is nothing left to do.)
  894.  
  895. 4.24. Executing MEMORY pass.
  896.  
  897. 4.24.1. Executing OPT_MEM pass (optimize memories).
  898. Performed a total of 0 transformations.
  899.  
  900. 4.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
  901. Performed a total of 0 transformations.
  902.  
  903. 4.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  904. Analyzing versa_ecp5_top.uart_inst.rxfifo.ram.mem write port 0.
  905. Analyzing versa_ecp5_top.uart_inst.txfifo.ram.mem write port 0.
  906.  
  907. 4.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
  908.  
  909. 4.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
  910. Checking read port `\uart_inst.rxfifo.ram.mem'[0] in module `\versa_ecp5_top': merging output FF to cell.
  911. Write port 0: non-transparent.
  912. Checking read port `\uart_inst.txfifo.ram.mem'[0] in module `\versa_ecp5_top': no output FF found.
  913. Checking read port address `\uart_inst.txfifo.ram.mem'[0] in module `\versa_ecp5_top': merged address FF to cell.
  914.  
  915. 4.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
  916. Finding unused cells or wires in module \versa_ecp5_top..
  917. Removed 2 unused cells and 15 unused wires.
  918. <suppressed ~10 debug messages>
  919.  
  920. 4.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
  921.  
  922. 4.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
  923. Performed a total of 0 transformations.
  924.  
  925. 4.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
  926. Finding unused cells or wires in module \versa_ecp5_top..
  927.  
  928. 4.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).
  929.  
  930. 4.25. Executing OPT_CLEAN pass (remove unused cells and wires).
  931. Finding unused cells or wires in module \versa_ecp5_top..
  932.  
  933. 4.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
  934. mapping memory versa_ecp5_top.uart_inst.rxfifo.ram.mem via $__TRELLIS_DPR16X4_
  935. Extracted data FF from read port 0 of versa_ecp5_top.uart_inst.rxfifo.ram.mem: $\uart_inst.rxfifo.ram.mem$rdreg[0]
  936. mapping memory versa_ecp5_top.uart_inst.txfifo.ram.mem via $__TRELLIS_DPR16X4_
  937. Extracted addr FF from read port 0 of versa_ecp5_top.uart_inst.txfifo.ram.mem: $\uart_inst.txfifo.ram.mem$rdreg[0]
  938. <suppressed ~892 debug messages>
  939.  
  940. 4.27. Executing TECHMAP pass (map to technology primitives).
  941.  
  942. 4.27.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/lutrams_map.v
  943. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/lutrams_map.v' to AST representation.
  944. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
  945. Successfully finished Verilog frontend.
  946.  
  947. 4.27.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/brams_map.v
  948. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/brams_map.v' to AST representation.
  949. Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
  950. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
  951. Successfully finished Verilog frontend.
  952.  
  953. 4.27.3. Continuing TECHMAP pass.
  954. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
  955. No more expansions possible.
  956. <suppressed ~34 debug messages>
  957.  
  958. 4.28. Executing OPT pass (performing simple optimizations).
  959.  
  960. 4.28.1. Executing OPT_EXPR pass (perform const folding).
  961. Optimizing module versa_ecp5_top.
  962. <suppressed ~49 debug messages>
  963.  
  964. 4.28.2. Executing OPT_MERGE pass (detect identical cells).
  965. Finding identical cells in module `\versa_ecp5_top'.
  966. Removed a total of 0 cells.
  967.  
  968. 4.28.3. Executing OPT_DFF pass (perform DFF optimizations).
  969. Adding SRST signal on $auto$ff.cc:266:slice$510 ($dffe) from module versa_ecp5_top (D = \uart_inst.uart_tx.data [7], Q = \uart_inst.uart_tx.dsr [7], rval = 1'1).
  970.  
  971. 4.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  972. Finding unused cells or wires in module \versa_ecp5_top..
  973. Removed 0 unused cells and 143 unused wires.
  974. <suppressed ~1 debug messages>
  975.  
  976. 4.28.5. Rerunning OPT passes. (Removed registers in this run.)
  977.  
  978. 4.28.6. Executing OPT_EXPR pass (perform const folding).
  979. Optimizing module versa_ecp5_top.
  980.  
  981. 4.28.7. Executing OPT_MERGE pass (detect identical cells).
  982. Finding identical cells in module `\versa_ecp5_top'.
  983. Removed a total of 0 cells.
  984.  
  985. 4.28.8. Executing OPT_DFF pass (perform DFF optimizations).
  986.  
  987. 4.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
  988. Finding unused cells or wires in module \versa_ecp5_top..
  989.  
  990. 4.28.10. Finished fast OPT passes.
  991.  
  992. 4.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
  993.  
  994. 4.30. Executing OPT pass (performing simple optimizations).
  995.  
  996. 4.30.1. Executing OPT_EXPR pass (perform const folding).
  997. Optimizing module versa_ecp5_top.
  998.  
  999. 4.30.2. Executing OPT_MERGE pass (detect identical cells).
  1000. Finding identical cells in module `\versa_ecp5_top'.
  1001. Removed a total of 0 cells.
  1002.  
  1003. 4.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  1004. Running muxtree optimizer on module \versa_ecp5_top..
  1005. Creating internal representation of mux trees.
  1006. Evaluating internal representation of mux trees.
  1007. Analyzing evaluation results.
  1008. Removed 0 multiplexer ports.
  1009. <suppressed ~7 debug messages>
  1010.  
  1011. 4.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  1012. Optimizing cells in module \versa_ecp5_top.
  1013. Consolidated identical input bits for $mux cell \uart_inst.rxfifo.488:
  1014. Old ports: A=2'00, B=2'10, Y=$flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$194
  1015. New ports: A=1'0, B=1'1, Y=$flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$194 [1]
  1016. New connections: $flatten\uart_inst.\rxfifo.$auto$ghdl.cc:806:import_module$194 [0] = 1'0
  1017. Consolidated identical input bits for $mux cell \uart_inst.txfifo.488:
  1018. Old ports: A=2'00, B=2'10, Y=$flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$194
  1019. New ports: A=1'0, B=1'1, Y=$flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$194 [1]
  1020. New connections: $flatten\uart_inst.\txfifo.$auto$ghdl.cc:806:import_module$194 [0] = 1'0
  1021. Optimizing cells in module \versa_ecp5_top.
  1022. Performed a total of 2 changes.
  1023.  
  1024. 4.30.5. Executing OPT_MERGE pass (detect identical cells).
  1025. Finding identical cells in module `\versa_ecp5_top'.
  1026. Removed a total of 0 cells.
  1027.  
  1028. 4.30.6. Executing OPT_DFF pass (perform DFF optimizations).
  1029.  
  1030. 4.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
  1031. Finding unused cells or wires in module \versa_ecp5_top..
  1032.  
  1033. 4.30.8. Executing OPT_EXPR pass (perform const folding).
  1034. Optimizing module versa_ecp5_top.
  1035.  
  1036. 4.30.9. Rerunning OPT passes. (Maybe there is more to do..)
  1037.  
  1038. 4.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
  1039. Running muxtree optimizer on module \versa_ecp5_top..
  1040. Creating internal representation of mux trees.
  1041. Evaluating internal representation of mux trees.
  1042. Analyzing evaluation results.
  1043. Removed 0 multiplexer ports.
  1044. <suppressed ~7 debug messages>
  1045.  
  1046. 4.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  1047. Optimizing cells in module \versa_ecp5_top.
  1048. Performed a total of 0 changes.
  1049.  
  1050. 4.30.12. Executing OPT_MERGE pass (detect identical cells).
  1051. Finding identical cells in module `\versa_ecp5_top'.
  1052. Removed a total of 0 cells.
  1053.  
  1054. 4.30.13. Executing OPT_DFF pass (perform DFF optimizations).
  1055.  
  1056. 4.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
  1057. Finding unused cells or wires in module \versa_ecp5_top..
  1058.  
  1059. 4.30.15. Executing OPT_EXPR pass (perform const folding).
  1060. Optimizing module versa_ecp5_top.
  1061.  
  1062. 4.30.16. Finished OPT passes. (There is nothing left to do.)
  1063.  
  1064. 4.31. Executing TECHMAP pass (map to technology primitives).
  1065.  
  1066. 4.31.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/techmap.v
  1067. Parsing Verilog input from `/usr/local/bin/../share/yosys/techmap.v' to AST representation.
  1068. Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
  1069. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
  1070. Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
  1071. Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
  1072. Generating RTLIL representation for module `\_90_simplemap_various'.
  1073. Generating RTLIL representation for module `\_90_simplemap_registers'.
  1074. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
  1075. Generating RTLIL representation for module `\_90_shift_shiftx'.
  1076. Generating RTLIL representation for module `\_90_fa'.
  1077. Generating RTLIL representation for module `\_90_lcu'.
  1078. Generating RTLIL representation for module `\_90_alu'.
  1079. Generating RTLIL representation for module `\_90_macc'.
  1080. Generating RTLIL representation for module `\_90_alumacc'.
  1081. Generating RTLIL representation for module `\$__div_mod_u'.
  1082. Generating RTLIL representation for module `\$__div_mod_trunc'.
  1083. Generating RTLIL representation for module `\_90_div'.
  1084. Generating RTLIL representation for module `\_90_mod'.
  1085. Generating RTLIL representation for module `\$__div_mod_floor'.
  1086. Generating RTLIL representation for module `\_90_divfloor'.
  1087. Generating RTLIL representation for module `\_90_modfloor'.
  1088. Generating RTLIL representation for module `\_90_pow'.
  1089. Generating RTLIL representation for module `\_90_pmux'.
  1090. Generating RTLIL representation for module `\_90_demux'.
  1091. Generating RTLIL representation for module `\_90_lut'.
  1092. Successfully finished Verilog frontend.
  1093.  
  1094. 4.31.2. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/arith_map.v
  1095. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/arith_map.v' to AST representation.
  1096. Generating RTLIL representation for module `\_80_ecp5_alu'.
  1097. Successfully finished Verilog frontend.
  1098.  
  1099. 4.31.3. Continuing TECHMAP pass.
  1100. Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\_80_ecp5_alu for cells of type $alu.
  1101. Using extmapper simplemap for cells of type $reduce_or.
  1102. Using extmapper simplemap for cells of type $not.
  1103. Using extmapper simplemap for cells of type $or.
  1104. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
  1105. Using extmapper simplemap for cells of type $eq.
  1106. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
  1107. Using template $paramod$dfca81329cbbac01700318224209a5f2318c7128\_80_ecp5_alu for cells of type $alu.
  1108. Using extmapper simplemap for cells of type $and.
  1109. Using extmapper simplemap for cells of type $ne.
  1110. Using extmapper simplemap for cells of type $sdff.
  1111. Using extmapper simplemap for cells of type $dffe.
  1112. Using extmapper simplemap for cells of type $dff.
  1113. Using extmapper simplemap for cells of type $reduce_bool.
  1114. Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_demux for cells of type $demux.
  1115. Using extmapper simplemap for cells of type $reduce_and.
  1116. Using extmapper simplemap for cells of type $sdffce.
  1117. Using extmapper simplemap for cells of type $bmux.
  1118. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
  1119. Using extmapper simplemap for cells of type $logic_not.
  1120. Using extmapper simplemap for cells of type $mux.
  1121. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
  1122. Using extmapper simplemap for cells of type $sdffe.
  1123. Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
  1124. Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux.
  1125. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
  1126. Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ecp5_alu for cells of type $alu.
  1127. Using extmapper simplemap for cells of type $logic_and.
  1128. Using extmapper simplemap for cells of type $logic_or.
  1129. Using extmapper simplemap for cells of type $pos.
  1130. Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
  1131. Using extmapper simplemap for cells of type $xor.
  1132. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
  1133. Using template $paramod\_90_lcu\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
  1134. No more expansions possible.
  1135. <suppressed ~1001 debug messages>
  1136.  
  1137. 4.32. Executing OPT pass (performing simple optimizations).
  1138.  
  1139. 4.32.1. Executing OPT_EXPR pass (perform const folding).
  1140. Optimizing module versa_ecp5_top.
  1141. <suppressed ~1048 debug messages>
  1142.  
  1143. 4.32.2. Executing OPT_MERGE pass (detect identical cells).
  1144. Finding identical cells in module `\versa_ecp5_top'.
  1145. <suppressed ~177 debug messages>
  1146. Removed a total of 59 cells.
  1147.  
  1148. 4.32.3. Executing OPT_DFF pass (perform DFF optimizations).
  1149.  
  1150. 4.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
  1151. Finding unused cells or wires in module \versa_ecp5_top..
  1152. Removed 97 unused cells and 655 unused wires.
  1153. <suppressed ~98 debug messages>
  1154.  
  1155. 4.32.5. Finished fast OPT passes.
  1156.  
  1157. 4.33. Executing OPT_CLEAN pass (remove unused cells and wires).
  1158. Finding unused cells or wires in module \versa_ecp5_top..
  1159.  
  1160. 4.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
  1161.  
  1162. 4.35. Executing TECHMAP pass (map to technology primitives).
  1163.  
  1164. 4.35.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
  1165. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
  1166. Generating RTLIL representation for module `\$_DFF_N_'.
  1167. Generating RTLIL representation for module `\$_DFF_P_'.
  1168. Generating RTLIL representation for module `\$_DFFE_NN_'.
  1169. Generating RTLIL representation for module `\$_DFFE_PN_'.
  1170. Generating RTLIL representation for module `\$_DFFE_NP_'.
  1171. Generating RTLIL representation for module `\$_DFFE_PP_'.
  1172. Generating RTLIL representation for module `\$_DFF_NP0_'.
  1173. Generating RTLIL representation for module `\$_DFF_NP1_'.
  1174. Generating RTLIL representation for module `\$_DFF_PP0_'.
  1175. Generating RTLIL representation for module `\$_DFF_PP1_'.
  1176. Generating RTLIL representation for module `\$_SDFF_NP0_'.
  1177. Generating RTLIL representation for module `\$_SDFF_NP1_'.
  1178. Generating RTLIL representation for module `\$_SDFF_PP0_'.
  1179. Generating RTLIL representation for module `\$_SDFF_PP1_'.
  1180. Generating RTLIL representation for module `\$_DFFE_NP0P_'.
  1181. Generating RTLIL representation for module `\$_DFFE_NP1P_'.
  1182. Generating RTLIL representation for module `\$_DFFE_PP0P_'.
  1183. Generating RTLIL representation for module `\$_DFFE_PP1P_'.
  1184. Generating RTLIL representation for module `\$_DFFE_NP0N_'.
  1185. Generating RTLIL representation for module `\$_DFFE_NP1N_'.
  1186. Generating RTLIL representation for module `\$_DFFE_PP0N_'.
  1187. Generating RTLIL representation for module `\$_DFFE_PP1N_'.
  1188. Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
  1189. Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
  1190. Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
  1191. Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
  1192. Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
  1193. Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
  1194. Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
  1195. Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
  1196. Generating RTLIL representation for module `\$_ALDFF_NP_'.
  1197. Generating RTLIL representation for module `\$_ALDFF_PP_'.
  1198. Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
  1199. Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
  1200. Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
  1201. Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
  1202. Generating RTLIL representation for module `\FD1P3AX'.
  1203. Generating RTLIL representation for module `\FD1P3AY'.
  1204. Generating RTLIL representation for module `\FD1P3BX'.
  1205. Generating RTLIL representation for module `\FD1P3DX'.
  1206. Generating RTLIL representation for module `\FD1P3IX'.
  1207. Generating RTLIL representation for module `\FD1P3JX'.
  1208. Generating RTLIL representation for module `\FD1S3AX'.
  1209. Generating RTLIL representation for module `\FD1S3AY'.
  1210. Generating RTLIL representation for module `\FD1S3BX'.
  1211. Generating RTLIL representation for module `\FD1S3DX'.
  1212. Generating RTLIL representation for module `\FD1S3IX'.
  1213. Generating RTLIL representation for module `\FD1S3JX'.
  1214. Generating RTLIL representation for module `\IFS1P3BX'.
  1215. Generating RTLIL representation for module `\IFS1P3DX'.
  1216. Generating RTLIL representation for module `\IFS1P3IX'.
  1217. Generating RTLIL representation for module `\IFS1P3JX'.
  1218. Generating RTLIL representation for module `\OFS1P3BX'.
  1219. Generating RTLIL representation for module `\OFS1P3DX'.
  1220. Generating RTLIL representation for module `\OFS1P3IX'.
  1221. Generating RTLIL representation for module `\OFS1P3JX'.
  1222. Generating RTLIL representation for module `\IB'.
  1223. Generating RTLIL representation for module `\IBPU'.
  1224. Generating RTLIL representation for module `\IBPD'.
  1225. Generating RTLIL representation for module `\OB'.
  1226. Generating RTLIL representation for module `\OBZ'.
  1227. Generating RTLIL representation for module `\OBZPU'.
  1228. Generating RTLIL representation for module `\OBZPD'.
  1229. Generating RTLIL representation for module `\OBCO'.
  1230. Generating RTLIL representation for module `\BB'.
  1231. Generating RTLIL representation for module `\BBPU'.
  1232. Generating RTLIL representation for module `\BBPD'.
  1233. Generating RTLIL representation for module `\ILVDS'.
  1234. Generating RTLIL representation for module `\OLVDS'.
  1235. Successfully finished Verilog frontend.
  1236.  
  1237. 4.35.2. Continuing TECHMAP pass.
  1238. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
  1239. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
  1240. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFF_P_.
  1241. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
  1242. Using template \$_SDFF_NP0_ for cells of type $_SDFF_NP0_.
  1243. Using template $paramod\$_DFFE_NP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_NP_.
  1244. Using template $paramod\$_DFFE_PN_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PN_.
  1245. Using template $paramod\$_DFFE_NP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_NP_.
  1246. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
  1247. Using template \$_SDFFE_NP0P_ for cells of type $_SDFFE_NP0P_.
  1248. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
  1249. No more expansions possible.
  1250. <suppressed ~298 debug messages>
  1251.  
  1252. 4.36. Executing OPT_EXPR pass (perform const folding).
  1253. Optimizing module versa_ecp5_top.
  1254. <suppressed ~1 debug messages>
  1255.  
  1256. 4.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).
  1257.  
  1258. 4.38. Executing ECP5_GSR pass (implement FF init values).
  1259. Handling GSR in versa_ecp5_top.
  1260.  
  1261. 4.39. Executing ATTRMVCP pass (move or copy attributes).
  1262.  
  1263. 4.40. Executing OPT_CLEAN pass (remove unused cells and wires).
  1264. Finding unused cells or wires in module \versa_ecp5_top..
  1265. Removed 0 unused cells and 772 unused wires.
  1266. <suppressed ~1 debug messages>
  1267.  
  1268. 4.41. Executing TECHMAP pass (map to technology primitives).
  1269.  
  1270. 4.41.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/latches_map.v
  1271. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/latches_map.v' to AST representation.
  1272. Generating RTLIL representation for module `\$_DLATCH_N_'.
  1273. Generating RTLIL representation for module `\$_DLATCH_P_'.
  1274. Successfully finished Verilog frontend.
  1275.  
  1276. 4.41.2. Continuing TECHMAP pass.
  1277. No more expansions possible.
  1278. <suppressed ~4 debug messages>
  1279.  
  1280. 4.42. Executing ABC pass (technology mapping using ABC).
  1281.  
  1282. 4.42.1. Extracting gate netlist of module `\versa_ecp5_top' to `<abc-temp-dir>/input.blif'..
  1283. Extracted 387 gates and 591 wires to a netlist network with 202 inputs and 109 outputs.
  1284.  
  1285. 4.42.1.1. Executing ABC.
  1286. Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
  1287. ABC: ABC command line: "source <abc-temp-dir>/abc.script".
  1288. ABC:
  1289. ABC: + read_blif <abc-temp-dir>/input.blif
  1290. ABC: + read_lut <abc-temp-dir>/lutdefs.txt
  1291. ABC: + strash
  1292. ABC: + &get -n
  1293. ABC: + &fraig -x
  1294. ABC: + &put
  1295. ABC: + scorr
  1296. ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
  1297. ABC: + dc2
  1298. ABC: + dretime
  1299. ABC: + strash
  1300. ABC: + dch -f
  1301. ABC: + if
  1302. ABC: + mfs2
  1303. ABC: + dress <abc-temp-dir>/input.blif
  1304. ABC: Total number of equiv classes = 87.
  1305. ABC: Participating nodes from both networks = 262.
  1306. ABC: Participating nodes from the first network = 120. ( 70.59 % of nodes)
  1307. ABC: Participating nodes from the second network = 142. ( 83.53 % of nodes)
  1308. ABC: Node pairs (any polarity) = 120. ( 70.59 % of names can be moved)
  1309. ABC: Node pairs (same polarity) = 112. ( 65.88 % of names can be moved)
  1310. ABC: Total runtime = 0.03 sec
  1311. ABC: + write_blif <abc-temp-dir>/output.blif
  1312.  
  1313. 4.42.1.2. Re-integrating ABC results.
  1314. ABC RESULTS: $lut cells: 169
  1315. ABC RESULTS: internal signals: 280
  1316. ABC RESULTS: input signals: 202
  1317. ABC RESULTS: output signals: 109
  1318. Removing temp directory.
  1319. Removed 0 unused cells and 424 unused wires.
  1320.  
  1321. 4.43. Executing TECHMAP pass (map to technology primitives).
  1322.  
  1323. 4.43.1. Executing Verilog-2005 frontend: /usr/local/bin/../share/yosys/ecp5/cells_map.v
  1324. Parsing Verilog input from `/usr/local/bin/../share/yosys/ecp5/cells_map.v' to AST representation.
  1325. Generating RTLIL representation for module `\$_DFF_N_'.
  1326. Generating RTLIL representation for module `\$_DFF_P_'.
  1327. Generating RTLIL representation for module `\$_DFFE_NN_'.
  1328. Generating RTLIL representation for module `\$_DFFE_PN_'.
  1329. Generating RTLIL representation for module `\$_DFFE_NP_'.
  1330. Generating RTLIL representation for module `\$_DFFE_PP_'.
  1331. Generating RTLIL representation for module `\$_DFF_NP0_'.
  1332. Generating RTLIL representation for module `\$_DFF_NP1_'.
  1333. Generating RTLIL representation for module `\$_DFF_PP0_'.
  1334. Generating RTLIL representation for module `\$_DFF_PP1_'.
  1335. Generating RTLIL representation for module `\$_SDFF_NP0_'.
  1336. Generating RTLIL representation for module `\$_SDFF_NP1_'.
  1337. Generating RTLIL representation for module `\$_SDFF_PP0_'.
  1338. Generating RTLIL representation for module `\$_SDFF_PP1_'.
  1339. Generating RTLIL representation for module `\$_DFFE_NP0P_'.
  1340. Generating RTLIL representation for module `\$_DFFE_NP1P_'.
  1341. Generating RTLIL representation for module `\$_DFFE_PP0P_'.
  1342. Generating RTLIL representation for module `\$_DFFE_PP1P_'.
  1343. Generating RTLIL representation for module `\$_DFFE_NP0N_'.
  1344. Generating RTLIL representation for module `\$_DFFE_NP1N_'.
  1345. Generating RTLIL representation for module `\$_DFFE_PP0N_'.
  1346. Generating RTLIL representation for module `\$_DFFE_PP1N_'.
  1347. Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
  1348. Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
  1349. Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
  1350. Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
  1351. Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
  1352. Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
  1353. Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
  1354. Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
  1355. Generating RTLIL representation for module `\$_ALDFF_NP_'.
  1356. Generating RTLIL representation for module `\$_ALDFF_PP_'.
  1357. Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
  1358. Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
  1359. Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
  1360. Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
  1361. Generating RTLIL representation for module `\FD1P3AX'.
  1362. Generating RTLIL representation for module `\FD1P3AY'.
  1363. Generating RTLIL representation for module `\FD1P3BX'.
  1364. Generating RTLIL representation for module `\FD1P3DX'.
  1365. Generating RTLIL representation for module `\FD1P3IX'.
  1366. Generating RTLIL representation for module `\FD1P3JX'.
  1367. Generating RTLIL representation for module `\FD1S3AX'.
  1368. Generating RTLIL representation for module `\FD1S3AY'.
  1369. Generating RTLIL representation for module `\FD1S3BX'.
  1370. Generating RTLIL representation for module `\FD1S3DX'.
  1371. Generating RTLIL representation for module `\FD1S3IX'.
  1372. Generating RTLIL representation for module `\FD1S3JX'.
  1373. Generating RTLIL representation for module `\IFS1P3BX'.
  1374. Generating RTLIL representation for module `\IFS1P3DX'.
  1375. Generating RTLIL representation for module `\IFS1P3IX'.
  1376. Generating RTLIL representation for module `\IFS1P3JX'.
  1377. Generating RTLIL representation for module `\OFS1P3BX'.
  1378. Generating RTLIL representation for module `\OFS1P3DX'.
  1379. Generating RTLIL representation for module `\OFS1P3IX'.
  1380. Generating RTLIL representation for module `\OFS1P3JX'.
  1381. Generating RTLIL representation for module `\IB'.
  1382. Generating RTLIL representation for module `\IBPU'.
  1383. Generating RTLIL representation for module `\IBPD'.
  1384. Generating RTLIL representation for module `\OB'.
  1385. Generating RTLIL representation for module `\OBZ'.
  1386. Generating RTLIL representation for module `\OBZPU'.
  1387. Generating RTLIL representation for module `\OBZPD'.
  1388. Generating RTLIL representation for module `\OBCO'.
  1389. Generating RTLIL representation for module `\BB'.
  1390. Generating RTLIL representation for module `\BBPU'.
  1391. Generating RTLIL representation for module `\BBPD'.
  1392. Generating RTLIL representation for module `\ILVDS'.
  1393. Generating RTLIL representation for module `\OLVDS'.
  1394. Generating RTLIL representation for module `\$lut'.
  1395. Successfully finished Verilog frontend.
  1396.  
  1397. 4.43.2. Continuing TECHMAP pass.
  1398. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
  1399. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
  1400. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
  1401. Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut.
  1402. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
  1403. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
  1404. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
  1405. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
  1406. Using template $paramod$ee4b98bad07bc0ced6d708127af2144fc9ba3e00\$lut for cells of type $lut.
  1407. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
  1408. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
  1409. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
  1410. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
  1411. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
  1412. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
  1413. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
  1414. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
  1415. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
  1416. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
  1417. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111000 for cells of type $lut.
  1418. Using template $paramod$c9c145a3c6d085b43407e8d146c4cb593e0f20bb\$lut for cells of type $lut.
  1419. Using template $paramod$415b9dd3a15783ae56c103f189fd8e182f997441\$lut for cells of type $lut.
  1420. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
  1421. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
  1422. Using template $paramod$fedcddf7a4357754b8c2c1b3c873f3560b924a39\$lut for cells of type $lut.
  1423. Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut.
  1424. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
  1425. Using template $paramod$e053a22d78e6bd5ea33183ea69976f0db741be0e\$lut for cells of type $lut.
  1426. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
  1427. Using template $paramod$3d4f386a402395482bb3a56159e7ad913d874bd8\$lut for cells of type $lut.
  1428. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
  1429. Using template $paramod$c89a9a9957c39e979dc74d6b6568a6e2c8127b19\$lut for cells of type $lut.
  1430. Using template $paramod$70e260b11d61c2beb07d1dff789df1caf45cc3d9\$lut for cells of type $lut.
  1431. Using template $paramod$ba05b8a1a425003df083aea0e69541f5cbdc68f2\$lut for cells of type $lut.
  1432. Using template $paramod$5685833deb7a1113d516d214d6ae4bd4024ab19f\$lut for cells of type $lut.
  1433. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut.
  1434. Using template $paramod$71cb81cd7ec213b39129c5f3867d1aa22dffde1b\$lut for cells of type $lut.
  1435. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010100 for cells of type $lut.
  1436. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100011 for cells of type $lut.
  1437. Using template $paramod$06b5f7e5a17024622a77ecd9b5b6f113e0b34c96\$lut for cells of type $lut.
  1438. Using template $paramod$8505fb0f515c3c5732d5f3e31f6468a2a13b0230\$lut for cells of type $lut.
  1439. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
  1440. Using template $paramod$1a73a09a6e092620145558f2f06f2243b658a28f\$lut for cells of type $lut.
  1441. Using template $paramod$0b3372659570d45902474f8e8fd36c71f42c226d\$lut for cells of type $lut.
  1442. Using template $paramod$a21a3d8f63cd41ec182698f6bdd24857b57e32ff\$lut for cells of type $lut.
  1443. Using template $paramod$38f9bf4dd2329347b8471f0a98443dd323386889\$lut for cells of type $lut.
  1444. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011111 for cells of type $lut.
  1445. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
  1446. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
  1447. No more expansions possible.
  1448. <suppressed ~871 debug messages>
  1449.  
  1450. 4.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
  1451. Optimizing LUTs in versa_ecp5_top.
  1452. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  1453. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  1454. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3380.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  1455. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  1456. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3391.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  1457. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  1458. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  1459. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3449.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  1460. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3445.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  1461. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  1462. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  1463. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  1464. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3443.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  1465. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  1466. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3451.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  1467. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  1468. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  1469. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  1470. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3455.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  1471. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3453.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  1472. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3447.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  1473. Optimizing lut $abc$3341$auto$blifparse.cc:525:parse_blif$3457.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  1474. Removed 0 unused cells and 395 unused wires.
  1475.  
  1476. 4.45. Executing AUTONAME pass.
  1477. Renamed 3477 objects in module versa_ecp5_top (31 iterations).
  1478. <suppressed ~567 debug messages>
  1479.  
  1480. 4.46. Executing HIERARCHY pass (managing design hierarchy).
  1481.  
  1482. 4.46.1. Analyzing design hierarchy..
  1483. Top module: \versa_ecp5_top
  1484.  
  1485. 4.46.2. Analyzing design hierarchy..
  1486. Top module: \versa_ecp5_top
  1487. Removed 0 unused modules.
  1488.  
  1489. 4.47. Printing statistics.
  1490.  
  1491. === versa_ecp5_top ===
  1492.  
  1493. Number of wires: 335
  1494. Number of wire bits: 1082
  1495. Number of public wires: 335
  1496. Number of public wire bits: 1082
  1497. Number of memories: 0
  1498. Number of memory bits: 0
  1499. Number of processes: 0
  1500. Number of cells: 406
  1501. CCU2C 40
  1502. EHXPLLL 1
  1503. LUT4 180
  1504. PFUMX 18
  1505. TRELLIS_DPR16X4 16
  1506. TRELLIS_FF 150
  1507. VLO 1
  1508.  
  1509. 4.48. Executing CHECK pass (checking for obvious problems).
  1510. Checking module versa_ecp5_top...
  1511. Found and reported 0 problems.
  1512.  
  1513. 4.49. Executing JSON backend.
  1514.  
  1515. Warnings: 1 unique messages, 2 total
  1516. End of script. Logfile hash: 03056c06bc, CPU: user 0.70s system 0.03s, MEM: 45.56 MB peak
  1517. Yosys 0.28+1 (git sha1 a9c792dce, clang 14.0.0-1ubuntu1 -fPIC -Os)
  1518. Time spent: 27% 16x read_verilog (0 sec), 18% 1x abc (0 sec), ...
  1519. nextpnr-ecp5 --json versa_ecp5_top.json --lpf versa_ecp5.lpf \
  1520. --textcfg versa_ecp5_top.config --um5g-45k --freq 100 --lpf-allow-unconstrained --package CABGA381
  1521. Info: constraining clock net 'clk_in' to 100.00 MHz
  1522. Warning: IO 'twi_sda' is unconstrained in LPF and will be automatically placed
  1523. Warning: IO 'twi_scl' is unconstrained in LPF and will be automatically placed
  1524.  
  1525. Info: Logic utilisation before packing:
  1526. Info: Total LUT4s: 356/43848 0%
  1527. Info: logic LUTs: 180/43848 0%
  1528. Info: carry LUTs: 80/43848 0%
  1529. Info: RAM LUTs: 64/ 5481 1%
  1530. Info: RAMW LUTs: 32/10962 0%
  1531.  
  1532. Info: Total DFFs: 150/43848 0%
  1533.  
  1534. Info: Packing IOs..
  1535. Info: $twi_sda$iobuf_i: twi_sda$const$VCC$506.Y
  1536. Info: $twi_scl$iobuf_i: twi_scl$const$VCC$505.Y
  1537. Info: pin 'txd_uart$tr_io' constrained to Bel 'X36/Y0/PIOB'.
  1538. Info: pin 'segdp$tr_io' constrained to Bel 'X6/Y71/PIOA'.
  1539. Info: pin 'seg[13]$tr_io' constrained to Bel 'X90/Y44/PIOD'.
  1540. Info: pin 'seg[12]$tr_io' constrained to Bel 'X90/Y44/PIOC'.
  1541. Info: pin 'seg[11]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
  1542. Info: pin 'seg[10]$tr_io' constrained to Bel 'X90/Y44/PIOA'.
  1543. Info: pin 'seg[9]$tr_io' constrained to Bel 'X90/Y41/PIOD'.
  1544. Info: pin 'seg[8]$tr_io' constrained to Bel 'X90/Y41/PIOC'.
  1545. Info: pin 'seg[7]$tr_io' constrained to Bel 'X90/Y41/PIOB'.
  1546. Info: pin 'seg[6]$tr_io' constrained to Bel 'X90/Y41/PIOA'.
  1547. Info: pin 'seg[5]$tr_io' constrained to Bel 'X90/Y38/PIOD'.
  1548. Info: pin 'seg[4]$tr_io' constrained to Bel 'X90/Y38/PIOB'.
  1549. Info: pin 'seg[3]$tr_io' constrained to Bel 'X90/Y38/PIOA'.
  1550. Info: pin 'seg[2]$tr_io' constrained to Bel 'X90/Y35/PIOD'.
  1551. Info: pin 'seg[1]$tr_io' constrained to Bel 'X90/Y38/PIOC'.
  1552. Info: pin 'seg[0]$tr_io' constrained to Bel 'X90/Y35/PIOB'.
  1553. Info: pin 'rxd_uart$tr_io' constrained to Bel 'X38/Y0/PIOB'.
  1554. Info: pin 'reset_n$tr_io' constrained to Bel 'X4/Y71/PIOB'.
  1555. Info: pin 'oled[7]$tr_io' constrained to Bel 'X90/Y11/PIOD'.
  1556. Info: pin 'oled[6]$tr_io' constrained to Bel 'X90/Y14/PIOB'.
  1557. Info: pin 'oled[5]$tr_io' constrained to Bel 'X90/Y14/PIOD'.
  1558. Info: pin 'oled[4]$tr_io' constrained to Bel 'X90/Y17/PIOA'.
  1559. Info: pin 'oled[3]$tr_io' constrained to Bel 'X90/Y14/PIOC'.
  1560. Info: pin 'oled[2]$tr_io' constrained to Bel 'X90/Y14/PIOA'.
  1561. Info: pin 'oled[1]$tr_io' constrained to Bel 'X90/Y11/PIOB'.
  1562. Info: pin 'oled[0]$tr_io' constrained to Bel 'X90/Y11/PIOC'.
  1563. Info: pin 'dip_sw[7]$tr_io' constrained to Bel 'X90/Y32/PIOD'.
  1564. Info: pin 'dip_sw[6]$tr_io' constrained to Bel 'X90/Y32/PIOA'.
  1565. Info: pin 'dip_sw[5]$tr_io' constrained to Bel 'X90/Y29/PIOD'.
  1566. Info: pin 'dip_sw[4]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
  1567. Info: pin 'dip_sw[3]$tr_io' constrained to Bel 'X0/Y32/PIOC'.
  1568. Info: pin 'dip_sw[2]$tr_io' constrained to Bel 'X0/Y32/PIOA'.
  1569. Info: pin 'dip_sw[1]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
  1570. Info: pin 'dip_sw[0]$tr_io' constrained to Bel 'X0/Y35/PIOC'.
  1571. Info: pin 'clk_in$tr_io' constrained to Bel 'X0/Y68/PIOC'.
  1572. Info: Packing constants..
  1573. Info: Packing carries...
  1574. Info: Packing LUTs...
  1575. Info: Packing LUT5-7s...
  1576. Info: Packing FFs...
  1577. Info: 81 FFs paired with LUTs.
  1578. Info: Generating derived timing constraints...
  1579. Info: Input frequency of PLL 'clk_pll1.pllinst_0' is constrained to 100.0 MHz
  1580. Info: Derived frequency constraint of 125.0 MHz for net clk_pll1.clkop
  1581. Info: Derived frequency constraint of 25.0 MHz for net mclk
  1582. Info: Derived frequency constraint of 50.0 MHz for net clk_pll1.clkos2
  1583. Info: Derived frequency constraint of 75.0 MHz for net clk_pll1.clkos3
  1584. Info: Promoting globals...
  1585. Info: promoting clock net mclk to global network
  1586. Info: Checksum: 0x699e2513
  1587.  
  1588. Info: Annotating ports with timing budgets for target frequency 100.00 MHz
  1589. ERROR: cell type 'VLO' is unsupported (instantiated as 'clk_pll1.scuba_vlo_inst')
  1590. 2 warnings, 1 error
  1591. make: *** [../ghdlsynth.mk:26: versa_ecp5_top.config] Error 255
  1592. robin@user:~/share/lattice/ghdl-yosys-plugin/examples/ecp5_versa$ ^C
  1593. robin@user:~/share/lattice/ghdl-yosys-plugin/examples/ecp5_versa$ ^C
  1594. robin@user:~/share/lattice/ghdl-yosys-plugin/examples/ecp5_versa$ make clean all > log.txt
  1595. Info: constraining clock net 'clk_in' to 100.00 MHz
  1596. Warning: IO 'twi_sda' is unconstrained in LPF and will be automatically placed
  1597. Warning: IO 'twi_scl' is unconstrained in LPF and will be automatically placed
  1598.  
  1599. Info: Logic utilisation before packing:
  1600. Info: Total LUT4s: 356/43848 0%
  1601. Info: logic LUTs: 180/43848 0%
  1602. Info: carry LUTs: 80/43848 0%
  1603. Info: RAM LUTs: 64/ 5481 1%
  1604. Info: RAMW LUTs: 32/10962 0%
  1605.  
  1606. Info: Total DFFs: 150/43848 0%
  1607.  
  1608. Info: Packing IOs..
  1609. Info: $twi_sda$iobuf_i: twi_sda$const$VCC$506.Y
  1610. Info: $twi_scl$iobuf_i: twi_scl$const$VCC$505.Y
  1611. Info: pin 'txd_uart$tr_io' constrained to Bel 'X36/Y0/PIOB'.
  1612. Info: pin 'segdp$tr_io' constrained to Bel 'X6/Y71/PIOA'.
  1613. Info: pin 'seg[13]$tr_io' constrained to Bel 'X90/Y44/PIOD'.
  1614. Info: pin 'seg[12]$tr_io' constrained to Bel 'X90/Y44/PIOC'.
  1615. Info: pin 'seg[11]$tr_io' constrained to Bel 'X90/Y44/PIOB'.
  1616. Info: pin 'seg[10]$tr_io' constrained to Bel 'X90/Y44/PIOA'.
  1617. Info: pin 'seg[9]$tr_io' constrained to Bel 'X90/Y41/PIOD'.
  1618. Info: pin 'seg[8]$tr_io' constrained to Bel 'X90/Y41/PIOC'.
  1619. Info: pin 'seg[7]$tr_io' constrained to Bel 'X90/Y41/PIOB'.
  1620. Info: pin 'seg[6]$tr_io' constrained to Bel 'X90/Y41/PIOA'.
  1621. Info: pin 'seg[5]$tr_io' constrained to Bel 'X90/Y38/PIOD'.
  1622. Info: pin 'seg[4]$tr_io' constrained to Bel 'X90/Y38/PIOB'.
  1623. Info: pin 'seg[3]$tr_io' constrained to Bel 'X90/Y38/PIOA'.
  1624. Info: pin 'seg[2]$tr_io' constrained to Bel 'X90/Y35/PIOD'.
  1625. Info: pin 'seg[1]$tr_io' constrained to Bel 'X90/Y38/PIOC'.
  1626. Info: pin 'seg[0]$tr_io' constrained to Bel 'X90/Y35/PIOB'.
  1627. Info: pin 'rxd_uart$tr_io' constrained to Bel 'X38/Y0/PIOB'.
  1628. Info: pin 'reset_n$tr_io' constrained to Bel 'X4/Y71/PIOB'.
  1629. Info: pin 'oled[7]$tr_io' constrained to Bel 'X90/Y11/PIOD'.
  1630. Info: pin 'oled[6]$tr_io' constrained to Bel 'X90/Y14/PIOB'.
  1631. Info: pin 'oled[5]$tr_io' constrained to Bel 'X90/Y14/PIOD'.
  1632. Info: pin 'oled[4]$tr_io' constrained to Bel 'X90/Y17/PIOA'.
  1633. Info: pin 'oled[3]$tr_io' constrained to Bel 'X90/Y14/PIOC'.
  1634. Info: pin 'oled[2]$tr_io' constrained to Bel 'X90/Y14/PIOA'.
  1635. Info: pin 'oled[1]$tr_io' constrained to Bel 'X90/Y11/PIOB'.
  1636. Info: pin 'oled[0]$tr_io' constrained to Bel 'X90/Y11/PIOC'.
  1637. Info: pin 'dip_sw[7]$tr_io' constrained to Bel 'X90/Y32/PIOD'.
  1638. Info: pin 'dip_sw[6]$tr_io' constrained to Bel 'X90/Y32/PIOA'.
  1639. Info: pin 'dip_sw[5]$tr_io' constrained to Bel 'X90/Y29/PIOD'.
  1640. Info: pin 'dip_sw[4]$tr_io' constrained to Bel 'X90/Y29/PIOC'.
  1641. Info: pin 'dip_sw[3]$tr_io' constrained to Bel 'X0/Y32/PIOC'.
  1642. Info: pin 'dip_sw[2]$tr_io' constrained to Bel 'X0/Y32/PIOA'.
  1643. Info: pin 'dip_sw[1]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
  1644. Info: pin 'dip_sw[0]$tr_io' constrained to Bel 'X0/Y35/PIOC'.
  1645. Info: pin 'clk_in$tr_io' constrained to Bel 'X0/Y68/PIOC'.
  1646. Info: Packing constants..
  1647. Info: Packing carries...
  1648. Info: Packing LUTs...
  1649. Info: Packing LUT5-7s...
  1650. Info: Packing FFs...
  1651. Info: 81 FFs paired with LUTs.
  1652. Info: Generating derived timing constraints...
  1653. Info: Input frequency of PLL 'clk_pll1.pllinst_0' is constrained to 100.0 MHz
  1654. Info: Derived frequency constraint of 125.0 MHz for net clk_pll1.clkop
  1655. Info: Derived frequency constraint of 25.0 MHz for net mclk
  1656. Info: Derived frequency constraint of 50.0 MHz for net clk_pll1.clkos2
  1657. Info: Derived frequency constraint of 75.0 MHz for net clk_pll1.clkos3
  1658. Info: Promoting globals...
  1659. Info: promoting clock net mclk to global network
  1660. Info: Checksum: 0x699e2513
  1661.  
  1662. Info: Annotating ports with timing budgets for target frequency 100.00 MHz
  1663. ERROR: cell type 'VLO' is unsupported (instantiated as 'clk_pll1.scuba_vlo_inst')
  1664. 2 warnings, 1 error
  1665. make: *** [../ghdlsynth.mk:26: versa_ecp5_top.config] Error 255
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