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- Stuff I would add to the 65C02:
- S16 - Switch into modified SWEET16 mode ( described in another section )
- USX - Use X for the next instruction instead of A
- USY - Use Y for the next instruction instead of A
- USZ - Use a zeropage location for the next instruction instead of A
- DJL zz bb - Decrement zeropage location "zz" and branch to "bb"
- ASL X - X shift left
- LSR X - X shift right
- ROL X - X rotate left
- ROR X - X rotate right
- ASL Y - Y shift left
- LSR Y - Y shift right
- ROL Y - Y rotate left
- ROR Y - Y rotate right
- RND - set A to a random number from 0 to 255
- RND #ii - set A to a random number from 0 to "#ii"
- RND zp - set A to a random number from 0 to "zp"
- NOZ - invert zero flag
- SET x,A - set bit X in accumulator
- RES x,A - reset bit X in accumulator
- TST x,A - test bit X in accumulator
- SZF x,A - copy zero flag to bit X in accumulator
- TST A - set status flags as if A were the result of a calculation
- TST X - set status flags as if X were the result of a calculation
- TST Y - set status flags as if Y were the result of a calculation
- -SWEET16-----------------------------------------------------------------------------------
- uses first 32 bytes of memory for its registers
- R0 - accumulator
- R12 - subroutine return stack
- R13 - compare instruction results
- R14 - prior result (status register)
- R15 - program counter
- Register OPS-
- 1n SET Rn Constant (Set)
- 2n LD Rn (Load)
- 3n ST Rn (Store)
- 4n LD @Rn (Load Indirect)
- 5n ST @Rn (Store Indirect)
- 6n LDD @Rn (Load Double Indirect)
- 7n STD @Rn (Store Double Indirect)
- 8n POP @Rn (Pop Indirect)
- 9n STP @Rn (Store POP Indirect)
- An ADD Rn (Add)
- Bn SUB Rn (Sub)
- Cn POPD @Rn (Pop Double Indirect)
- Dn CPR Rn (Compare)
- En INR Rn (Increment)
- Fn DCR Rn (Decrement)
- Non-register OPS-
- 00 RTN (Return to 6502 mode)
- 01 BR ea (Branch always)
- 02 BNC ea (Branch if No Carry)
- 03 BC ea (Branch if Carry)
- 04 BP ea (Branch if Plus)
- 05 BM ea (Branch if Minus)
- 06 BZ ea (Branch if Zero)
- 07 BNZ ea (Branch if NonZero)
- 08 BM1 ea (Branch if Minus 1)
- 09 BNM1 ea (Branch if Not Minus 1)
- 0A BK (Break)
- 0B RS (Return from Subroutine)
- 0C BS ea (Branch to Subroutine)
- 0D (Unassigned)
- 0E (Unassigned)
- 0F (Unassigned)
- -SWEET16-opcodes-(detail)-----------------------------------------------------------------
- 1n SET Rn Constant (Set)
- The 2-byte constant is loaded into Rn (n=0 to F, Hex) and branch conditions set accordingly. The carry is cleared.
- 2n LD Rn (Load)
- The ACC (R0) is loaded from Rn and branch conditions set according to the data transferred. The carry is cleared and contents of Rn are not disturbed.
- 3n ST Rn (Store)
- The ACC is stored into Rn and branch conditions set according to the data transferred. The carry is cleared and the ACC contents are not disturbed.
- 4n LD @Rn (Load Indirect)
- The low-order ACC byte is loaded from the memory location whose address resides in Rn and the high-order ACC byte is cleared. Branch conditions reflect the final ACC contents which will always be positive and never minus 1. The carry is cleared. After the transfer, Rn is incremented by 1.
- 5n ST @Rn (Store Indirect)
- The low-order ACC byte is stored into the memory location whose address resides in Rn. Branch conditions reflect the 2-byte ACC contents. The carry is cleared. After the transfer Rn is incremented by 1.
- 6n LDD @Rn (Load Double Indirect)
- The low order ACC byte is loaded from memory location whose address resides in Rn, and Rn is then incremented by 1. The high order ACC byte is loaded from the memory location whose address resides in the incremented Rn, and Rn is again incremented by 1. Branch conditions reflect the final ACC contents. The carry is cleared.
- 7n STD @Rn (Store Double Indirect)
- The low-order ACC byte is stored into memory location whose address resides in Rn, and Rn is the incremented by 1. The high-order ACC byte is stored into the memory location whose address resides in the incremented Rn, and Rn is again incremented by 1. Branch conditions reflect the ACC contents which are not disturbed. The carry is cleared.
- 8n POP @Rn (Pop Indirect)
- The low-order ACC byte is loaded from the memory location whose address resides in Rn after Rn is decremented by 1, and the high order ACC byte is cleared. Branch conditions reflect the final 2-byte ACC contents which will always be positive and never minus one. The carry is cleared. Because Rn is decremented prior to loading the ACC, single byte stacks may be implemented with the ST @Rn and POP @Rn ops (Rn is the stack pointer).
- 9n STP @Rn (Store POP Indirect)
- The low-order ACC byte is stored into the memory location whose address resides in Rn after Rn is decremented by 1. Branch conditions will reflect the 2-byte ACC contents which are not modified. STP @Rn and POP @Rn are used together to move data blocks beginning at the greatest address and working down. Additionally, single-byte stacks may be implemented with the STP @Rn ops.
- An ADD Rn (Add)
- The contents of Rn are added to the contents of ACC (R0), and the low-order 16 bits of the sum restored in ACC. the 17th sum bit becomes the carry and the other branch conditions reflect the final ACC contents.
- Bn SUB Rn (Sub)
- The contents of Rn are subtracted from the ACC contents by performing a two's complement addition:
- ACC = ACC + Rn + 1
- The low order 16 bits of the subtraction are restored in the ACC, the 17th sum bit becomes the carry and other branch conditions reflect the final ACC contents. If the 16-bit unsigned ACC contents are greater than or equal to the 16-bit unsigned Rn contents, then the carry is set, otherwise it is cleared. Rn is not disturbed.
- Cn POPD @Rn (Pop Double Indirect)
- Rn is decremented by 1 and the high-order ACC byte is loaded from the memory location whose address now resides in Rn. Rn is again decremented by 1 and the low-order ACC byte is loaded from the corresponding memory location. Branch conditions reflect the final ACC contents. The carry is cleared. Because Rn is decremented prior to loading each of the ACC halves, double-byte stacks may be implemented with the STD @Rn and POPD @Rn ops (Rn is the stack pointer).
- Dn CPR Rn (Compare)
- The ACC (R0) contents are compared to Rn by performing the 16 bit binary subtraction ACC-Rn and storing the low order 16 difference bits in R13 for subsequent branch tests. If the 16 bit unsigned ACC contents are greater than or equal to the 16 bit unsigned Rn contents, then the carry is set, otherwise it is cleared. No other registers, including ACC and Rn, are disturbed.
- En INR Rn (Increment)
- The contents of Rn are incremented by 1. The carry is cleared and other branch conditions reflect the incremented value.
- Fn DCR Rn (Decrement)
- The contents of Rn are decremented by 1. The carry is cleared and other branch conditions reflect the decremented value.
- 00 RTN (Return to 6502 mode)
- 01 BR ea (Branch always)
- An effective address (ea) is calculated by adding the signed displacement byte (d) to the PC. The PC contains the address of the instruction immediately following the BR, or the address of the BR op plus 2. The displacement is a signed two's complement value from -128 to +127. Branch conditions are not changed.
- NOTE: The effective address calculation is identical to that for 6502 relative branches. The Hex add & Subtract features of the APPLE ][ monitor may be used to calculate displacements.
- 02 BNC ea (Branch if No Carry)
- A branch to the effective address is taken only is the carry is clear, otherwise execution resumes as normal with the next instruction. Branch conditions are not changed.
- 03 BC ea (Branch if Carry)
- A branch is effected only if the carry is set. Branch conditions are not changed.
- 04 BP ea (Branch if Plus)
- A branch is effected only if the prior 'result' (or most recently transferred dat) was positive. Branch conditions are not changed.
- 05 BM ea (Branch if Minus)
- A branch is effected only if prior 'result' was minus (negative, MSB = 1). Branch conditions are not changed.
- 06 BZ ea (Branch if Zero)
- A Branch is effected only if the prior 'result' was zero. Branch conditions are not changed.
- 07 BNZ ea (Branch if NonZero)
- A branch is effected only if the priot 'result' was non-zero Branch conditions are not changed.
- 08 BM1 ea (Branch if Minus 1)
- A branch is effected only if the prior 'result' was minus one ($FFFF Hex). Branch conditions are not changed.
- 09 BNM1 ea (Branch if Not Minus 1)
- A branch effected only if the prior 'result' was not minus 1. Branch conditions are not changed.
- 0A BK (Break)
- A 6502 BRK (break) instruction is executed. SWEET 16 may be re-entered non destructively at SW16d after correcting the stack pointer to its value prior to executing the BRK.
- 0B RS (Return from Subroutine)
- RS terminates execution of a SWEET 16 subroutine and returns to the SWEET 16 calling program which resumes execution (in SWEET 16 mode). R12, which is the SWEET 16 subroutine return stack pointer, is decremented twice. Branch conditions are not changed.
- 0C BS ea (Branch to Subroutine)
- A branch to the effective address (PC + 2 + d) is taken and execution is resumed in SWEET 16 mode. The current PC is pushed onto a SWEET 16 subroutine return address stack whose pointer is R12, and R12 is incremented by 2. The carry is cleared and branch conditions set to indicate the current ACC contents.
- 0D (Escape code)
- 0E (Switch into $0D prefix mode, where every opcode acts as if it has the prefix)
- 0F (Unassigned)
- -0D-opcodes------------------------------
- 0D 00 - 0D 0C - Same as normal 01-0C
- 0D 0D END - End prefix mode, if on
- 0D 0E -
- 0D 0F -
- 0D 10 ASL r0 - Shift accumulator left
- 0D 11 LSR r0 - Shift accumulator right
- 0D 12 EX r0, r1 - exchange r0 and r1
- 0D 13 xx xx JP xxxx - BR to 16bit constant
- 0D 14 JS r0 - BS to location in r0
- 0D 15 xx xx JS xxxx - BS to 16bit constant
- 0D 16 -
- 0D 17 -
- 0D 18 -
- 0D 19 -
- 0D 1A -
- 0D 1B -
- 0D 1C -
- 0D 1D -
- 0D 1E -
- 0D 1F -
- 0D 2x zz zz LD [Mem], rX - Store register from memory
- 0D 3x zz zz LD rX, [Mem] - Load register from memory
- 0D 4x zz zz EX rX, [Mem] - Swap register with memory
- 0D 50 xy MOV rX, rY - Copy rY to rX
- 0D 51 xy EX rX, rY - Swap rX with rY
- 0D 52 xy CMP rX, rY - Compare rX with rY
- 0D 53 xy -
- 0D 54 xy PUSH rX, rY - Push rX to stack @rY
- 0D 55 xy POP rX, rY - Pop stack @rY and store to rX
- 0D 56 xy ASL rX, # - Shift rX left by constant
- 0D 47 xy LSR rX, # - Shift rY right by constant
- 0D 48 xy ADD rX, rY - Increase rX by rY
- 0D 49 xy SUB rX, rY - Decrease rX by rY
- 0D 4A xy MUL rX, rY - Multiply rX by rY
- 0D 4B xy DIV rX, rY - Divide rX by rY
- 0D 4C xy MOD rX, rY - Divide rX by rY and store the remainder
- 0D 4D xy AND rX, rY - AND rX with rY
- 0D 4E xy OR rX, rY - OR rX with rY
- 0D 4F xy XOR rX, rY - XOR rX with rY
- 0D 5z xy - Like "0d 5z xy" except rY is indirect
- 0D 6x xy - Like "0d 5z xy" except rX is indirect
- 0D 7x xy - Like "0d 5z xy" except both rX and rY are indirect
- 0D 9x RRR rX - Redirect result into register rX instead of the destination
- 0D 9x RRR @rX - ( Same except indirect )
- 0D Ax CRR rX - Copy result into register rX as well as in the destination
- 0D Bx CRR @rX - ( Same except indirect)
- ( The $0D prefix is implied for the next opcode following one of these four, but if
- followed by $00, then the effects will apply to the opcode after the $00 )
- 0D Cx yyyy SET rX, yyyy - Set rX to constant yyyy
- 0D Dw -
- 0D Ex -
- 0D Fx -
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