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1 | #include "am5729-beagleboneai.dts" | |
2 | #include "bbai-pins.h" // https://pastebin.com/vwn4m7Nf | |
3 | ||
4 | &{/chosen} { | |
5 | - | base_dtb = "bbai-custom.dts"; // <-- name of this file goes here |
5 | + | base_dtb = "bbai-uart5.dts"; // <-- name of this file goes here |
6 | }; | |
7 | ||
8 | ||
9 | &dra7_pmx_core { | |
10 | uart5_pins: uart5 { | |
11 | pinctrl-single,pins = < | |
12 | DRA7XX_CORE_IOPAD( P9_13, PIN_OUTPUT | MUX_MODE4 ) // txd | |
13 | DRA7XX_CORE_IOPAD( P9_11A, PIN_INPUT_PULLUP | MUX_MODE4 ) // rxd | |
14 | DRA7XX_CORE_IOPAD( P9_11B, PIN_OUTPUT | MUX_MODE15 ) // (shared pin) | |
15 | >; | |
16 | }; | |
17 | }; | |
18 | ||
19 | // ttyS4 | |
20 | &uart5 { | |
21 | status = "okay"; | |
22 | pinctrl-names = "default"; | |
23 | pinctrl-0 = <&uart5_pins>; | |
24 | }; | |
25 | ||
26 | ||
27 | // Here's the obnoxious part: since u-boot doesn't have sane pin defaults yet, all pins not | |
28 | // explicitly setup above should be overridden here. This will eventually no longer be needed. | |
29 | &cape_pins_default { | |
30 | pinctrl-single,pins = < | |
31 | // DRA7XX_CORE_IOPAD( P9_11A, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio | |
32 | // DRA7XX_CORE_IOPAD( P9_11B, PIN_INPUT | MUX_MODE14 ) | |
33 | DRA7XX_CORE_IOPAD( P9_12, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
34 | // DRA7XX_CORE_IOPAD( P9_13, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio | |
35 | DRA7XX_CORE_IOPAD( P9_14, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
36 | DRA7XX_CORE_IOPAD( P9_15, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
37 | DRA7XX_CORE_IOPAD( P9_16, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
38 | DRA7XX_CORE_IOPAD( P9_17A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
39 | DRA7XX_CORE_IOPAD( P9_17B, PIN_INPUT | MUX_MODE14 ) | |
40 | DRA7XX_CORE_IOPAD( P9_18A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
41 | DRA7XX_CORE_IOPAD( P9_18B, PIN_INPUT | MUX_MODE14 ) | |
42 | DRA7XX_CORE_IOPAD( P9_19A, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
43 | DRA7XX_CORE_IOPAD( P9_19B, PIN_INPUT | MUX_MODE14 ) | |
44 | DRA7XX_CORE_IOPAD( P9_20A, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
45 | DRA7XX_CORE_IOPAD( P9_20B, PIN_INPUT | MUX_MODE14 ) | |
46 | DRA7XX_CORE_IOPAD( P9_21A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
47 | DRA7XX_CORE_IOPAD( P9_21B, PIN_INPUT | MUX_MODE14 ) | |
48 | DRA7XX_CORE_IOPAD( P9_22A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
49 | DRA7XX_CORE_IOPAD( P9_22B, PIN_INPUT | MUX_MODE14 ) | |
50 | DRA7XX_CORE_IOPAD( P9_23, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
51 | DRA7XX_CORE_IOPAD( P9_24, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
52 | DRA7XX_CORE_IOPAD( P9_25, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
53 | DRA7XX_CORE_IOPAD( P9_26A, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
54 | DRA7XX_CORE_IOPAD( P9_26B, PIN_INPUT | MUX_MODE14 ) | |
55 | DRA7XX_CORE_IOPAD( P9_27A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
56 | DRA7XX_CORE_IOPAD( P9_27B, PIN_INPUT | MUX_MODE14 ) | |
57 | DRA7XX_CORE_IOPAD( P9_28, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
58 | DRA7XX_CORE_IOPAD( P9_29A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
59 | DRA7XX_CORE_IOPAD( P9_29B, PIN_INPUT | MUX_MODE14 ) | |
60 | DRA7XX_CORE_IOPAD( P9_30, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
61 | DRA7XX_CORE_IOPAD( P9_31A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
62 | DRA7XX_CORE_IOPAD( P9_31B, PIN_INPUT | MUX_MODE14 ) | |
63 | DRA7XX_CORE_IOPAD( P9_41A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
64 | DRA7XX_CORE_IOPAD( P9_41B, PIN_INPUT | MUX_MODE14 ) | |
65 | DRA7XX_CORE_IOPAD( P9_42A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
66 | DRA7XX_CORE_IOPAD( P9_42B, PIN_INPUT | MUX_MODE14 ) | |
67 | DRA7XX_CORE_IOPAD( P8_03, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
68 | DRA7XX_CORE_IOPAD( P8_04, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
69 | DRA7XX_CORE_IOPAD( P8_05, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
70 | DRA7XX_CORE_IOPAD( P8_06, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
71 | DRA7XX_CORE_IOPAD( P8_07, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
72 | DRA7XX_CORE_IOPAD( P8_08, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
73 | DRA7XX_CORE_IOPAD( P8_09, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
74 | DRA7XX_CORE_IOPAD( P8_10, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
75 | DRA7XX_CORE_IOPAD( P8_11, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
76 | DRA7XX_CORE_IOPAD( P8_12, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
77 | DRA7XX_CORE_IOPAD( P8_13, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
78 | DRA7XX_CORE_IOPAD( P8_14, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
79 | DRA7XX_CORE_IOPAD( P8_15A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
80 | DRA7XX_CORE_IOPAD( P8_15B, PIN_INPUT | MUX_MODE14 ) | |
81 | DRA7XX_CORE_IOPAD( P8_16, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
82 | DRA7XX_CORE_IOPAD( P8_17, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
83 | DRA7XX_CORE_IOPAD( P8_18, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
84 | DRA7XX_CORE_IOPAD( P8_19, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
85 | DRA7XX_CORE_IOPAD( P8_20, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
86 | DRA7XX_CORE_IOPAD( P8_21, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
87 | DRA7XX_CORE_IOPAD( P8_22, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
88 | DRA7XX_CORE_IOPAD( P8_23, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
89 | DRA7XX_CORE_IOPAD( P8_24, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
90 | DRA7XX_CORE_IOPAD( P8_25, PIN_INPUT_PULLUP | MUX_MODE14 ) | |
91 | DRA7XX_CORE_IOPAD( P8_26, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
92 | DRA7XX_CORE_IOPAD( P8_27A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
93 | DRA7XX_CORE_IOPAD( P8_27B, PIN_INPUT | MUX_MODE14 ) | |
94 | DRA7XX_CORE_IOPAD( P8_28A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
95 | DRA7XX_CORE_IOPAD( P8_28B, PIN_INPUT | MUX_MODE14 ) | |
96 | DRA7XX_CORE_IOPAD( P8_29A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
97 | DRA7XX_CORE_IOPAD( P8_29B, PIN_INPUT | MUX_MODE14 ) | |
98 | DRA7XX_CORE_IOPAD( P8_30A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
99 | DRA7XX_CORE_IOPAD( P8_30B, PIN_INPUT | MUX_MODE14 ) | |
100 | DRA7XX_CORE_IOPAD( P8_31A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
101 | DRA7XX_CORE_IOPAD( P8_31B, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio | |
102 | DRA7XX_CORE_IOPAD( P8_32A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
103 | DRA7XX_CORE_IOPAD( P8_32B, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio | |
104 | DRA7XX_CORE_IOPAD( P8_33A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
105 | DRA7XX_CORE_IOPAD( P8_33B, PIN_INPUT | MUX_MODE14 ) | |
106 | DRA7XX_CORE_IOPAD( P8_34A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
107 | DRA7XX_CORE_IOPAD( P8_34B, PIN_INPUT | MUX_MODE14 ) | |
108 | DRA7XX_CORE_IOPAD( P8_35A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
109 | DRA7XX_CORE_IOPAD( P8_35B, PIN_INPUT | MUX_MODE14 ) | |
110 | DRA7XX_CORE_IOPAD( P8_36A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
111 | DRA7XX_CORE_IOPAD( P8_36B, PIN_INPUT | MUX_MODE14 ) | |
112 | DRA7XX_CORE_IOPAD( P8_37A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
113 | DRA7XX_CORE_IOPAD( P8_37B, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio | |
114 | DRA7XX_CORE_IOPAD( P8_38A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
115 | DRA7XX_CORE_IOPAD( P8_38B, PIN_INPUT_PULLDOWN | MUX_MODE15 ) // note: has no gpio | |
116 | DRA7XX_CORE_IOPAD( P8_39, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
117 | DRA7XX_CORE_IOPAD( P8_40, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
118 | DRA7XX_CORE_IOPAD( P8_41, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
119 | DRA7XX_CORE_IOPAD( P8_42, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
120 | DRA7XX_CORE_IOPAD( P8_43, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
121 | DRA7XX_CORE_IOPAD( P8_44, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
122 | DRA7XX_CORE_IOPAD( P8_45A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
123 | DRA7XX_CORE_IOPAD( P8_45B, PIN_INPUT | MUX_MODE14 ) | |
124 | DRA7XX_CORE_IOPAD( P8_46A, PIN_INPUT_PULLDOWN | MUX_MODE14 ) | |
125 | DRA7XX_CORE_IOPAD( P8_46B, PIN_INPUT | MUX_MODE14 ) | |
126 | >; | |
127 | }; |