lru_tb

`timescale 1ns / 1ps

module lru_tb;

reg clock, rst, en;
reg[31:0] data_in;
wire[31:0] out1, out2, out3, out4, out5, out6, out7, out8;

lru buffer(
    .clk(clock),
    .reset(rst),
    .enable(en),
    .data(data_in),
    .out1(out1),
    .out2(out2),
    .out3(out3),
    .out4(out4),
    .out5(out5),
    .out6(out6),
    .out7(out7),
    .out8(out8)
);

integer i;
integer test[0:20];

initial begin

    test[0] = 20;
    test[1] = 7627;
    test[2] = 777;
    test[3] = 888;
    test[4] = 9999;
    test[5] = 222;
    test[6] = 999;
    test[7] = 4444;
    test[8] = 555;
    test[9] = 7627;
    test[10] = 7627;
    test[11] = 222;
    test[12] = 222;
    test[13] = 222;
    test[14] = 111;
    test[15] = 333;

    clock = 0;
    rst = 0;
    en = 0;
    #5 clock = ~clock;
    #5 clock = ~clock;

    for(i = 0; i < 16; i = i + 1) begin
        data_in = test[i];
        #5 en = 1;
        #5 clock = ~clock;
        #5 en = 0;
        #5 clock = ~clock;
        if (data_in == 555) begin
            $display ("Current state: %d", buffer.state);
        end
        #5 clock = ~clock;
        #5 clock = ~clock;
        if (data_in == 555) begin
            $display ("Current state: %d", buffer.state);
        end
        #5 clock = ~clock;
        #5 clock = ~clock;
        if (data_in == 555) begin
            $display ("Current state: %d", buffer.state);
        end

        $display("inserted %d, out = [%d, %d, %d, %d, %d, %d, %d, %d]", test[i], out1, out2, out3, out4, out5, out6, out7, out8);
    end
    $stop;

end

endmodule