Lab10 - Ej04 - FF T y su Testbench

module FF_T (input clk, reset, output reg Q);

    always @ (posedge clk or posedge reset)
        if (reset)
            Q <= 1'b0;
        else
            Q <= ~Q;

endmodule

module tb();

    reg clk, reset;
    wire Q;

    FF_T DUT(clk, reset, Q);

    initial begin
        $dumpfile("timing.vcd");
        $dumpvars(0, tb);
    end

    initial
        #100 $finish;

    always
        #5 clk = ~clk;

    initial begin
        clk = 0; reset = 0;
        #32
        reset = 1;
        #20
        reset = 0;
    end

endmodule