library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity licznik_modulo_16 is
    Port ( Clk : in  STD_LOGIC;
            switch: in STD_LOGIC_vector(1 downto 0);
           poz1 : out  STD_LOGIC_vector(3 downto 0));
end licznik_modulo_16;

architecture Behavioral of licznik_modulo_16 is
    signal licznik: std_logic_vector(14 downto 0) := "000000000000000";
    signal miejsce: std_logic;
    begin
    process(Clk)
        begin
            if Clk'event and Clk = '1' then
                if switch(0) ='1' then
                    if (switch(1) = '1') then
                        licznik <= licznik+1;
                    else
                        licznik <= licznik-1;
                    end if;
                end if;
            end if;
    end process;
    poz1 <= licznik(14 downto 11);

end Behavioral;