Lab07 - Ej02 - Testbench

`include "fsm_moore.v"

module testbench();

    reg A, B, clk, reset;
    wire Q;
    wire [1:0] state, next_state;

    FSM_moore U1(A, B, clk, reset, Q, state, next_state);

    initial begin
        A = 0; B = 0; clk = 0; reset = 0;
        #2
        reset = 1;
        #1
        reset = 0;
        #5
        A = 1;
        B = 1;
        #30
        B = 0;
        #20
        A = 0;
        #20
        A = 1;
        B = 1;
    end

    initial begin
        $dumpfile("timing.vcd");
        $dumpvars(0, testbench);
    end

    initial
        #150 $finish;

    always
        #5 clk = ~clk;

endmodule